...
> > > > +MODULE_IMPORT_NS(CXL);
> > > > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h
> > > > new file mode 100644
> > > > index ..beb03921e6da
> > > > --- /dev/null
> > > > +++ b/drivers/cxl/pci.h
> > > > @@ -0,0 +1,15 @@
> > > > +// SPDX-License-Identifier: GPL-2.0-only
> >
On Thu, Dec 3, 2020 at 11:22 PM Dan Williams wrote:
>
> On Tue, Nov 17, 2020 at 6:50 AM Jonathan Cameron
> wrote:
> >
> > On Tue, 10 Nov 2020 21:43:50 -0800
> > Ben Widawsky wrote:
> >
> > > From: Dan Williams
> > >
> > > The CXL.mem protocol allows a device to act as a provider of "System
> >
On Tue, Nov 17, 2020 at 6:50 AM Jonathan Cameron
wrote:
>
> On Tue, 10 Nov 2020 21:43:50 -0800
> Ben Widawsky wrote:
>
> > From: Dan Williams
> >
> > The CXL.mem protocol allows a device to act as a provider of "System
> > RAM" and/or "Persistent Memory" that is fully coherent as if the memory
On Tue, 10 Nov 2020 21:43:50 -0800
Ben Widawsky wrote:
> From: Dan Williams
>
> The CXL.mem protocol allows a device to act as a provider of "System
> RAM" and/or "Persistent Memory" that is fully coherent as if the memory
> was attached to the typical CPU memory controller.
>
> The memory
On Wed, Nov 11, 2020 at 09:17:37AM -0800, Dan Williams wrote:
> > > +config CXL_MEM
> > > +tristate "CXL.mem Device Support"
> > > +depends on PCI && CXL_BUS_PROVIDER != n
> >
> > depend on PCI && CXL_BUS_PROVIDER
> >
> > > +default m if CXL_BUS_PROVIDER
> >
> > Please
On Fri, Nov 13, 2020 at 5:09 PM Ben Widawsky wrote:
[..]
> > Unused, maybe move it to the patch that adds the use?
> >
>
> This is a remnant from when Dan gave me the basis to do the mmio work. I agree
> it can be removed now.
Yes.
> > > +static int cxl_mem_dvsec(struct pci_dev *pdev, int
On 20-11-13 12:17:28, Bjorn Helgaas wrote:
> On Tue, Nov 10, 2020 at 09:43:50PM -0800, Ben Widawsky wrote:
> > From: Dan Williams
> >
> > The CXL.mem protocol allows a device to act as a provider of "System
> > RAM" and/or "Persistent Memory" that is fully coherent as if the memory
> > was
On Tue, Nov 10, 2020 at 09:43:50PM -0800, Ben Widawsky wrote:
> From: Dan Williams
>
> The CXL.mem protocol allows a device to act as a provider of "System
> RAM" and/or "Persistent Memory" that is fully coherent as if the memory
> was attached to the typical CPU memory controller.
>
> The
On Wed, Nov 11, 2020 at 1:42 PM Randy Dunlap wrote:
>
> On 11/11/20 9:17 AM, Dan Williams wrote:
> > On Tue, Nov 10, 2020 at 11:12 PM Christoph Hellwig
> > wrote:
> >>
> >> On Tue, Nov 10, 2020 at 09:43:50PM -0800, Ben Widawsky wrote:
> >>> +config CXL_MEM
> >>> +tristate "CXL.mem
On 11/11/20 9:17 AM, Dan Williams wrote:
> On Tue, Nov 10, 2020 at 11:12 PM Christoph Hellwig wrote:
>>
>> On Tue, Nov 10, 2020 at 09:43:50PM -0800, Ben Widawsky wrote:
>>> +config CXL_MEM
>>> +tristate "CXL.mem Device Support"
>>> +depends on PCI && CXL_BUS_PROVIDER != n
>>
>>
On Wed, Nov 11, 2020 at 9:17 AM Dan Williams wrote:
[..]
> > > +
> > > + pci_read_config_word(pdev, pos + PCI_DVSEC_VENDOR_OFFSET,
> > > );
> > > + pci_read_config_word(pdev, pos + PCI_DVSEC_ID_OFFSET, );
> > > + if (vendor == PCI_DVSEC_VENDOR_CXL && dvsec ==
On Tue, Nov 10, 2020 at 11:12 PM Christoph Hellwig wrote:
>
> On Tue, Nov 10, 2020 at 09:43:50PM -0800, Ben Widawsky wrote:
> > +config CXL_MEM
> > +tristate "CXL.mem Device Support"
> > +depends on PCI && CXL_BUS_PROVIDER != n
>
> depend on PCI && CXL_BUS_PROVIDER
>
> > +
On Tue, Nov 10, 2020 at 09:43:50PM -0800, Ben Widawsky wrote:
> +config CXL_MEM
> +tristate "CXL.mem Device Support"
> +depends on PCI && CXL_BUS_PROVIDER != n
depend on PCI && CXL_BUS_PROVIDER
> +default m if CXL_BUS_PROVIDER
Please don't set weird defaults for new
Hi,
On 11/10/20 9:43 PM, Ben Widawsky wrote:
> ---
> drivers/cxl/Kconfig | 20 +++
> drivers/cxl/Makefile | 2 ++
> drivers/cxl/mem.c| 82
> drivers/cxl/pci.h| 15
> 4 files changed, 119 insertions(+)
> diff --git
From: Dan Williams
The CXL.mem protocol allows a device to act as a provider of "System
RAM" and/or "Persistent Memory" that is fully coherent as if the memory
was attached to the typical CPU memory controller.
The memory range exported by the device may optionally be described by
the platform
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