On 2014年10月09日 09:18, Lan Tianyu wrote:
> On 2014年10月09日 04:54, Peter Zijlstra wrote:
>> On Thu, Sep 25, 2014 at 04:32:02PM +0800, Lan Tianyu wrote:
>>> This patchset is to parallel enabling nonboot cpus with resuming devices
>>> during system resume in order to accelerate S2RAM. From test result
On 2014年10月09日 09:18, Lan Tianyu wrote:
On 2014年10月09日 04:54, Peter Zijlstra wrote:
On Thu, Sep 25, 2014 at 04:32:02PM +0800, Lan Tianyu wrote:
This patchset is to parallel enabling nonboot cpus with resuming devices
during system resume in order to accelerate S2RAM. From test result on
a 8
On 2014年10月09日 04:54, Peter Zijlstra wrote:
> On Thu, Sep 25, 2014 at 04:32:02PM +0800, Lan Tianyu wrote:
>> This patchset is to parallel enabling nonboot cpus with resuming devices
>> during system resume in order to accelerate S2RAM. From test result on
>> a 8 logical core Haswell machine,
On Wednesday, October 08, 2014 10:54:41 PM Peter Zijlstra wrote:
> On Thu, Sep 25, 2014 at 04:32:02PM +0800, Lan Tianyu wrote:
> > This patchset is to parallel enabling nonboot cpus with resuming devices
> > during system resume in order to accelerate S2RAM. From test result on
> > a 8 logical
On Thu, Sep 25, 2014 at 04:32:02PM +0800, Lan Tianyu wrote:
> This patchset is to parallel enabling nonboot cpus with resuming devices
> during system resume in order to accelerate S2RAM. From test result on
> a 8 logical core Haswell machine, system resume time reduces from 347ms
> to 217ms with
On Thu, Sep 25, 2014 at 04:32:02PM +0800, Lan Tianyu wrote:
This patchset is to parallel enabling nonboot cpus with resuming devices
during system resume in order to accelerate S2RAM. From test result on
a 8 logical core Haswell machine, system resume time reduces from 347ms
to 217ms with this
On Wednesday, October 08, 2014 10:54:41 PM Peter Zijlstra wrote:
On Thu, Sep 25, 2014 at 04:32:02PM +0800, Lan Tianyu wrote:
This patchset is to parallel enabling nonboot cpus with resuming devices
during system resume in order to accelerate S2RAM. From test result on
a 8 logical core
On 2014年10月09日 04:54, Peter Zijlstra wrote:
On Thu, Sep 25, 2014 at 04:32:02PM +0800, Lan Tianyu wrote:
This patchset is to parallel enabling nonboot cpus with resuming devices
during system resume in order to accelerate S2RAM. From test result on
a 8 logical core Haswell machine, system
This patchset is to parallel enabling nonboot cpus with resuming devices
during system resume in order to accelerate S2RAM. From test result on
a 8 logical core Haswell machine, system resume time reduces from 347ms
to 217ms with this patchset.
In the current world, all nonboot cpus are enabled
This patchset is to parallel enabling nonboot cpus with resuming devices
during system resume in order to accelerate S2RAM. From test result on
a 8 logical core Haswell machine, system resume time reduces from 347ms
to 217ms with this patchset.
In the current world, all nonboot cpus are enabled
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