On Thu, 2021-03-11 at 08:19 +, Marc Zyngier wrote:
> On 2021-03-11 00:05, Pali Rohár wrote:
> > On Wednesday 24 February 2021 14:11:30 Jianjun Wang wrote:
> >> +static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
> >> + unsigned int virq, unsigned
On Wed, 2021-03-10 at 09:41 +, Marc Zyngier wrote:
> On Wed, 10 Mar 2021 06:48:49 +,
> Jianjun Wang wrote:
> > > > +static struct irq_chip mtk_msi_irq_chip = {
> > > > + .name = "MSI",
> > > > + .irq_enable = mtk_pcie_irq_unmask,
> > > > + .irq_disable =
On 2021-03-11 00:05, Pali Rohár wrote:
On Wednesday 24 February 2021 14:11:30 Jianjun Wang wrote:
+static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs,
+ void *arg)
On Wednesday 24 February 2021 14:11:30 Jianjun Wang wrote:
> +static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
> +unsigned int virq, unsigned int nr_irqs,
> +void *arg)
> +{
> + struct mtk_pcie_port *port
Hi Marc,
Thanks for your review.
On Tue, 2021-03-09 at 11:23 +, Marc Zyngier wrote:
> On Wed, 24 Feb 2021 06:11:30 +,
> Jianjun Wang wrote:
> >
> > Add MSI support for MediaTek Gen3 PCIe controller.
> >
> > This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> >
On Wed, 24 Feb 2021 06:11:30 +,
Jianjun Wang wrote:
>
> Add MSI support for MediaTek Gen3 PCIe controller.
>
> This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> block diagram is as follows:
>
> +-+
> | GIC |
>
Hi Krzysztof,
Thanks for your review, I will fix it at next version.
On Wed, 2021-02-24 at 15:31 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
>
> [...]
> > +static struct irq_chip mtk_msi_irq_chip = {
> > + .name = "MSI",
> > + .irq_enable = mtk_pcie_irq_unmask,
> > + .irq_disable =
Hi Jianjun,
[...]
> +static struct irq_chip mtk_msi_irq_chip = {
> + .name = "MSI",
> + .irq_enable = mtk_pcie_irq_unmask,
> + .irq_disable = mtk_pcie_irq_mask,
> + .irq_ack = irq_chip_ack_parent,
> + .irq_mask = mtk_pcie_irq_mask,
> + .irq_unmask = mtk_pcie_irq_unmask,
>
Add MSI support for MediaTek Gen3 PCIe controller.
This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:
+-+
| GIC |
+-+
^
|
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