Re: Pcie bus enumeration and 64bit issues

On Wed, Sep 16, 2015 at 12:08 PM, Ruudgoogle wrote: > > For a big system i use an external pcie enclosure. Unfortunately the bios > fails to properly initialise the system. As work around i plan to start the > chassis after the linux kernel has booted. This leads to some other problems > i

Pcie bus enumeration and 64bit issues

Hello all, For a big system i use an external pcie enclosure. Unfortunately the bios fails to properly initialise the system. As work around i plan to start the chassis after the linux kernel has booted. This leads to some other problems i would like to discuss here/get pointers to kernel

Pcie bus enumeration and 64bit issues

Hello all, For a big system i use an external pcie enclosure. Unfortunately the bios fails to properly initialise the system. As work around i plan to start the chassis after the linux kernel has booted. This leads to some other problems i would like to discuss here/get pointers to kernel

Re: Pcie bus enumeration and 64bit issues

On Wed, Sep 16, 2015 at 12:08 PM, Ruudgoogle wrote: > > For a big system i use an external pcie enclosure. Unfortunately the bios > fails to properly initialise the system. As work around i plan to start the > chassis after the linux kernel has booted. This leads to

Re: PCIe bus enumeration

On Tuesday 08 July 2014 14:27:00 Bjorn Helgaas wrote: > On Tue, Jul 8, 2014 at 1:20 PM, Federico Vaga wrote: > > On Tuesday 08 July 2014 12:23:39 Bjorn Helgaas wrote: > >> On Tue, Jul 8, 2014 at 1:15 AM, Federico Vaga > > > > wrote: > >> >> > So, It looks like that some BIOS disable the bridge

Re: PCIe bus enumeration

On Tuesday 08 July 2014 14:27:00 Bjorn Helgaas wrote: On Tue, Jul 8, 2014 at 1:20 PM, Federico Vaga federico.v...@cern.ch wrote: On Tuesday 08 July 2014 12:23:39 Bjorn Helgaas wrote: On Tue, Jul 8, 2014 at 1:15 AM, Federico Vaga federico.v...@cern.ch wrote: So, It looks like that

Re: PCIe bus enumeration

On Tue, Jul 8, 2014 at 1:20 PM, Federico Vaga wrote: > On Tuesday 08 July 2014 12:23:39 Bjorn Helgaas wrote: >> On Tue, Jul 8, 2014 at 1:15 AM, Federico Vaga > wrote: >> >> > So, It looks like that some BIOS disable the bridge when there >> >> > is >> >> > nothing behind it. Why? Power save? :/

Re: PCIe bus enumeration

On Tuesday 08 July 2014 12:23:39 Bjorn Helgaas wrote: > On Tue, Jul 8, 2014 at 1:15 AM, Federico Vaga wrote: > >> > So, It looks like that some BIOS disable the bridge when there > >> > is > >> > nothing behind it. Why? Power save? :/ > >> > >> Could be power savings, or possibly to conserve

Re: PCIe bus enumeration

On Tue, Jul 8, 2014 at 1:15 AM, Federico Vaga wrote: >> > So, It looks like that some BIOS disable the bridge when there is >> > nothing behind it. Why? Power save? :/ >> >> Could be power savings, or possibly to conserve bus numbers, which >> are a limited resource. > > what is the maximum

Re: PCIe bus enumeration

(I'm changing my email address to the work one. Initially it was just my personal curiosity but now you are helping me with my work, so I think is correct in this way) > > So, It looks like that some BIOS disable the bridge when there is > > nothing behind it. Why? Power save? :/ > > Could be

Re: PCIe bus enumeration

(I'm changing my email address to the work one. Initially it was just my personal curiosity but now you are helping me with my work, so I think is correct in this way) So, It looks like that some BIOS disable the bridge when there is nothing behind it. Why? Power save? :/ Could be power

Re: PCIe bus enumeration

On Tue, Jul 8, 2014 at 1:15 AM, Federico Vaga federico.v...@cern.ch wrote: So, It looks like that some BIOS disable the bridge when there is nothing behind it. Why? Power save? :/ Could be power savings, or possibly to conserve bus numbers, which are a limited resource. what is the

Re: PCIe bus enumeration

On Tuesday 08 July 2014 12:23:39 Bjorn Helgaas wrote: On Tue, Jul 8, 2014 at 1:15 AM, Federico Vaga federico.v...@cern.ch wrote: So, It looks like that some BIOS disable the bridge when there is nothing behind it. Why? Power save? :/ Could be power savings, or possibly to conserve

Re: PCIe bus enumeration

On Tue, Jul 8, 2014 at 1:20 PM, Federico Vaga federico.v...@cern.ch wrote: On Tuesday 08 July 2014 12:23:39 Bjorn Helgaas wrote: On Tue, Jul 8, 2014 at 1:15 AM, Federico Vaga federico.v...@cern.ch wrote: So, It looks like that some BIOS disable the bridge when there is nothing behind

Re: PCIe bus enumeration

On Mon, Jul 7, 2014 at 1:29 AM, Federico Vaga wrote: > On Friday 04 July 2014 15:26:12 Bjorn Helgaas wrote: >> On Fri, Jul 04, 2014 at 09:55:20AM +0200, Federico Vaga wrote: >> > > I assume these ports don't support hotplug. If they *did* >> > > support >> > > hotplug, those ports would have to

Re: PCIe bus enumeration

On Friday 04 July 2014 15:26:12 Bjorn Helgaas wrote: > On Fri, Jul 04, 2014 at 09:55:20AM +0200, Federico Vaga wrote: > > > I assume these ports don't support hotplug. If they *did* > > > support > > > hotplug, those ports would have to exist because they handle the > > > hotplug events (presence

Re: PCIe bus enumeration

On Friday 04 July 2014 15:26:12 Bjorn Helgaas wrote: On Fri, Jul 04, 2014 at 09:55:20AM +0200, Federico Vaga wrote: I assume these ports don't support hotplug. If they *did* support hotplug, those ports would have to exist because they handle the hotplug events (presence detect,

Re: PCIe bus enumeration

On Mon, Jul 7, 2014 at 1:29 AM, Federico Vaga federico.v...@gmail.com wrote: On Friday 04 July 2014 15:26:12 Bjorn Helgaas wrote: On Fri, Jul 04, 2014 at 09:55:20AM +0200, Federico Vaga wrote: I assume these ports don't support hotplug. If they *did* support hotplug, those ports would

Re: PCIe bus enumeration

On Fri, Jul 04, 2014 at 09:55:20AM +0200, Federico Vaga wrote: > > I assume these ports don't support hotplug. If they *did* support > > hotplug, those ports would have to exist because they handle the > > hotplug events (presence detect, etc.) > > I asked: yes, they do not support hotplug > >

Re: PCIe bus enumeration

On Fri, Jul 04, 2014 at 09:55:20AM +0200, Federico Vaga wrote: I assume these ports don't support hotplug. If they *did* support hotplug, those ports would have to exist because they handle the hotplug events (presence detect, etc.) I asked: yes, they do not support hotplug If you

Re: PCIe bus enumeration

On Thu, Jul 3, 2014 at 2:40 PM, Federico Vaga wrote: > On Thursday 03 July 2014 13:43:14 Bjorn Helgaas wrote: >> The /sys/bus/pci/slots/*/address files might help. On my system, I >> have: >> >> $ grep . /sys/bus/pci/slots/*/address /dev/null >> /sys/bus/pci/slots/5/address::03:00 > >

Re: PCIe bus enumeration

(Sorry for double emailing, a sw update changes my configuration to HTML email as default.So, the linux kernel mailing list complains that probably I'm spamming) On Thursday 03 July 2014 13:43:14 Bjorn Helgaas wrote: > On Thu, Jul 3, 2014 at 10:45 AM, Federico Vaga wrote: > > Hello, > > > >

Re: PCIe bus enumeration

On Thu, Jul 3, 2014 at 10:45 AM, Federico Vaga wrote: > Hello, > > (I haven't a deep knowledge of the PCIe specification, maybe I'm just > missing something) > > is there a way to force the PCI subsystem to assign a bus-number to > every PCIe bridge, even if there is nothing connected? > > > My

PCIe bus enumeration

Hello, (I haven't a deep knowledge of the PCIe specification, maybe I'm just missing something) is there a way to force the PCI subsystem to assign a bus-number to every PCIe bridge, even if there is nothing connected? My aim is to have a bus enumeration constant and independent from what I

PCIe bus enumeration

Hello, (I haven't a deep knowledge of the PCIe specification, maybe I'm just missing something) is there a way to force the PCI subsystem to assign a bus-number to every PCIe bridge, even if there is nothing connected? My aim is to have a bus enumeration constant and independent from what I

Re: PCIe bus enumeration

On Thu, Jul 3, 2014 at 10:45 AM, Federico Vaga federico.v...@gmail.com wrote: Hello, (I haven't a deep knowledge of the PCIe specification, maybe I'm just missing something) is there a way to force the PCI subsystem to assign a bus-number to every PCIe bridge, even if there is nothing

Re: PCIe bus enumeration

(Sorry for double emailing, a sw update changes my configuration to HTML email as default.So, the linux kernel mailing list complains that probably I'm spamming) On Thursday 03 July 2014 13:43:14 Bjorn Helgaas wrote: On Thu, Jul 3, 2014 at 10:45 AM, Federico Vaga federico.v...@gmail.com

Re: PCIe bus enumeration

On Thu, Jul 3, 2014 at 2:40 PM, Federico Vaga federico.v...@gmail.com wrote: On Thursday 03 July 2014 13:43:14 Bjorn Helgaas wrote: The /sys/bus/pci/slots/*/address files might help. On my system, I have: $ grep . /sys/bus/pci/slots/*/address /dev/null