oogle.com; gustavo.pimen...@synopsys.com
> Subject: RE: [PATCH] PCI: dwc: Added link up check in map_bus of
> dw_child_pcie_ops
>
> Hi Lorenzo and Richard,
>
> > -Original Message-
> > From: Lorenzo Pieralisi
> > Sent: 2020年10月20日 17:55
> > To: Z.q. Hou
&g
.com;
> gustavo.pimen...@synopsys.com
> Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> dw_child_pcie_ops
>
> On Tue, Oct 20, 2020 at 02:13:13AM +, Z.q. Hou wrote:
>
> [...]
>
> > > > For NXP Layerscape platforms (the ls1028a and ls2088a are also NXP
On Thu, Oct 15, 2020 at 05:47:38PM -0500, Bjorn Helgaas wrote:
> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError in the
> > enumeration of the PCIe controller, which is not connecting
> > with an
On Tue, Oct 20, 2020 at 02:13:13AM +, Z.q. Hou wrote:
[...]
> > > For NXP Layerscape platforms (the ls1028a and ls2088a are also NXP
> > Layerscape platform), as the error response to AXI/AHB was enabled, it will
> > get UR error and trigger SError on AXI bus when it accesses a non-existent
On Fri, Sep 18, 2020 at 09:27:40AM -0600, Rob Herring wrote:
[...]
> > > Maybe a link down just never happens once up, but if so, then we only need
> > > to check it once and fail probe.
> >
> > Many customers connect the FPGA Endpoint, which may establish PCIe link
> > after the PCIe
On Tue, Oct 20, 2020 at 02:13:13AM +, Z.q. Hou wrote:
[...]
> > > For NXP Layerscape platforms (the ls1028a and ls2088a are also NXP
> > Layerscape platform), as the error response to AXI/AHB was enabled, it will
> > get UR error and trigger SError on AXI bus when it accesses a non-existent
Hi Lorenzo,
On 19/10/20 9:43 pm, Lorenzo Pieralisi wrote:
> On Mon, Oct 12, 2020 at 04:41:11AM +, Z.q. Hou wrote:
>
> [...]
>
> Yeah, I don't see any registers in the DRA7x PCIe wrapper for
> disabling error forwarding.
It's a DWC port logic register AFAICT, but perhaps
m;
> gustavo.pimen...@synopsys.com
> Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> dw_child_pcie_ops
>
> Hi Hou,
>
> On 19/10/20 10:54 am, Z.q. Hou wrote:
> > Hello Bjorn,
> >
> > Thanks a lot for your comments!
> >
> >> -
On Thu, Oct 15, 2020 at 05:47:38PM -0500, Bjorn Helgaas wrote:
> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError in the
> > enumeration of the PCIe controller, which is not connecting
> > with an
On Mon, Oct 12, 2020 at 04:41:11AM +, Z.q. Hou wrote:
[...]
> > >> Yeah, I don't see any registers in the DRA7x PCIe wrapper for
> > >> disabling error forwarding.
> > >
> > > It's a DWC port logic register AFAICT, but perhaps not present in all
> > versions.
> >
> > Okay. I see there's a
el.org;
>> r...@kernel.org; lorenzo.pieral...@arm.com; bhelg...@google.com;
>> gustavo.pimen...@synopsys.com
>> Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
>> dw_child_pcie_ops
>>
>> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou
m;
> gustavo.pimen...@synopsys.com
> Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> dw_child_pcie_ops
>
> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError i
On Thu, Oct 15, 2020 at 05:47:38PM -0500, Bjorn Helgaas wrote:
> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError in the
> > enumeration of the PCIe controller, which is not connecting
> > with an
On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> On NXP Layerscape platforms, it results in SError in the
> enumeration of the PCIe controller, which is not connecting
> with an Endpoint device. And it doesn't make sense to
> enumerate the Endpoints when the
On Wed, Oct 14, 2020 at 6:13 AM Lorenzo Pieralisi
wrote:
>
> On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError in the
> > enumeration of the PCIe controller, which is not connecting
> > with an Endpoint
On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> On NXP Layerscape platforms, it results in SError in the
> enumeration of the PCIe controller, which is not connecting
> with an Endpoint device. And it doesn't make sense to
> enumerate the Endpoints when the
On Wed, Sep 16, 2020 at 01:41:30PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> On NXP Layerscape platforms, it results in SError in the
> enumeration of the PCIe controller, which is not connecting
> with an Endpoint device. And it doesn't make sense to
> enumerate the Endpoints when the
Hi Lorenzo,
On 08/10/20 8:38 pm, Lorenzo Pieralisi wrote:
> On Thu, Oct 01, 2020 at 07:02:04PM +0530, Kishon Vijay Abraham I wrote:
>
> [...]
>
Yeah, I don't see any registers in the DRA7x PCIe wrapper for disabling
error forwarding.
>>>
>>> It's a DWC port logic register AFAICT, but
;>>>
> >>>>> Thanks a lot for your comments!
> >>>>>
> >>>>>> -Original Message-
> >>>>>> From: Lorenzo Pieralisi
> >>>>>> Sent: 2020年9月28日 17:39
> >>>>>> To: Z.q
gt;
> > > > -Original Message-
> > > > From: Lorenzo Pieralisi
> > > > Sent: 2020年9月28日 17:39
> > > > To: Z.q. Hou
> > > > Cc: Rob Herring ; linux-kernel@vger.kernel.org;
> > > > PCI ; Bjorn Helgaas
> > &g
On Thu, 8 Oct 2020 at 20:42, Rob Herring wrote:
>
> On Thu, Oct 8, 2020 at 9:47 AM Naresh Kamboju
> wrote:
> >
> > On Fri, 2 Oct 2020 at 14:59, Naresh Kamboju
> > wrote:
> > >
> > > On Thu, 1 Oct 2020 at 22:16, Michael Walle wrote:
> > > >
> > > > Am 2020-10-01 15:32, schrieb Kishon Vijay
On Thu, Oct 8, 2020 at 9:47 AM Naresh Kamboju wrote:
>
> On Fri, 2 Oct 2020 at 14:59, Naresh Kamboju wrote:
> >
> > On Thu, 1 Oct 2020 at 22:16, Michael Walle wrote:
> > >
> > > Am 2020-10-01 15:32, schrieb Kishon Vijay Abraham I:
> > >
> > > > Meanwhile would it be okay to add linkup check
On Thu, Oct 01, 2020 at 07:02:04PM +0530, Kishon Vijay Abraham I wrote:
[...]
> >> Yeah, I don't see any registers in the DRA7x PCIe wrapper for disabling
> >> error forwarding.
> >
> > It's a DWC port logic register AFAICT, but perhaps not present in all
> > versions.
>
> Okay. I see there's
On Fri, 2 Oct 2020 at 14:59, Naresh Kamboju wrote:
>
> On Thu, 1 Oct 2020 at 22:16, Michael Walle wrote:
> >
> > Am 2020-10-01 15:32, schrieb Kishon Vijay Abraham I:
> >
> > > Meanwhile would it be okay to add linkup check atleast for DRA7X so
> > > that
> > > we could have it booting in
On Thu, 1 Oct 2020 at 22:16, Michael Walle wrote:
>
> Am 2020-10-01 15:32, schrieb Kishon Vijay Abraham I:
>
> > Meanwhile would it be okay to add linkup check atleast for DRA7X so
> > that
> > we could have it booting in linux-next?
>
> Layerscape SoCs (at least the LS1028A) are also still
Am 2020-10-01 15:32, schrieb Kishon Vijay Abraham I:
Meanwhile would it be okay to add linkup check atleast for DRA7X so
that
we could have it booting in linux-next?
Layerscape SoCs (at least the LS1028A) are also still broken in
linux-next,
did I miss something here?
-michael
Lorenzo Pieralisi
>>>>>> Sent: 2020年9月28日 17:39
>>>>>> To: Z.q. Hou
>>>>>> Cc: Rob Herring ; linux-kernel@vger.kernel.org; PCI
>>>>>> ; Bjorn Helgaas ;
>>>>>> Gustavo Pimentel ; Michael Walle
>>>>>&
;>>> Cc: Rob Herring ; linux-kernel@vger.kernel.org; PCI
> >>>> ; Bjorn Helgaas ;
> >>>> Gustavo Pimentel ; Michael Walle
> >>>> ; Ard Biesheuvel
> >>>> Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> >>
;> -Original Message-
>>>> From: Lorenzo Pieralisi
>>>> Sent: 2020年9月28日 17:39
>>>> To: Z.q. Hou
>>>> Cc: Rob Herring ; linux-kernel@vger.kernel.org; PCI
>>>> ; Bjorn Helgaas ;
>>>> Gustavo Pimentel ; Michael Wa
gt; > Sent: 2020年9月28日 17:39
> > > To: Z.q. Hou
> > > Cc: Rob Herring ; linux-kernel@vger.kernel.org; PCI
> > > ; Bjorn Helgaas ;
> > > Gustavo Pimentel ; Michael Walle
> > > ; Ard Biesheuvel
> > > Subject: Re: [PATCH] PCI: dwc: Added link u
org; PCI
> > ; Bjorn Helgaas ;
> > Gustavo Pimentel ; Michael Walle
> > ; Ard Biesheuvel
> > Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> > dw_child_pcie_ops
> >
> > On Thu, Sep 24, 2020 at 04:24:47AM +, Z.q. Hou wrote:
> >
; From: Rob Herring
> > > Sent: 2020年9月18日 23:28
> > > To: Z.q. Hou
> > > Cc: linux-kernel@vger.kernel.org; PCI ;
> > > Lorenzo Pieralisi ; Bjorn Helgaas
> > > ; Gustavo Pimentel
> > > ; Michael Walle
> ;
> > > Ard Biesheuvel
>
CI ; Lorenzo
> > Pieralisi ; Bjorn Helgaas
> > ; Gustavo Pimentel
> > ; Michael Walle ;
> > Ard Biesheuvel
> > Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> > dw_child_pcie_ops
> >
> > On Fri, Sep 18, 2020 at 5:02 AM Z.q. Hou wrote:
&
> From: Rob Herring
> > > Sent: 2020年9月17日 4:29
> > > To: Z.q. Hou
> > > Cc: linux-kernel@vger.kernel.org; PCI ;
> > > Lorenzo Pieralisi ; Bjorn Helgaas
> > > ; Gustavo Pimentel
> > > ; Michael Walle
> ;
> > > Ard Biesheuvel
; Ard Biesheuvel
> Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> dw_child_pcie_ops
>
> On Fri, Sep 18, 2020 at 11:02:07AM +, Z.q. Hou wrote:
>
> > But now the SError is exactly caused by the first access of the
> > non-existent function
t; Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> dw_child_pcie_ops
>
> Hi Zhiqiang,
>
> > So the alternative solution seems to correct the PCIe enumeration, I
> > will submit a patch to let the first access only read the Vendor ID.
>
> Please put
o
> > Pieralisi ; Bjorn Helgaas
> > ; Gustavo Pimentel
> > ; Michael Walle ;
> > Ard Biesheuvel
> > Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> > dw_child_pcie_ops
> >
> > On Tue, Sep 15, 2020 at 11:49 PM Zhiqiang Hou
> > w
On Fri, Sep 18, 2020 at 11:02:07AM +, Z.q. Hou wrote:
> But now the SError is exactly caused by the first access of the
> non-existent function, I dug into the kernel enumeration code and
> found it will fire a 4Byte CFG read transaction to read the Vendor
> ID and Device ID together, so I
Hi Zhiqiang,
So the alternative solution seems to correct the PCIe enumeration, I
will submit
a patch to let the first access only read the Vendor ID.
Please put me on CC of that patch.
Thanks,
-michael
> Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> dw_child_pcie_ops
>
> On Tue, Sep 15, 2020 at 11:49 PM Zhiqiang Hou
> wrote:
> >
> > From: Hou Zhiqiang
> >
> > On NXP Layerscape platforms, it results in SError in the enumeration
&g
On Tue, Sep 15, 2020 at 11:49 PM Zhiqiang Hou wrote:
>
> From: Hou Zhiqiang
>
> On NXP Layerscape platforms, it results in SError in the
> enumeration of the PCIe controller, which is not connecting
> with an Endpoint device. And it doesn't make sense to
> enumerate the Endpoints when the PCIe
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