On Sun, May 21, 2017 at 09:09:37PM +0200, Andreas Noever wrote:
> (and of course I have to request
> this at least once: you should definitely release the spec - I highly
> doubt that Intel's competitive advantage depends on keeping this
> linked list technology secret ;) ).
"next year Intel
On Sun, May 21, 2017 at 09:09:37PM +0200, Andreas Noever wrote:
> (and of course I have to request
> this at least once: you should definitely release the spec - I highly
> doubt that Intel's competitive advantage depends on keeping this
> linked list technology secret ;) ).
"next year Intel
On Mon, May 22 2017, 12:45 PM, Mika Westerberg wrote:
> I'm not sure it is good idea to use bit fields here at all. I'm not an expert
> in C
> but I remember reading somewhere that they are not suitable for representing
> fields inside hardware registers.
>
On Mon, May 22 2017, 12:45 PM, Mika Westerberg wrote:
> I'm not sure it is good idea to use bit fields here at all. I'm not an expert
> in C
> but I remember reading somewhere that they are not suitable for representing
> fields inside hardware registers.
>
On Sun, May 21, 2017 at 09:09:37PM +0200, Andreas Noever wrote:
> On Thu, May 18, 2017 at 4:38 PM, Mika Westerberg
> wrote:
> > Organization of the capabilities in switches and ports is not so random
> > after all. Rework the capability handling functionality so
On Sun, May 21, 2017 at 09:09:37PM +0200, Andreas Noever wrote:
> On Thu, May 18, 2017 at 4:38 PM, Mika Westerberg
> wrote:
> > Organization of the capabilities in switches and ports is not so random
> > after all. Rework the capability handling functionality so that it
> > follows how
On Thu, May 18, 2017 at 4:38 PM, Mika Westerberg
wrote:
> Organization of the capabilities in switches and ports is not so random
> after all. Rework the capability handling functionality so that it
> follows how capabilities are organized and provide two new
On Thu, May 18, 2017 at 4:38 PM, Mika Westerberg
wrote:
> Organization of the capabilities in switches and ports is not so random
> after all. Rework the capability handling functionality so that it
> follows how capabilities are organized and provide two new functions
>
On Fri, May 19, 2017 at 11:12 AM, Mika Westerberg
wrote:
> On Thu, May 18, 2017 at 07:38:29PM +0300, Andy Shevchenko wrote:
>> On Thu, May 18, 2017 at 5:38 PM, Mika Westerberg
>> wrote:
>> One nit here.
>> Both has quite similar
On Fri, May 19, 2017 at 11:12 AM, Mika Westerberg
wrote:
> On Thu, May 18, 2017 at 07:38:29PM +0300, Andy Shevchenko wrote:
>> On Thu, May 18, 2017 at 5:38 PM, Mika Westerberg
>> wrote:
>> One nit here.
>> Both has quite similar bodies.
>> Wouldn't be nice to split out a helper which takes
On Thu, May 18, 2017 at 07:38:29PM +0300, Andy Shevchenko wrote:
> On Thu, May 18, 2017 at 5:38 PM, Mika Westerberg
> wrote:
> > Organization of the capabilities in switches and ports is not so random
> > after all. Rework the capability handling functionality so
On Thu, May 18, 2017 at 07:38:29PM +0300, Andy Shevchenko wrote:
> On Thu, May 18, 2017 at 5:38 PM, Mika Westerberg
> wrote:
> > Organization of the capabilities in switches and ports is not so random
> > after all. Rework the capability handling functionality so that it
> > follows how
On Thu, May 18, 2017 at 5:38 PM, Mika Westerberg
wrote:
> Organization of the capabilities in switches and ports is not so random
> after all. Rework the capability handling functionality so that it
> follows how capabilities are organized and provide two new
On Thu, May 18, 2017 at 5:38 PM, Mika Westerberg
wrote:
> Organization of the capabilities in switches and ports is not so random
> after all. Rework the capability handling functionality so that it
> follows how capabilities are organized and provide two new functions
>
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