; Subject: Re: [PATCH v2] x86/resctrl: Fix AMD L3 QOS CDP enable/disable
>
> Hi Babu,
>
> On 11/20/2020 9:25 AM, Babu Moger wrote:
> > When the AMD QoS feature CDP(code and data prioritization) is enabled
> > or disabled, the CDP bit in MSR _0C81 is written on
Hi Babu,
On 11/20/2020 9:25 AM, Babu Moger wrote:
When the AMD QoS feature CDP(code and data prioritization) is enabled
or disabled, the CDP bit in MSR _0C81 is written on one of the
CPUs in L3 domain(core complex). That is not correct. The CDP bit needs
to be updated all the logical CPUs
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