Maybe no contract ... but a bunch of places (many of them in Intel
specific code) that check for it
Interestingly, quite a few of them are actually checking for HYPERVISOR
not because of missing hypervisor features, but rather because
hypervisors don't have to work around certain errata. :)
> I wouldn't expect all hypervisors to necessarily set CPUID.01H:ECX[bit
> 31]. Architecturally, on Intel CPUs, that bit is simply defined as
> "not used." There is no documented contract between Intel and
> hypervisor vendors regarding the use of that bit. (AMD, on the other
> hand, *does*
On Mon, Nov 9, 2020 at 2:57 PM Luck, Tony wrote:
>
> > I thought Linux had long ago gone the route of turning rdmsr/wrmsr
> > into rdmsr_safe/wrmsr_safe, so that the guest would ignore the #GPs on
> > writes and return zero to the caller for #GPs on reads.
>
> Linux just switched that around for
> I thought Linux had long ago gone the route of turning rdmsr/wrmsr
> into rdmsr_safe/wrmsr_safe, so that the guest would ignore the #GPs on
> writes and return zero to the caller for #GPs on reads.
Linux just switched that around for the machine check banks ... if they #GP
fault, then something
On Mon, Nov 9, 2020 at 2:09 PM Luck, Tony wrote:
>
> What does KVM do with model specific MSRs?
"Model specific model-specific registers?" :-)
KVM only implements a small subset of MSRs. By default, any access to
the rest raises #GP.
> Looks like you let the guest believe it was running on one
What does KVM do with model specific MSRs?
Looks like you let the guest believe it was running on one of Sandy Bridge, Ivy
Bridge, Haswell (Xeon).
So, the core MCE code tried to enable extended error reporting.
If there is a mode to have KVM let the guest think that it read/wrote MSR 0x17F,
On Mon, 2020-11-02 at 11:18 +, tip-bot2 for Tony Luck wrote:
> The following commit has been merged into the ras/core branch of tip:
>
> Commit-ID: 68299a42f84288537ee3420c431ac0115ccb90b1
> Gitweb:
> https://git.kernel.org/tip/68299a42f84288537ee3420c431ac0115ccb90b1
> Author:
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