On Fri, Apr 21, 2017 at 02:30:32PM +, Roy Pledge wrote:
> These transactions are done in HW via an ACP port which if I remember
> correctly only supports non coherent transactions. I will need to go
> back and check through email conversations I had with Catalin last
> year when debugging an
On Fri, Apr 21, 2017 at 02:30:32PM +, Roy Pledge wrote:
> These transactions are done in HW via an ACP port which if I remember
> correctly only supports non coherent transactions. I will need to go
> back and check through email conversations I had with Catalin last
> year when debugging an
These transactions are done in HW via an ACP port which if I remember correctly
only supports non coherent transactions. I will need to go back and check
through email conversations I had with Catalin last year when debugging an
issue using this mechanism (cacheable/nonshareable mapping) but
These transactions are done in HW via an ACP port which if I remember correctly
only supports non coherent transactions. I will need to go back and check
through email conversations I had with Catalin last year when debugging an
issue using this mechanism (cacheable/nonshareable mapping) but
Hi,
I notice you missed Catalin and Will from Cc. In future, please ensure
that you Cc them when altering arm64 arch code.
On Thu, Apr 20, 2017 at 03:34:16PM -0400, Haiying Wang wrote:
> NXP arm64 based SoC needs to allocate cacheable and
> non-shareable memory for the software portals of
>
Hi,
I notice you missed Catalin and Will from Cc. In future, please ensure
that you Cc them when altering arm64 arch code.
On Thu, Apr 20, 2017 at 03:34:16PM -0400, Haiying Wang wrote:
> NXP arm64 based SoC needs to allocate cacheable and
> non-shareable memory for the software portals of
>
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