Re: sky2 X86-64 PCI synchronization problems

2007-04-20 Thread Daniel J Blueman
Stephen, From your description of the problem, it sounds just like writes to PCI memory-mapped address space are being delayed and/or reordered in the processor when in x86-64 mode. I'd suggest to add wmb()/rmb() or (overkill) mb() calls after MMIO stores to flush writes immediately and force

Re: sky2 X86-64 PCI synchronization problems

2007-04-20 Thread Daniel J Blueman
Stephen, From your description of the problem, it sounds just like writes to PCI memory-mapped address space are being delayed and/or reordered in the processor when in x86-64 mode. I'd suggest to add wmb()/rmb() or (overkill) mb() calls after MMIO stores to flush writes immediately and force

sky2 X86-64 PCI synchronization problems

2007-04-19 Thread Stephen Hemminger
I am testing a Gigabyte 965P-S3 motherboard with onboard Marvell 88E8056 Ethernet controller (sky2 driver). The CPU is a Core-2 Duo. Strange errors occur under moderate load with X86-64 kernel. Surprisingly, with i386 kernel the controller runs fine without errors. These look bus/PCI related

sky2 X86-64 PCI synchronization problems

2007-04-19 Thread Stephen Hemminger
I am testing a Gigabyte 965P-S3 motherboard with onboard Marvell 88E8056 Ethernet controller (sky2 driver). The CPU is a Core-2 Duo. Strange errors occur under moderate load with X86-64 kernel. Surprisingly, with i386 kernel the controller runs fine without errors. These look bus/PCI related