Dear Arnd,
On Fri, 14 Feb 2014 01:09:44 -0800
Arnd Bergmann wrote:
> On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote:
> > Hi all,
> >
> > The writel/readl is too expensive especially on Cortex A9 w/ outer L2
> > cache. This introduce i2c read/write error on Marvell Berlin SoCs when
> >
On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote:
> Hi all,
>
> The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache.
> This
> introduce i2c read/write error on Marvell Berlin SoCs when there are L2 cache
> maintenance operations at the same time.
>
> In our
On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote:
Hi all,
The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache.
This
introduce i2c read/write error on Marvell Berlin SoCs when there are L2 cache
maintenance operations at the same time.
In our internal
Dear Arnd,
On Fri, 14 Feb 2014 01:09:44 -0800
Arnd Bergmann a...@arndb.de wrote:
On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote:
Hi all,
The writel/readl is too expensive especially on Cortex A9 w/ outer L2
cache. This introduce i2c read/write error on Marvell Berlin SoCs when
Hi all,
The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache.
This
introduce i2c read/write error on Marvell Berlin SoCs when there are L2 cache
maintenance operations at the same time.
In our internal berlin bsp, we just replaced readl/writel with the relaxed
version.
Hi all,
The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache.
This
introduce i2c read/write error on Marvell Berlin SoCs when there are L2 cache
maintenance operations at the same time.
In our internal berlin bsp, we just replaced readl/writel with the relaxed
version.
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