Re: use {readl|writel}_relaxed instead of readl/writel in i2c-designware-core ?

2014-02-14 Thread Jisheng Zhang
Dear Arnd, On Fri, 14 Feb 2014 01:09:44 -0800 Arnd Bergmann wrote: > On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote: > > Hi all, > > > > The writel/readl is too expensive especially on Cortex A9 w/ outer L2 > > cache. This introduce i2c read/write error on Marvell Berlin SoCs when > >

Re: use {readl|writel}_relaxed instead of readl/writel in i2c-designware-core ?

2014-02-14 Thread Arnd Bergmann
On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote: > Hi all, > > The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache. > This > introduce i2c read/write error on Marvell Berlin SoCs when there are L2 cache > maintenance operations at the same time. > > In our

Re: use {readl|writel}_relaxed instead of readl/writel in i2c-designware-core ?

2014-02-14 Thread Arnd Bergmann
On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote: Hi all, The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache. This introduce i2c read/write error on Marvell Berlin SoCs when there are L2 cache maintenance operations at the same time. In our internal

Re: use {readl|writel}_relaxed instead of readl/writel in i2c-designware-core ?

2014-02-14 Thread Jisheng Zhang
Dear Arnd, On Fri, 14 Feb 2014 01:09:44 -0800 Arnd Bergmann a...@arndb.de wrote: On Friday 14 February 2014 15:54:38 Jisheng Zhang wrote: Hi all, The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache. This introduce i2c read/write error on Marvell Berlin SoCs when

use {readl|writel}_relaxed instead of readl/writel in i2c-designware-core ?

2014-02-13 Thread Jisheng Zhang
Hi all, The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache. This introduce i2c read/write error on Marvell Berlin SoCs when there are L2 cache maintenance operations at the same time. In our internal berlin bsp, we just replaced readl/writel with the relaxed version.

use {readl|writel}_relaxed instead of readl/writel in i2c-designware-core ?

2014-02-13 Thread Jisheng Zhang
Hi all, The writel/readl is too expensive especially on Cortex A9 w/ outer L2 cache. This introduce i2c read/write error on Marvell Berlin SoCs when there are L2 cache maintenance operations at the same time. In our internal berlin bsp, we just replaced readl/writel with the relaxed version.