On 9/18/14, 12:53 PM, Arnaldo Carvalho de Melo wrote:
If nobody objects I'll merge this patch, as it fixes problems, but I
wonder if the best wouldn't be simply not calling
perf_evlist__mmap_consume() till the last event there is in fact
consumed... I.e. as we _really_ consume the events, we
The following patch removes some kzalloc-related macros and rewrites the
associated null tests to use !x rather than x == NULL. The complete
semantic patch used for this transformation is as follows:
// smpl
@disable unlikely@
expression ptr;
statement S,S1;
@@
From: Julia Lawall julia.law...@lip6.fr
This patch removes some kzalloc-related macros and rewrites the
associated null tests to use !x rather than x == NULL.
A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)
// smpl
@@
expression ptr;
On 9/18/14, 2:21 PM, David Ahern wrote:
On 9/18/14, 12:53 PM, Arnaldo Carvalho de Melo wrote:
If nobody objects I'll merge this patch, as it fixes problems, but I
wonder if the best wouldn't be simply not calling
perf_evlist__mmap_consume() till the last event there is in fact
consumed... I.e.
On 09/12, Aaron Tomlin wrote:
Tasks get their end of stack set to STACK_END_MAGIC with the
aim to catch stack overruns. Currently this feature does not
apply to init_task. This patch removes this restriction.
Note that a similar patch was posted by Prarit Bhargava [1]
some time ago but was
On Wed, 17 Sep 2014, Dmitry Torokhov wrote:
Hi Thomas,
On Wednesday, September 17, 2014 12:05:42 PM Thomas Gleixner wrote:
On Tue, 16 Sep 2014, Eric Caruso wrote:
We would like to be able to set different irq masks for triggers during
normal operation and for waking up the system. For
From: Wenyou Yang wenyou.y...@atmel.com
Ensure that the L2 cache configuration is optimal to avoid depending on the
bootloader to set it correctly.
Signed-off-by: Wenyou Yang wenyou.y...@atmel.com
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
On Thu, 18 Sep 2014 15:14:03 +0200
Alexander Graf ag...@suse.de wrote:
Am 18.09.2014 um 06:17 schrieb German Rivera german.riv...@freescale.com:
On 09/15/2014 06:44 PM, Kim Phillips wrote:
On Thu, 11 Sep 2014 12:34:21 -0500
J. German Rivera german.riv...@freescale.com wrote:
From:
I am announcing the release of the Linux 3.13.11.7 kernel.
The updated 3.13.y tree can be found at:
git://kernel.ubuntu.com/ubuntu/linux.git linux-3.13.y
and can be browsed at:
http://kernel.ubuntu.com/git?p=ubuntu/linux.git;h=refs/heads/linux-3.13.y;a=shortlog
The diff from v3.13.11.6 is
On Thu, Sep 18, 2014 at 08:29:34PM +0200, Fabian Frederick wrote:
spin_unlock after spin_lock only.
This fixes the following sparse warning:
fs/jbd2/transaction.c:1102:20: warning: context imbalance
in 'jbd2_journal_get_create_access' - different lock contexts for basic block
On Thu, Sep 18, 2014 at 10:38:36PM +0200, Alexandre Belloni wrote:
From: Wenyou Yang wenyou.y...@atmel.com
Ensure that the L2 cache configuration is optimal to avoid depending on the
bootloader to set it correctly.
Signed-off-by: Wenyou Yang wenyou.y...@atmel.com
Signed-off-by: Alexandre
[...]
In that case, don't forget to enable MMC_CAP2_FULL_PWR_CYCLE.
if MMC_CAP2_NO_PRESCAN_POWERUP enable, will call mmc_power_off() at start,
then it will check ios.power_mode, but the state is MMC_POWER_OFF and just
return.
Uhh, that's right! So, I wonder why we invokes
On 18/09/14 01:17, Russell King - ARM Linux wrote:
On Wed, Sep 17, 2014 at 09:10:16AM -0700, Daniel Thompson wrote:
@@ -604,8 +731,19 @@ static void gic_raise_softirq(const struct cpumask
*mask, unsigned int irq)
{
int cpu;
unsigned long flags, map = 0;
+unsigned long
Chris,
On Thu, Sep 18, 2014 at 12:31 AM, Chris Zhong z...@rock-chips.com wrote:
Get voltage duty table from device tree might be better, other platforms
can also use this
driver without any modify.
Signed-off-by: Chris Zhong z...@rock-chips.com
eries-changes: 2
Adviced by Lee Jones
-
Chris,
On Thu, Sep 18, 2014 at 12:31 AM, Chris Zhong z...@rock-chips.com wrote:
Document the st-pwm regulator
Signed-off-by: Chris Zhong z...@rock-chips.com
---
Changes in v2:
Adviced by Lee Jones
- rename the documentation
Adviced by Doug Anderson
- update the example
Adviced by Mark
On 18/09/2014 at 22:02:12 +0100, Russell King - ARM Linux wrote :
On Thu, Sep 18, 2014 at 10:38:36PM +0200, Alexandre Belloni wrote:
From: Wenyou Yang wenyou.y...@atmel.com
Ensure that the L2 cache configuration is optimal to avoid depending on the
bootloader to set it correctly.
On Wed, Sep 17, 2014 at 11:21:47PM -0400, Pranith Kumar wrote:
Add early boot self tests for RCU under CONFIG_PROVE_RCU.
Currently the only test is adding a dummy callback which increments a counter
which we then later verify after calling rcu_barrier*().
Signed-off-by: Pranith Kumar
These changes allow us to support VFP correctly on Krait processors.
They also fix short vector emulation for Cortex-A15 and Krait.
Stepan Moskovchenko (1):
arm: vfp: Bounce undefined instructions in vectored mode
Stephen Boyd (2):
ARM: vfp: Workaround bad MVFR1 register on some Kraits
From: Stepan Moskovchenko step...@codeaurora.org
Certain ARM CPU implementations (e.g. Cortex-A15) may not raise a
floating- point exception whenever deprecated short-vector VFP
instructions are executed. Instead these instructions are treated
as UNALLOCATED. Change the VFP exception handling
Certain versions of the Krait processor don't report that they
support the fused multiply accumulate instruction via the MVFR1
register despite the fact that they actually do. Unfortunately we
use this register to identify support for VFPv4. Override the
hwcap on all Krait processors to indicate
The subarchitecture field in the fpsid register is 7 bits wide.
The topmost bit is used to designate that the subarchitecture
designer is not ARM. We use this field to determine which VFP
version is supported by the CPU. Since the topmost bit is ignored
with the current mask we detect non-ARM
On Wed, Sep 17 2014 at 07:51:38 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Hi Russell,
On Wed, Sep 17, 2014 at 09:10:16AM -0700, Daniel Thompson wrote:
This patch provides support for arm's newly added IPI FIQ. It works
by placing all interrupt sources *except* IPI FIQ in
Now that all GIC interrupt routing and handling logic is in the GIC
driver itself, un-export variables/functions which are no longer used
outside the GIC driver. This also allows us to remove gic_compare_int
and combine gic_get_int_mask with gic_get_int since these interfaces
are no longer used.
In preparation for GIC IRQ domain support, assign a GIC IRQ base
that does not overlap with the CPU IRQs.
Note that this breaks SEAD-3 when the GIC is in EIC mode, though
I'm not convinced it was working before either. It will be fixed
in the following patches.
Signed-off-by: Andrew Bresticker
The generic plat_irq_dispatch provided in irq_cpu.c is sufficient for
dispatching interrupts on Malta in legacy and vectored interrupt modes.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No
It's a duplicate of sead3-platform.c and is not even compiled.
Remove it before we start fixing up IRQ assignments.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No changes from v1.
---
GIC edge-triggered interrupts must be acknowledged by clearing the edge
detector via a write to GIC_SH_WEDGE. Create a separate edge-triggered
irq_chip with the appropriate irq_ack() callback. This also allows us
to get rid of gic_irq_flags.
Signed-off-by: Andrew Bresticker
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
local watchdog and count/compare timer. The remainder are CPU
interrupts which may optionally be re-routed through the GIC.
GIC hardware IRQs 0-6 are now used for local interrupts while
hardware IRQs 7+ are used for external
Now that the GIC properly uses IRQ domains, kill off the per-platform
routing tables that were used to make the GIC appear transparent.
This includes:
- removing the mapping tables and the support for applying them,
- moving GIC IPI support to the GIC driver,
- properly routing the i8259
Use a simple IRQ domain for the MIPS GIC. Remove the gic_platform_init
callback as it's no longer necessary for it to set the irqchip.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Acked-by: Jason Cooper ja...@lakedaemon.net
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by:
Create a legacy IRQ domain for the 16 i8259 interrupts.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No changes from v1.
---
arch/mips/Kconfig| 1 +
arch/mips/kernel/i8259.c | 24
Instead of requiring platforms to define the correct GIC_NUM_INTRS,
use the value reported in GIC_SH_CONFIG.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Acked-by: Jason Cooper ja...@lakedaemon.net
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef
If the online CPU check in gic_set_affinity() fails, return a proper
errno value instead of -1.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Acked-by: Jason Cooper ja...@lakedaemon.net
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No
Implement an irq_set_type callback for the GIC which is used to set
the polarity and trigger type of GIC interrupts.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Acked-by: Jason Cooper ja...@lakedaemon.net
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef
There's no need for platforms to have their own GIC irq_ack/irq_eoi
callbacks. irq_ack need only clear the GIC's edge detector on
edge-triggered interrupts and there's no need at all for irq_eoi.
Also get rid of the mask_ack callback since it's not necessary either.
Signed-off-by: Andrew
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig
option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Acked-by: Jason Cooper ja...@lakedaemon.net
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by:
Define a generic MIPS_GIC_IRQ_BASE which should be suitable for all
current boards in mach-generic/irq.h.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No changes from v1.
---
When mapping an interrupt in the CPU IRQ domain, set the vint handler
for that interrupt if the CPU uses vectored interrupt handling.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No changes
The GIC on Malta boards supports a total of 47 interrupts (40 shared
and 7 local) and is assigned a base of 24. This overlaps with the
MSC01 interrupt assignments which have a base of 64, so move the MSC01
interrupt base back a bit to give the GIC some room.
Signed-off-by: Andrew Bresticker
Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No changes from v1.
---
arch/mips/Kconfig | 1 +
Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs.
Since systems using CPS must also have a GIC, which is responsible for
routing all external interrupts and can map them to any hardware interrupt
vector, enable the remaining vectors. The two software interrupt vectors
are
Jacob Pan schrieb, Am 18.09.2014 01:13:
On Thu, 18 Sep 2014 00:20:00 +0200
Hartmut Knaack knaac...@gmx.de wrote:
Jacob Pan schrieb, Am 17.09.2014 02:11:
Platform driver for X-Powers AXP288 ADC, which is a sub-device of
the customized AXP288 PMIC for Intel Baytrail-CR platforms. GPADC
Nothing calls gic_{enable,disable}_interrupt() any more.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No changes from v1.
---
arch/mips/include/asm/gic.h | 2 --
The current MIPS GIC driver and the platform code using it are rather
ugly and could use a good cleanup before adding device-tree support [0].
This major issues addressed in this series are converting the GIC (and
platforms using it) to use IRQ domains and properly mapping interrupts
through the
The hardware perf event driver and oprofile interpret the global
cp0_perfcount_irq differently: in the hardware perf event driver
it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the
actual IRQ number. This still works most of the time since
MIPS_CPU_IRQ_BASE is usually 0, but is
For platforms which boot with device-tree or have correctly chained
all external interrupt controllers, a generic plat_irq_dispatch() can
be used. Implement a plat_irq_dispatch() which simply handles all the
pending interrupts as reported by C0_Cause.
Signed-off-by: Andrew Bresticker
mips_cpu_intc_init() is used for DT-based initialization of the CPU
IRQ domain. Give it a more appropriate name.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
No changes from v1.
---
The generic plat_irq_dispatch provided in irq_cpu.c is sufficient for
dispatching interrupts on SEAD-3 in legacy and vectored interrupt modes.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Reviewed-by: Qais Yousef qais.you...@imgtec.com
Tested-by: Qais Yousef qais.you...@imgtec.com
---
if anybody complains.
Same thing for v3.17-rc5 and next-20140918. Let's see if we can remove
the goni or aquila with wm8994 driver.
Done on top of next-20140918. Untested.
-8-
From: Paul Bolle pebo...@tiscali.nl
Please follow the patch submission process
On 09/18/2014 12:33 PM, Dave Hansen wrote:
@@ -410,6 +442,8 @@ void set_cpu_sibling_map(int cpu)
} else if (i != cpu !c-booted_cores)
c-booted_cores = cpu_data(i).booted_cores;
}
+ if (match_mc(c, o) ==
On 18 September 2014 08:49, Adrian Hunter adrian.hun...@intel.com wrote:
On 09/18/2014 08:25 AM, Adrian Hunter wrote:
On 09/17/2014 10:57 PM, Stephen Warren wrote:
On 09/17/2014 01:55 PM, Ulf Hansson wrote:
On 12 September 2014 19:18, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen
On Thu, Sep 11, 2014 at 07:03:32PM +0200, Christoffer Dall wrote:
On Thu, Sep 11, 2014 at 10:14:13AM +0200, Eric Auger wrote:
On 09/11/2014 05:09 AM, Christoffer Dall wrote:
On Mon, Sep 01, 2014 at 10:53:04AM +0200, Eric Auger wrote:
This patch enables irqfd on ARM.
irqfd framework
On Thu, Sep 18, 2014 at 02:27:59PM -0700, Doug Anderson wrote:
On Thu, Sep 18, 2014 at 12:31 AM, Chris Zhong z...@rock-chips.com wrote:
I would be tempted to say that you should add a few required properties:
* regulator-boot-on
* regulator-always-on
* regulator-initial-microvolts
From my
It would be nice to be copied on these patches, as the VFP code is
entirely my creation... I'll review these patches shortly.
On Thu, Sep 18, 2014 at 02:43:09PM -0700, Stephen Boyd wrote:
These changes allow us to support VFP correctly on Krait processors.
They also fix short vector emulation
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 21 +
1
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/Kconfig| 10 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 145
This patchset provides support for the Watchdog Timer (WDT) found in the Krait
Processor Sub-system (KPSS) of the MSM8960, APQ8064, and IPQ8064 chips.
This driver is implemented ontop of WATCHDOG_CORE, and therefore its primary
interface is through userspace. The implemantion is currently very
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by:
On Thursday, September 18, 2014 05:38:45 AM Paul E. McKenney wrote:
On Thu, Sep 18, 2014 at 03:15:36PM +0800, Lan Tianyu wrote:
On 2014年09月17日 21:10, Paul E. McKenney wrote:
On Wed, Sep 17, 2014 at 03:11:42PM +0800, Lan Tianyu wrote:
On 2014年08月29日 03:47, Paul E. McKenney wrote:
On Thu, 18 Sep 2014 23:52:01 +0200
Hartmut Knaack knaac...@gmx.de wrote:
Jacob Pan schrieb, Am 18.09.2014 01:13:
On Thu, 18 Sep 2014 00:20:00 +0200
Hartmut Knaack knaac...@gmx.de wrote:
Jacob Pan schrieb, Am 17.09.2014 02:11:
Platform driver for X-Powers AXP288 ADC, which is a
On 09/16/2014 09:58 PM, Jonathan Richardson wrote:
Hi,
This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where PS_HOLD has failed to reset the chip.
Choose priority 128, as according to documentation, this mechanism is
sufficient to restart the entire
On Thu, Sep 18, 2014 at 09:57:17PM +0200, Rickard Strandqvist wrote:
Should I add this as a patch in lib/string.c or email him first.. What
is customary in these situations?
Just write up a normal patch and try to merge it through the normal
methods.
It's not that controversial to do:
On 09/18/2014 03:31 PM, Hauke Mehrtens wrote:
On 09/16/2014 09:58 PM, Jonathan Richardson wrote:
Hi,
This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a
On Thu, Sep 18, 2014 at 02:43:11PM -0700, Stephen Boyd wrote:
diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h
index f4ab34fd4f72..76d3f6907cce 100644
--- a/arch/arm/include/asm/vfp.h
+++ b/arch/arm/include/asm/vfp.h
@@ -21,7 +21,7 @@
#define FPSID_FORMAT_MASK(0x3
On Sep 18, 2014, at 3:32 PM, Josh Cartwright jo...@codeaurora.org wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where PS_HOLD has failed to reset the chip.
Choose priority 128, as
On 09/18/2014 12:38 AM, Nicholas A. Bellinger wrote:
On Sat, 2014-09-13 at 21:55 +0200, Christoph Hellwig wrote:
ping again. We're getting closer to the end of the 3.18 merge window
and there still hasn't been a response. Should Andy just send the patches
directly to Linus once 3.18 opens
On 09/19/2014 12:39 AM, Florian Fainelli wrote:
On 09/18/2014 03:31 PM, Hauke Mehrtens wrote:
On 09/16/2014 09:58 PM, Jonathan Richardson wrote:
Hi,
This patchset contains initial support for Broadcom's Cygnus SoC based on
our
iProc architecture. Initial support is minimal and includes
On Thu, Sep 18, 2014 at 03:47:20PM -0700, Kumar Gala wrote:
On Sep 18, 2014, at 3:32 PM, Josh Cartwright jo...@codeaurora.org wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where
On Thu, Sep 18, 2014 at 02:43:12PM -0700, Stephen Boyd wrote:
From: Stepan Moskovchenko step...@codeaurora.org
Certain ARM CPU implementations (e.g. Cortex-A15) may not raise a
floating- point exception whenever deprecated short-vector VFP
instructions are executed. Instead these
Hello,
I've fixed coding style issues in drivers/staging/imx-drm directory. This is a
part of Eudyptula Challenge.
Rene Kolarik
Signed-off-by: Rene Kolarik rene.kola...@gmail.com
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index
On Fri, Sep 19, 2014 at 12:55:11AM +0200, Rafael J. Wysocki wrote:
On Thursday, September 18, 2014 05:38:45 AM Paul E. McKenney wrote:
On Thu, Sep 18, 2014 at 03:15:36PM +0800, Lan Tianyu wrote:
On 2014年09月17日 21:10, Paul E. McKenney wrote:
On Wed, Sep 17, 2014 at 03:11:42PM +0800, Lan
On Wednesday, September 17, 2014 04:40:36 PM Graeme Gregory wrote:
On Thu, Sep 18, 2014 at 01:22:10AM +0200, Arnd Bergmann wrote:
On Wednesday 17 September 2014, Graeme Gregory wrote:
It sounds like from the discussions in other threads that ARM64 should
be following x86 and re-using DT
On Sep 18, 2014, at 3:49 PM, Josh Cartwright jo...@codeaurora.org wrote:
On Thu, Sep 18, 2014 at 03:47:20PM -0700, Kumar Gala wrote:
On Sep 18, 2014, at 3:32 PM, Josh Cartwright jo...@codeaurora.org wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other
On Thu, 2014-09-18 at 15:22 -0500, Kim Phillips wrote:
On Thu, 18 Sep 2014 15:14:03 +0200
Alexander Graf ag...@suse.de wrote:
Am 18.09.2014 um 06:17 schrieb German Rivera
german.riv...@freescale.com:
On 09/15/2014 06:44 PM, Kim Phillips wrote:
On Thu, 11 Sep 2014 12:34:21
On 12 September 2014 12:16, Greg KH gre...@linuxfoundation.org wrote:
On Fri, Sep 12, 2014 at 11:41:44AM -0600, Mathieu Poirier wrote:
Good morning and thanks for the review. Pls see comments below.
Mathieu
On 11 September 2014 14:33, Greg KH gre...@linuxfoundation.org wrote:
Some first
On Thu, 2014-09-18 at 15:54 -0700, Andy Grover wrote:
On 09/18/2014 12:38 AM, Nicholas A. Bellinger wrote:
On Sat, 2014-09-13 at 21:55 +0200, Christoph Hellwig wrote:
ping again. We're getting closer to the end of the 3.18 merge window
and there still hasn't been a response. Should Andy
From: Todd Poynor toddpoy...@google.com
Currently when a pending wakeup irq stops suspend, it can be difficult
to determine why suspend was prevented and which IRQ was actually
responsible. In order to help debug such situation, this patch prints the
IRQ number and action name of that pending
@@ -58,12 +56,12 @@ int spu_handle_mm_fault(struct mm_struct *mm, unsigned
long ea,
goto out_unlock;
}
- is_write = dsisr MFC_DSISR_ACCESS_PUT;
+ is_write = dsisr DSISR_ISSTORE;
if (is_write) {
if (!(vma-vm_flags VM_WRITE))
From: Todd Poynor toddpoy...@google.com
Existing timestamps in a dmesg only log suspend activities
(e.g. filesystem syncs, freezing/unfreezing tasks etc) while the
system has already started to enter/exit the suspend state.
Sometimes it is handy to have suspend entry/exit overhead
information
On Thu, 2014-09-18 at 18:13 -0500, Yoder Stuart-B08248 wrote:
-Original Message-
From: Kim Phillips [mailto:kim.phill...@freescale.com]
Sent: Thursday, September 18, 2014 3:23 PM
To: Alexander Graf
Cc: Rivera Jose-B46482; gre...@linuxfoundation.org; a...@arndb.de;
Hi Mark,
Thanks for the feedback.
On 14-09-16 05:00 PM, Mark Rutland wrote:
On Tue, Sep 16, 2014 at 08:58:12PM +0100, Jonathan Richardson wrote:
Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Reviewed-by: Ray Jui r...@broadcom.com
Reviewed-by: Desmond Liu
On Thu, 18 Sep 2014 12:17:08 -0700, Andrew Morton wrote:
On Thu, 18 Sep 2014 23:56:25 +0900 Ryusuke Konishi
konishi.ryus...@lab.ntt.co.jp wrote:
From: Andreas Rohner andreas.roh...@gmx.net
This bug leads to reproducible silent data loss, despite the use of
msync(), sync() and a clean
On Thu, Sep 18, 2014 at 10:24:02PM +0200, Julia Lawall wrote:
From: Julia Lawall julia.law...@lip6.fr
This patch removes some kzalloc-related macros and rewrites the
associated null tests to use !x rather than x == NULL.
This is sort of exactly what Oleg asked us not to do in his previous
On 14-09-16 05:47 PM, Mark Rutland wrote:
On Tue, Sep 16, 2014 at 08:58:13PM +0100, Jonathan Richardson wrote:
The iProc clock driver controls PLL's common across iProc chips. The
Nit: s/PLL's/PLLs/ (we aren't greengrocers [1]).
Will fix.
cygnus driver controls cygnus specific features
+
+int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid)
+{
+ int psize, ssize;
+
+ *esid = (ea ESID_MASK) | SLB_ESID_V;
+
+ switch (REGION_ID(ea)) {
+ case USER_REGION_ID:
+ pr_devel(copro_data_segment: 0x%llx -- USER_REGION_ID\n, ea);
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, September 18, 2014 6:29 PM
To: Yoder Stuart-B08248
Cc: Phillips Kim-R1AAHA; Alexander Graf; Rivera Jose-B46482;
gre...@linuxfoundation.org; a...@arndb.de;
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/4]
-Original Message-
From: Kim Phillips [mailto:kim.phill...@freescale.com]
Sent: Thursday, September 18, 2014 3:23 PM
To: Alexander Graf
Cc: Rivera Jose-B46482; gre...@linuxfoundation.org; a...@arndb.de;
linux-kernel@vger.kernel.org; Yoder
Stuart-B08248; Wood Scott-B07421;
On 2014/9/17 22:17, Martin Kelly wrote:
When compiling with CONFIG_DEBUG_FS=n, gcc emits an unused variable
warning for pmc_atom.c because ret is used only within the
CONFIG_DEBUG_FS block. This patch adds a dummy #ifdef for
pmc_dbgfs_register when CONFIG_DEBUG_FS=n to simplify the code and
On Thu, 2014-09-18 at 18:39 -0500, Yoder Stuart-B08248 wrote:
-Original Message-
From: Kim Phillips [mailto:kim.phill...@freescale.com]
Sent: Monday, September 15, 2014 6:45 PM
To: Rivera Jose-B46482
Cc: gre...@linuxfoundation.org; a...@arndb.de;
On 09/18/2014 07:20 PM, Rafael J. Wysocki wrote:
On Wednesday, September 17, 2014 04:40:36 PM Graeme Gregory wrote:
On Thu, Sep 18, 2014 at 01:22:10AM +0200, Arnd Bergmann wrote:
On Wednesday 17 September 2014, Graeme Gregory wrote:
It sounds like from the discussions in other threads that
On 14-09-18 02:55 AM, Mika Westerberg wrote:
On Thu, Sep 18, 2014 at 11:41:13AM +0200, Samuel Ortiz wrote:
Hi Mika,
On Thu, Sep 18, 2014 at 10:49:43AM +0300, Mika Westerberg wrote:
On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
Direct Irq En bit can be initialized to a bad
On Thu, 18 Sep 2014, Henrique de Moraes Holschuh wrote:
On Thu, 18 Sep 2014, H. Peter Anvin wrote:
We should, but this is also part of why we want the early ucode capability.
Well, yes. But that won't help the several stable and LTS distros with
kernels without early ucode update support.
On Thu, 18 Sep 2014, micky wrote:
On 09/18/2014 12:53 PM, Lee Jones wrote:
On Thu, 18 Sep 2014, micky_ch...@realsil.com.cn wrote:
From: Micky Ching micky_ch...@realsil.com.cn
Fix rts52275249 failed send buffer cmd after suspend,
PM_CTRL3 should reset before send any buffer cmd after
On 09/17/2014 12:03 PM, Catalin Marinas wrote:
So for arm64 currently we have some hooks in dma-mapping.c to intercept
when a device is added to a bus. What I need to do though is check
recursively whether the parent (bus) had the 'dma-coherent' property
(pointed out by Jon). I think
Hi, Zefan
Thanks for your reply. You are right, vfs refcount should guarantee us
there is no more file read before we destroy that cgroup. I thought
there is somewhere else could release that cgroup refcount.
Maybe I didn't make it clear, this bug is hardly reproducible, we only
saw it once
On Sep 18, 2014 5:13 PM, Henrique de Moraes Holschuh h...@hmh.eng.br wrote:
On Thu, 18 Sep 2014, Henrique de Moraes Holschuh wrote:
On Thu, 18 Sep 2014, H. Peter Anvin wrote:
We should, but this is also part of why we want the early ucode
capability.
Well, yes. But that won't help
The cpuid bit gets twiddled...
On September 18, 2014 5:23:40 PM PDT, Andy Lutomirski l...@amacapital.net
wrote:
On Sep 18, 2014 5:13 PM, Henrique de Moraes Holschuh h...@hmh.eng.br
wrote:
On Thu, 18 Sep 2014, Henrique de Moraes Holschuh wrote:
On Thu, 18 Sep 2014, H. Peter Anvin wrote:
We
On Thu, Sep 18, 2014 at 09:13:26AM +0300, Gleb Natapov wrote:
On Thu, Sep 18, 2014 at 08:29:17AM +0800, Wanpeng Li wrote:
Hi Andres,
On Wed, Sep 17, 2014 at 10:51:48AM -0700, Andres Lagar-Cavilla wrote:
[...]
static inline int check_user_page_hwpoison(unsigned long addr)
{
int rc,
+/**
+ * @briefDisconnects one endpoint to remove its network link
+ *
+ * @param[in] mc_ioPointer to opaque I/O object
+ * @param[in]dprc_handleHandle to the DPRC object
+ * @param[in] endpointEndpoint configuration parameters.
+ *
+ * @returns'0' on
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