Addy,
On Tue, Oct 7, 2014 at 8:50 PM, Addy Ke addy...@rock-chips.com wrote:
As show in I2C specification:
- Standard-mode: the minimum HIGH period of the scl clock is 4.0us
the minimum LOW period of the scl clock is 4.7us
- Fast-mode: the minimum HIGH period of the scl clock
Both the LTC2941 and LTC2943 measure battery capacity.
The LTC2943 is compatible with the LTC2941, it adds voltage and
temperature monitoring, and uses a slightly different conversion
formula for the charge counter.
To avoid confusion with e.g. the LTC2945, the driver is called
LTC2941 instead of
Quoting Morten Rasmussen (2014-09-22 09:24:02)
Architectures that don't have any other means for tracking cpu frequency
changes need a callback from cpufreq to implement a scaling factor to
enable scale-invariant per-entity load-tracking in the scheduler.
To compute the scale invariance
On Mon, 2014-10-06 at 16:40 -0700, Zach Brown wrote:
Both of the file target's calls to vfs_fsync_range() got the end offset
off by one. The range is inclusive, not exclusive. It would sync a bit
more data than was required.
The sync path already tested the length of the range and fell
The scheduler needs to know the current capacity of a cpu taking into
account micro-architectural differences as well as current cpu
frequency. The method for determining this may vary not only from
architecture to architecture, but also within differnt platforms of the
same architectures.
struct
The fair scheduler needs a method to retrieve the capacity of a cpu,
which may be derived from several platform-specific factors including
micro-architectural differences (e.g. big.LITTLE cpus), cpus with
different transistor types or process node properties (e.g. Nvidia
Tegra30 LP cpu) and cpu
Move the cpu capacity bits out of arch/arm/ and into the CPUfreq driver.
Not all ARM devices will use CPUfreq and it is unsafe to assume as such
in topology.c.
Instead, use the new capacity_ops introduced into CFS. If this code is
generic enough then it could be factored and shared via a header
-Original Message-
From: Wolfram Sang [mailto:w...@the-dreams.de]
Sent: Friday, October 03, 2014 3:55 PM
To: Yuan Yao-B46683
Cc: ma...@denx.de; l...@karo-electronics.de; mark.rutl...@arm.com; Duan
Fugang-B38611; shawn@linaro.org; linux-kernel@vger.kernel.org; linux-
This change switches to using devm_* managed resources APIs to
request the resources in probe to simplify probe error path and
module unloading.
Cc: Dmitry Torokhov dmitry.torok...@gmail.com
Cc: linux-in...@vger.kernel.org
Signed-off-by: Pramod Gurav pramod.gu...@smartplayin.com
---
While offling node by hot removing memory, the following divide error
occurs:
divide error: [#1] SMP
[...]
Call Trace:
[...] handle_mm_fault
[...] ? try_to_wake_up
[...] ? wake_up_state
[...] __do_page_fault
[...] ? do_futex
[...] ? put_prev_entity
[...] ?
This change switches to using devm_* managed resources APIs to
request the resources in probe to simplify probe error path and
module unloading and does away with remove function.
Cc: Dmitry Torokhov dmitry.torok...@gmail.com
Cc: linux-in...@vger.kernel.org
Signed-off-by: Pramod Gurav
On Wed, Oct 08, 2014 at 06:30:14AM +, Yao Yuan wrote:
-Original Message-
From: Wolfram Sang [mailto:w...@the-dreams.de]
Sent: Friday, October 03, 2014 3:55 PM
To: Yuan Yao-B46683
Cc: ma...@denx.de; l...@karo-electronics.de; mark.rutl...@arm.com; Duan
Fugang-B38611;
On Tue, Sep 30, 2014 at 04:59:38PM +0200, Matteo Facchinetti wrote:
From: Matteo Facchinetti matteo.facchine...@sirius-es.it
If available voltages are not given, mmc_regulator_get_supply() function
returns 0 and mxcmmc driver doesn't set a value for ocr_avail mask.
In accordance with the
Hello Karam,
On Mon, Oct 06, 2014 at 02:31:05PM +0900, karam@lge.com wrote:
From: karam.lee karam@lge.com
Recently rw_page block device operation is added.
This patch implements rw_page operation for zram block device so
zram can process page sized I/O without bio.
It's a
On Tue, Sep 30, 2014 at 04:59:37PM +0200, Matteo Facchinetti wrote:
From: Matteo Facchinetti matteo.facchine...@sirius-es.it
In accordance with the other drivers that using the dma engine,
fix it, leaving *only* to dma driver the complete control to
ending the read operation.
Removing
Hi all,
Please do not add any material intended for v3.19 to you linux-next
included trees until after v3.18-rc1 has been released.
Changes since 20141007:
Non-merge commits (relative to Linus' tree): 9651
8214 files changed, 378909 insertions(+), 275679 deletions(-)
Hi Mark,
On Tue, Oct 7, 2014 at 7:13 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Oct 07, 2014 at 01:40:28PM +0100, Arun Chandran wrote:
This is due to incorrect definition of ELF_ET_DYN_BASE. It
introduces randomization for text even if user does a echo 0
Sorry later response and just back from vacation.
On 2014年09月29日 16:20, Viresh Kumar wrote:
But this change is buggy.. Because you are updating 'cpufreq_suspended'
before actually stopping the governor, any calls to __cpufreq_governor()
will be converted to NO-operations because of this in
On Mon, Oct 06, 2014 at 08:53:51AM +0200, Jean Pihet wrote:
Hi Jiri,
On 5 October 2014 20:24, Jiri Olsa jo...@redhat.com wrote:
On Sun, Oct 05, 2014 at 07:48:01PM +0200, Borislav Petkov wrote:
Top-posting on purpose:
Btw, jolsa, if you get your LCE proposal for the perf splitting
-Original Message-
From: Johan Hovold [mailto:jhov...@gmail.com] On Behalf Of Johan Hovold
Sent: Monday, October 06, 2014 7:03 PM
To: Muthu Mani
Cc: Samuel Ortiz; Lee Jones; Wolfram Sang; linux-...@vger.kernel.org; Linus
Walleij; Alexandre Courbot; linux-g...@vger.kernel.org;
There are two masks associated with cpusets. The cpus/mems_allowed
and effective_cpus/mems. On the legacy hierarchy both these masks
are consistent with each other. This is the intersection of their
value and the currently active cpus. This means that we destroy the
original values set in these
On 2014-10-07 at 18:17:16 +0200, Dmitry Torokhov dmitry.torok...@gmail.com
wrote:
On Tue, Oct 07, 2014 at 03:33:22PM +0200, Tobias Klauser wrote:
On 2014-10-07 at 13:31:41 +0200, Pramod Gurav
pramod.gu...@smartplayin.com wrote:
This change switch to managed resources to simplifies error
-Original Message-
From: Alexandre Courbot [mailto:gnu...@gmail.com]
Sent: Tuesday, October 07, 2014 3:34 PM
To: Muthu Mani
Cc: Samuel Ortiz; Lee Jones; Wolfram Sang; Linus Walleij; Greg Kroah-
Hartman; linux-...@vger.kernel.org; linux-g...@vger.kernel.org; linux-
On Tue, 7 Oct 2014, Dave Hansen wrote:
Does this break slub's __cmpxchg_double_slab trick? I thought it
required page-freelist and page-counters to be doubleword-aligned.
Sure that would be required for it to work.
It's not like we really require this optimization when we're debugging,
but
On 7 October 2014 22:15, bseg...@google.com wrote:
Vincent Guittot vincent.guit...@linaro.org writes:
From: Morten Rasmussen morten.rasmus...@arm.com
Adds usage contribution tracking for group entities. Unlike
se-avg.load_avg_contrib, se-avg.utilization_avg_contrib for group
entities is
On Wed, Oct 8, 2014 at 4:09 PM, Muthu Mani m...@cypress.com wrote:
-Original Message-
From: Alexandre Courbot [mailto:gnu...@gmail.com]
Sent: Tuesday, October 07, 2014 3:34 PM
To: Muthu Mani
Cc: Samuel Ortiz; Lee Jones; Wolfram Sang; Linus Walleij; Greg Kroah-
Hartman;
On Tue, Oct 07, 2014 at 05:07:36PM -0600, David Ahern wrote:
32-bit perf binaries are not able to set filters on 64-bit kernels.
$ perf record -e net:netif_receive_skb --filter 'name == eth1
Error: failed to set filter with 25 (Inappropriate ioctl for device)
The reason is that
On Tuesday 30 September 2014 12:41:46 Tomi Valkeinen wrote:
Hi,
On 09/09/14 14:46, Maarten ter Huurne wrote:
This font is suitable for framebuffer consoles on devices with a
320x240 screen, to get a reasonable number of characters (53x24) that
are still at a readable size.
The font
Dear Dmitry,
在 2014年10月08日 07:39, Dmitry Torokhov 写道:
Hi Caesar,
On Sun, Sep 28, 2014 at 06:38:09PM +0800, Caesar Wang wrote:
Thermal is TS-ADC Controller module supports
user-defined mode and automatic mode.
User-defined mode refers,TSADC all the control signals entirely by
software writing
On Tue, Oct 07, 2014 at 05:00:07PM -0400, Boris Ostrovsky wrote:
Commit 3dcf63677d4e (xen/balloon: cancel ballooning if adding new
memory failed) makes reserve_additional_memory() return BP_ECANCELED
when an error is encountered. This error, however, is ignored by the
caller
From: Doug Anderson diand...@chromium.org
Some 32-bit (ARMv7) systems are architected like this:
* The firmware doesn't know and doesn't care about hypervisor mode and
we don't want to add the complexity of hypervisor there.
* The firmware isn't involved in SMP bringup or resume.
* The ARCH
This is a bug fix for using physical arch timers when
the arch_timer_use_virtual boolean is false. It restores the
arch_counter_get_cntpct() function after removal in
0d651e4e clocksource: arch_timer: use virtual counters
We need this on certain ARMv7 systems which are architected like this:
*
Liviu, Bjorn,
On 30.09.14 17:54:31, Liviu Dudau wrote:
On Tue, Sep 30, 2014 at 05:18:05PM +0100, Bjorn Helgaas wrote:
OK, I rebuilt pci/host-generic from scratch. It consists of your v13
patches + Arnd's build fix for pci_pio_to_address() in !CONFIG_OF configs.
Something went wrong with
On Tue, Oct 07, 2014 at 03:57:58PM +0530, Vidya Sagar wrote:
Enables root port to advertise its ASPM-L1 capability
resulting in possible link entry to L1 when an ASPM-L1 capable
device is connected
Enables per-controller per-TMS clock clamping by default
Enabling above features result in
On Tue, Oct 07, 2014 at 08:44:05AM -0700, Stephen Warren wrote:
On 10/07/2014 03:27 AM, Vidya Sagar wrote:
Enables root port to advertise its ASPM-L1 capability
resulting in possible link entry to L1 when an ASPM-L1 capable
device is connected
Enables per-controller per-TMS clock
On Wed, Oct 08, 2014 at 09:44:05AM +0200, Thierry Reding wrote:
On Tue, Oct 07, 2014 at 03:57:58PM +0530, Vidya Sagar wrote:
[...]
+static inline void rp_writel(struct tegra_pcie_port *port, u32 value,
+unsigned long offset)
+{
+
On 29/09/14 15:22, Weike Chen wrote:
+ .num_chipselect = 4,
How is this right ?
There's only one physical chip-select line per SPI master...
It's a 1:1 mapping.
Now, we have another board which can support 4 slave spi per master, but not
only Galileo. Since that board
This series is partially in response to a discussion around DT bindings
for CPUfreq drivers [0], but it is also needed for on-going work to
integrate CPUfreq with the scheduler. In particular a scheduler-driven
cpu frequency scaling policy would be well served to know if the
underlying CPUfreq
There are cases for CPUfreq driver flags to be exposed outside of the
CPUfreq core code. In particular the CPUFREQ_NO_SLEEP flag can be used
by CPUfreq governors to optimize when and how they call that drivers
.target callback. In fact this knowledge is a requirement for the
on-going work to
Hi Linus,
The following changes since commit 2ce7598c9a453e0acd0e07be7be3f5eb39608ebd:
Linux 3.17-rc4 (2014-09-07 16:09:43 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git for-linus
for you to fetch changes up to
The CPUfreq core does not differentiate between .target .target_index
callbacks that may sleep or block and callbacks that are fast and return
immediately. To date this has not mattered much since the typical
CPUfreq governor calls the .target callback from process context via a
workqueue.
When
Hi Linus,
here is the bulk of GPIO changes for the v3.18 cycle.
When I tested to pull this into your tree I found two conflicts that
also appeared in linux-next, one in the qualcomm driver which
is trivial and one in the gpiolib.c which is also kind of trivial (lower
hunk is the correct one).
bus_add_device() should be called before devtmpfs_create_node(), so when
userland application opens device from devtmpfs, it wouldn't get ENODEV
from kernel, because device_add() wasn't completed.
Signed-off-by: Sergey Klyaus sergey.kly...@tune-it.ru
---
drivers/base/core.c | 40
On 8 October 2014 13:18, Mike Turquette mturque...@linaro.org wrote:
This series is partially in response to a discussion around DT bindings
for CPUfreq drivers [0], but it is also needed for on-going work to
integrate CPUfreq with the scheduler. In particular a scheduler-driven
cpu frequency
On Tuesday 07 October 2014 22:27:00 Scott Branden wrote:
From: Jonathan Richardson jonat...@broadcom.com
Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Reviewed-by: Ray Jui r...@broadcom.com
Reviewed-by: Desmond Liu desmo...@broadcom.com
Reviewed-by: JD
YOU HAVE WON $2,100,000.00.doc
Description: MS-Word document
On Tuesday 07 October 2014 22:27:02 Scott Branden wrote:
diff --git a/Documentation/devicetree/bindings/arm/cygnus.txt
b/Documentation/devicetree/bindings/arm/cygnus.txt
new file mode 100644
index 000..a210377
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cygnus.txt
@@ -0,0
Hi,
Intel Quark X1000 consists of two SPI controllers which can be PCI enumerated.
SPI-PXA2XX PCI layer doesn't support it. Thus, we add support for Intel Quark
X1000 SPI as well.
---
v3:
[PATCH 1/2]
* Improve the commit message.
* A couple of minor fixes.
[PATCH 2/2]
* Set '.num_chipselect' to
On Tuesday 07 October 2014 22:27:03 Scott Branden wrote:
From: Jonathan Richardson jonat...@broadcom.com
Tested-by: Jonathan Richardson jonat...@broadcom.com
Reviewed-by: JD (Jiandong) Zheng jdzh...@broadcom.com
Signed-off-by: Scott Branden sbran...@broadcom.com
Do you actually need a
There are two SPI controllers exported by PCI subsystem for Intel Quark X1000.
The SPI memory mapped I/O registers supported by Quark are different from
the current implementation, and Quark only supports the registers of 'SSCR0',
'SSCR1', 'SSSR', 'SSDR', and 'DDS_RATE'. This patch is to enable
There are several registers for SPI, and the registers of 'SSCR0' and 'SSCR1'
are accessed frequently. This path is to introduce helper functions to
simplify the accessing of 'SSCR0' and 'SSCR1'.
Reviewed-by: Andy Shevchenko andriy.shevche...@linux.intel.com
Acked-by: Mika Westerberg
We can get into an infinite loop if the I2S_CLR register fails to
clear due to a missing break statement, so add that.
Signed-off-by: Sonny Rao sonny...@chromium.org
---
sound/soc/rockchip/rockchip_i2s.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
On Tue, Oct 07, 2014 at 09:50:46PM +0200, Oleg Nesterov wrote:
And note that another caller of task_preempt_count(), set_cpu(), is
fine but it doesn't really need this helper.
And afaics we do not need -saved_preempt_count at all, the trivial
patch below makes it unnecessary, we can kill it
To all those CC'ed,
The Baytrail-T platform firmware has defined two customized operation
regions for PMIC chip Crystal Cove - one is for power resource handling
and one is for thermal: sensor temperature reporting, trip point setting,
etc. This patch adds support for them on top of the
On Wed, Oct 08, 2014 at 12:37:40PM +0530, Preeti U Murthy wrote:
There are two masks associated with cpusets. The cpus/mems_allowed
and effective_cpus/mems. On the legacy hierarchy both these masks
are consistent with each other. This is the intersection of their
value and the currently active
Commit-ID: 5f1d919a8ca15f450c749227bc5e2e18f3cbfdb4
Gitweb: http://git.kernel.org/tip/5f1d919a8ca15f450c749227bc5e2e18f3cbfdb4
Author: Jan Beulich jbeul...@suse.com
AuthorDate: Wed, 24 Sep 2014 08:40:14 +0100
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Wed, 8 Oct 2014
Commit-ID: 82ef36449d311a29b20f82fdce0de856057fa691
Gitweb: http://git.kernel.org/tip/82ef36449d311a29b20f82fdce0de856057fa691
Author: Jan Beulich jbeul...@suse.com
AuthorDate: Wed, 24 Sep 2014 08:41:30 +0100
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Wed, 8 Oct 2014
Commit-ID: 2075244f9b871f18a007935c73d2ab49d4fb43e0
Gitweb: http://git.kernel.org/tip/2075244f9b871f18a007935c73d2ab49d4fb43e0
Author: Bryan O'Donoghue pure.lo...@nexus-software.ie
AuthorDate: Tue, 7 Oct 2014 01:19:48 +0100
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Wed, 8
Dear Viresh Kumar,
On Wed, 8 Oct 2014 13:24:30 +0530, Viresh Kumar wrote:
On 8 October 2014 13:18, Mike Turquette mturque...@linaro.org wrote:
This series is partially in response to a discussion around DT bindings
for CPUfreq drivers [0], but it is also needed for on-going work to
Commit-ID: aece118e487a744eafcdd0c77fe32b55ee2092a1
Gitweb: http://git.kernel.org/tip/aece118e487a744eafcdd0c77fe32b55ee2092a1
Author: Bryan O'Donoghue pure.lo...@nexus-software.ie
AuthorDate: Tue, 7 Oct 2014 01:19:49 +0100
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Wed, 8
On Tue, Oct 07, 2014 at 10:27:00PM -0700, Scott Branden wrote:
+static void __init bcm_cygnus_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+ l2x0_of_init(0, ~0UL);
Please don't explicitly call l2x0 initialisation. Instead, set the
appropriate
Commit-ID: 3f63572187f5ae6a0a9e5ebee88b57e6f71c3cd4
Gitweb: http://git.kernel.org/tip/3f63572187f5ae6a0a9e5ebee88b57e6f71c3cd4
Author: Jan Beulich jbeul...@suse.com
AuthorDate: Wed, 24 Sep 2014 08:37:00 +0100
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Wed, 8 Oct 2014
Hi Oussama,
On 10/07/2014 02:02 PM, Oussama Ghorbel wrote:
The USB OTG port does not work since v3.16 on omap platform.
This is a regression introduced by the commit
eb82a3d846fa (phy: omap-usb2: Balance pm_runtime_enable() on probe failure
and remove).
This because the call to
On 8 October 2014 13:41, Thomas Petazzoni
thomas.petazz...@free-electrons.com wrote:
On Wed, 8 Oct 2014 13:24:30 +0530, Viresh Kumar wrote:
On 8 October 2014 13:18, Mike Turquette mturque...@linaro.org wrote:
This series is partially in response to a discussion around DT bindings
for
From: Jaiprakash Singh b44...@freescale.com
IFC IO accressor are set at run time based
on IFC IP registers endianness.IFC node in
DTS file contains information about
endianness.
Signed-off-by: Jaiprakash Singh b44...@freescale.com
---
.../bindings/memory-controllers/fsl/ifc.txt|2 +
On Wed, Oct 08, 2014 at 03:43:11PM +0900, Yasuaki Ishimatsu wrote:
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index bfa3c86..fb7dc3f 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -1496,18 +1496,26 @@ static void update_task_scan_period(struct
task_struct *p,
On Tue, Oct 07, 2014 at 11:26:11PM -0700, Mike Turquette wrote:
+struct capacity_ops {
+ unsigned long (*get_capacity)(int cpu);
+ spinlock_t lock;
+};
Yeah, fail there. Ops vectors should not contain serialization, that
simply doesn't work. It means you cannot switch the entire
On Mon, 29 Sep 2014, Bjorn Andersson wrote:
Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based
devices.
The driver exposes resources that child drivers can operate on; to
implementing regulator, clock and bus frequency drivers.
Signed-off-by: Bjorn Andersson
Hello Doug,
On 10/07/2014 07:48 PM, Doug Anderson wrote:
I don't have all the right patches to test this right now. Hopefully
you can point me at what we're using right now. I'd expect that this
will need the patches that Chanwoo and Javier are working on, so I've
added them to this.
Hi all,
recently Linux 3.14 has been released and I find the networking has
added udp gro and vxlan gro funtion, then I use the redhat 7.0(there is also
add this funtion)
to test, I use kernel vxlan module and create a vxlan device then attach the
device to ovs bridge , the configure
From: Lothar Waßmann
David Laight wrote:
From: Eric Dumazet
On Tue, 2014-10-07 at 15:19 +0200, Lothar Wamann wrote:
commit 1b7bde6d659d (net: fec: implement rx_copybreak to improve rx
performance)
introduced a regression for i.MX28. The swap_buffer() function doing
the
On 07.10.14 16:01:49, Liviu Dudau wrote:
On Tue, Oct 07, 2014 at 03:27:44PM +0100, Robert Richter wrote:
On 24.09.14 18:06:04, Arnd Bergmann wrote:
+ compatible = cavium,thunder-pcie;
+ device_type = pci;
+ msi-parent = its;
+
Hi Morten,
Sorry for late jumping in.
The problem seems to be self-evident. But for the implementation to be
equally attractive it needs to account for every freq change for every task,
or anything less than that makes it less attractive.
But this should be very hard. Intel Architecture has
As of now, a miscdevice driver has to provide an implementation of
the open() file operation if it wants to have misc_open() assign a
pointer to struct miscdevice to file-private_data for other file
operations to use (given the user calls open()).
This leads to situations where a miscdevice
On Tue, Oct 07, 2014 at 01:52:21PM +0100, Mark Brown wrote:
On Tue, Oct 07, 2014 at 02:11:07PM +0900, Gyungoh Yoo wrote:
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
Several problems here:
- I don't have patches 1-6 or the cover letter for this series - what
are the
From: Ian Munsie imun...@au1.ibm.com
This adds the OPAL call to change a PHB into cxl mode.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/opal.h| 2 ++
arch/powerpc/platforms/powernv/opal-wrappers.S |
This is the latest version of the cxl driver. Change log below:
v4:
- Updates based on comments from mpe (offline and online).
- Refactor the sstp lock to be an entry lock.
- Fixed error paths on new status_mutex in start_work
- added some missing include files
- moved associating pid/mm
From: Ian Munsie imun...@au1.ibm.com
Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests
to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This wastes a
lot of IRQs which can be a scarce resource.
For cxl we may require multiple IRQs for every context that
From: Sergei Shtylyov
On 10/07/2014 05:19 PM, Lothar Wamann wrote:
commit 1b7bde6d659d (net: fec: implement rx_copybreak to improve rx
performance)
introduced a regression for i.MX28. The swap_buffer() function doing
the endian conversion of the received data on i.MX28 may access
From: Ian Munsie imun...@au1.ibm.com
Export mmu_kernel_ssize and mmu_linear_psize. These are needed by the cxl
driver which has it's own MMU. To setup the MMU cxl needs access to these.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
On Wed, Oct 08, 2014 at 09:57:43AM +0800, Axel Lin wrote:
The module version is unlikely to be updated, use kernel version should be
enough.
Signed-off-by: Axel Lin axel@ingics.com
---
Hi Gyungoh,
Seems you have added MODULE_VERSION for the sky81452 serial patches.
Do you really need
From: Ian Munsie imun...@au1.ibm.com
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
On Wed, Oct 08, 2014 at 10:03:57AM +0900, Jingoo Han wrote:
On Tuesday, October 07, 2014 2:01 PM, Gyungoh Yoo wrote:
If possible, please add more detailed commit message for this patch.
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
drivers/video/backlight/Kconfig
From: Ian Munsie imun...@au1.ibm.com
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/pnv-pci.h| 31 ++
From: Ian Munsie imun...@au1.ibm.com
This adds a new function hash_page_mm() based on the existing hash_page().
This version allows any struct mm to be passed in, rather than assuming
current. This is useful for servicing co-processor faults which are not in the
context of the current running
From: Ian Munsie imun...@au1.ibm.com
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afuM.N and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling
From: Ian Munsie imun...@au1.ibm.com
This new header adds callbacks and structs needed by the rest of the kernel to
hook into the cxl infrastructure.
This adds the cxl_ctx_in_use() function for use in the mm code to see if any
cxl contexts are currently in use. This is used by the tlbie() to
On Tue, Oct 7, 2014 at 10:28 PM, Doug Anderson diand...@chromium.org wrote:
For pinctrl the default state is applied to pins before the driver's
probe function is called. This is normally a sensible thing to do,
but in some cases can cause problems. That's because the pins will
change state
From: Ian Munsie imun...@au1.ibm.com
This is the core of the cxl driver.
It adds support for using cxl cards in the powernv environment only (ie POWER8
bare metal). It allows access to cxl accelerators by userspace using the
/dev/cxl/afuM.N char devices.
The kernel driver has no knowledge of
From: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
drivers/misc/cxl/Kconfig | 17 +
drivers/misc/cxl/Makefile | 2 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig
From: Ian Munsie imun...@au1.ibm.com
This adds the base cxl support that cannot be built as a module. Specifically
it adds the cxl callbacks that are called from the core powerpc mm code which
must always exist irrespective of if the cxl module is loaded or not. This is
similar to how cell works
From: Ian Munsie imun...@au1.ibm.com
This adds a header file for use by userspace programs wanting to interact with
the kernel cxl driver. It defines structs and magic numbers required for
userspace to interact with devices in /dev/cxl/afuM.N.
Further documentation on this interface is added in
The parent should be spdif_8ch_pre not spdif_8ch_src, which doesn't
exist and looks to be a typo. The TRM also confirms this.
Signed-off-by: Sonny Rao sonny...@chromium.org
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 08/10/14 08:48, Chen, Alvin wrote:
Now, we have another board which can support 4 slave spi per master, but not
only Galileo. Since that board is not public, after discussing with team, we
decide to make the
upstream code to support '1'.
I will change it back to
.num_chipselect = 1,
Hi
From: Ian Munsie imun...@au1.ibm.com
This adds hooks into the core powerpc mm code for cxl.
The core powerpc code sometimes uses local tlbie. Unfortunately this won't
work with the current cxl driver as it relies on snooping tlbie broadcasts.
The cxl hardware can have TLB entries invalidated
From: Ian Munsie imun...@au1.ibm.com
This moves spu_flush_all_slbs() into a generic call copro_flush_all_slbs().
This will be useful when we add cxl which also needs a similar SLB flush call.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
From: Ian Munsie imun...@au1.ibm.com
Currently spu_handle_mm_fault() is in the cell platform.
This code is generically useful for other non-cell co-processors on powerpc.
This patch moves this function out of the cell platform into arch/powerpc/mm so
that others may use it.
Signed-off-by: Ian
From: Ian Munsie imun...@au1.ibm.com
__spu_trap_data_seg() currently contains code to determine the VSID and ESID
required for a particular EA and mm struct.
This code is generically useful for other co-processors. This moves the code of
the cell platform so it can be used by other powerpc code.
I ran into a problem on a Sandybridge i5-2500s whilst measuring the
performance of GTT write-combining access. I found subsequent runs were
about 10-40x slower than the first. For example,
igt/gem_gtt_speed:
Time to read 16k through a GTT map: 325.285µs
Time to write 16k through a
Hi,
Apologies for taking so long - I've added this into the -nmw tree now.
Thanks,
Steve.
On 03/10/14 19:15, Fabian Frederick wrote:
use macro definition
Signed-off-by: Fabian Frederick f...@skynet.be
---
fs/gfs2/glock.c | 4 ++--
fs/gfs2/glops.c | 2 +-
fs/gfs2/trans.c | 2 +-
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