On 7/29/2020 11:57 PM, Jakub Kicinski wrote:
On Wed, 29 Jul 2020 17:42:12 +0300 Moshe Shemesh wrote:
On 7/28/2020 3:59 AM, Jakub Kicinski wrote:
On Mon, 27 Jul 2020 14:02:29 +0300 Moshe Shemesh wrote:
The enable_remote_dev_reset devlink param flags that the host admin
allows device resets
From: Thomas Gleixner
Move POSIX CPU timer expiry and signal delivery into task context.
Signed-off-by: Thomas Gleixner
---
arch/x86/Kconfig |1 +
1 file changed, 1 insertion(+)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -209,6 +209,7 @@ config X86
select HAVE_PERF_REGS
From: Thomas Gleixner
Split it up as a preparatory step to move the heavy lifting out of
interrupt context.
Signed-off-by: Thomas Gleixner
---
kernel/time/posix-cpu-timers.c | 43 ++---
1 file changed, 24 insertions(+), 19 deletions(-)
---
This is the 3rd installment of the series to move posix timer expiry heavy
lifting out of hard interrupt context.
Running posix CPU timers in hard interrupt context has a few downsides:
- For PREEMPT_RT it cannot work as the expiry code needs to take
sighand lock, which is a 'sleeping
From: Thomas Gleixner
Running posix CPU timers in hard interrupt context has a few downsides:
- For PREEMPT_RT it cannot work as the expiry code needs to take
sighand lock, which is a 'sleeping spinlock' in RT. The original RT
approach of offloading the posix CPU timer handling into a
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 83bdc7275e6206f560d247be856bceba3e1ed8f2
commit: 797047f875b5463719cc70ba213eb691d453c946 net: ks8851: Implement
Parallel bus operations
date: 9 weeks ago
config: arm-randconfig-s031-20200730 (attached
Mike Rapoport writes:
> From: Mike Rapoport
>
> fadump_reserve_crash_area() reserves memory from a specified base address
> till the end of the RAM.
>
> Replace iteration through the memblock.memory with a single call to
> memblock_reserve() with appropriate that will take care of proper memory
On Thu, Jul 30, 2020 at 12:51:16PM +0100, David Howells wrote:
> (3) Al has objections to the ITER_MAPPING iov_iter type that I added
>
>
> https://lore.kernel.org/linux-fsdevel/20200719014436.gg2786...@zeniv.linux.org.uk/
>
> but note that iov_iter_for_each_range() is not actually
On Thu, Jul 30, 2020 at 03:00:19PM +0300, Kirill Tkhai wrote:
> # ls /proc/namespaces/ -l
> lrwxrwxrwx 1 root root 0 Jul 29 16:50 'cgroup:[4026531835]' ->
> 'cgroup:[4026531835]'
> lrwxrwxrwx 1 root root 0 Jul 29 16:50 'ipc:[4026531839]' -> 'ipc:[4026531839]'
> lrwxrwxrwx 1 root root 0 Jul 29
Converts test lib/test_uuid.c to KUnit
Signed-off-by: Arpitha Raghunandan <98.a...@gmail.com>
---
lib/Kconfig.debug | 7 +--
lib/Makefile | 2 +-
lib/{test_uuid.c => uuid_kunit.c} | 84 +--
3 files changed, 28 insertions(+), 65
On Wed, Jul 29, 2020 at 02:51:52PM -0700, Sami Tolvanen wrote:
> Commit f7b93d42945c ("arm64/alternatives: use subsections for replacement
> sequences") breaks LLVM's integrated assembler, because due to its
> one-pass design, it cannot compute instruction sequence lengths before the
> layout for
On Sat, 25 Jul 2020 17:32:04 -0700, Randy Dunlap wrote:
> Delete duplicated words in arch/arm64/ header files.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: linux-arm-ker...@lists.infradead.org
>
> arch/arm64/include/asm/pgtable-hwdef.h |4 ++--
> arch/arm64/include/asm/ptrace.h
On Thu, Jul 30, 2020 at 03:00:08PM +0300, Kirill Tkhai wrote:
> This patch introduces a new IDR and functions to add/remove and iterate
> registered namespaces in the system. It will be used to list namespaces
> in /proc/namespaces/... in next patches.
Looks like you could use an XArray for this
Hi Mike,
On Thu, Jul 30, 2020 at 01:27:48AM +, Mike Stunes wrote:
> Thanks for the updated patches! I applied this patch-set onto commit
> 01634f2bd42e ("Merge branch 'x86/urgent’”) from your tree. It boots,
> but CPU 1 (on a two-CPU VM) is offline at boot, and `chcpu -e 1` returns:
>
>
On Thu, Jul 30, 2020 at 07:47:57PM +0800, Yue Hu wrote:
> From: Yue Hu
>
> Just to identify the kernel fault more clearly.
>
> Signed-off-by: Yue Hu
> ---
> arch/arm64/mm/fault.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/mm/fault.c
IPQ8074 supports split firmware for q6 and m3 as well.
So add support for loading the m3 firmware before q6.
Now the drivers works fine for both split and unified
firmwares.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
Fixed issue in reading halt-regs parameter from device-tree.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
---
drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c
Enable remoteproc WCSS PIL driver with glink
and ssr subdevices. Also configures shared memory
and enables smp2p and mailboxes required for IPC.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 121
Enables scm support, clock is not needed for enabling scm interface.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
PRNG clock is needed by the secure PIL, support for the same
is added in subsequent patches.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++--
1 file changed, 47
Add name for ssr subdevice on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c
On 09.07.2020 23:04, Rob Herring wrote:
> On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote:
>> Add documentation for new optional properties in the exynos bus nodes:
>> samsung,interconnect-parent, #interconnect-cells, bus-width.
>> These properties allow to specify the SoC
Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
Acked-by: Rob Herring
Acked-by: Stephen Boyd
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
1 file changed, 1
IPQ8074 uses secure PIL. Hence, adding the support for the same.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
drivers/remoteproc/qcom_q6v5_wcss.c | 43 ++---
1 file changed, 40 insertions(+), 3
On Tue, Jul 28, 2020 at 05:21:26PM +0200, Jean-Philippe Brucker wrote:
> When a tracing BPF program attempts to read memory without using the
> bpf_probe_read() helper, the verifier marks the load instruction with
> the BPF_PROBE_MEM flag. Since the arm64 JIT does not currently recognize
> this
IPQ8074 needs support for secure pil as well.
Also, currently only unified firmware is supported.
IPQ8074 supports split firmware for q6 and m3, so
adding support for that.
This series is based on Govind's
"[v8] Add non PAS wcss Q6 support for QCS404"
changes since v6:
- Rebased on top of the
Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
Acked-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq8074.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/gcc-ipq8074.c
On 7/30/2020 12:07 AM, Jakub Kicinski wrote:
On Wed, 29 Jul 2020 17:54:08 +0300 Moshe Shemesh wrote:
On 7/28/2020 11:06 PM, Jakub Kicinski wrote:
On Tue, 28 Jul 2020 12:18:30 -0700 Jacob Keller wrote:
On 7/28/2020 11:44 AM, Jakub Kicinski wrote:
From user perspective what's important is
for Marvell
date: 4 months ago
config: arm-randconfig-s031-20200730 (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt
iocg usage_idx is the latest usage index, we should start from the
oldest usage index to show the consecutive NR_USAGE_SLOTS usages.
Signed-off-by: Chengming Zhou
---
tools/cgroup/iocost_monitor.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi,
One more nitpick below...
On Thu, Jul 30, 2020 at 12:25:31AM -0700, Badhri Jagan Sridharan wrote:
> @@ -4786,10 +4807,28 @@ static int devm_tcpm_psy_register(struct tcpm_port
> *port)
> return PTR_ERR_OR_ZERO(port->psy);
> }
>
> +static enum hrtimer_restart
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 83bdc7275e6206f560d247be856bceba3e1ed8f2
commit: 670d0a4b10704667765f7d18f7592993d02783aa sparse: use identifiers to
define address spaces
date: 6 weeks ago
config: arc-randconfig-s032-20200730 (attached
Matthew Wilcox wrote:
> I suspect you don't need to call find_get_pages_contig(). If you look
> at __readahead_batch() in pagemap.h, it does basically what you want
> (other than being wrapped up inside the readahead iterator). You require
> the pages already be pinned in the xarray, so
Hi Sean,
thanks for your review!
On Wed, Jul 29, 2020 at 08:14:55AM -0700, Sean Christopherson wrote:
> On Wed, Jul 29, 2020 at 03:22:31PM +0200, Joerg Roedel wrote:
> Speaking of too large, would it be overly paranoid to add:
>
> BUILD_BUG_ON(sizeof(struct vmcb_control_area) + sizeof(struct
From: Kan Liang
The counter value of a perf task may leak to another RDPMC task.
For example, a perf stat task as below is running on CPU 0.
perf stat -e 'branches,cycles' -- taskset -c 0 ./workload
In the meantime, an RDPMC task, which is also running on CPU 0, may read
the GP counters
On Thu, Jul 30, 2020 at 10:46:43AM +0100, Julien Thierry wrote:
> Julien Thierry (8):
> objtool: Group headers to check in a single list
> objtool: Make sync-check consider the target architecture
> objtool: Move macros describing structures to arch-dependent code
> objtool: Abstract
On 7/30/20 10:57 AM, pet...@infradead.org wrote:
On Thu, Jul 30, 2020 at 10:41:41AM +0100, Julien Thierry wrote:
+ if (file->elf->changed)
+ return elf_write(file->elf);
+ else
+ return 0;
}
I think we can do
On Sun, 2020-07-26 at 21:49 +0530, Rakesh Pillai wrote:
> We do have the usage of napi_gro_receive and netif_receive_skb in mac80211.
> /* deliver to local stack */
> if (rx->napi)
> napi_gro_receive(rx->napi, skb);
> else
>
On 7/30/20 11:03 AM, pet...@infradead.org wrote:
On Thu, Jul 30, 2020 at 10:41:43AM +0100, Julien Thierry wrote:
One orc_entry is associated with each instruction in the object file,
but having the orc_entry contained by the instruction structure forces
architectures not implementing the orc
Convert the i.MX nand controller binding to DT schema format
using json-schema.
Signed-off-by: Anson Huang
---
Documentation/devicetree/bindings/mtd/mxc-nand.txt | 19 --
.../devicetree/bindings/mtd/mxc-nand.yaml | 42 ++
2 files changed, 42 insertions(+),
Convert the gpmi nand controller binding to DT schema format
using json-schema.
Signed-off-by: Anson Huang
---
.../devicetree/bindings/mtd/gpmi-nand.txt | 75 -
.../devicetree/bindings/mtd/gpmi-nand.yaml | 118 +
2 files changed, 118
On Tue, 28 Jul 2020 10:28:07 +0800, Qinglang Miao wrote:
> Use for_each_child_of_node() macro instead of open coding it.
Applied to powerpc/next.
[1/1] powerpc: use for_each_child_of_node() macro
https://git.kernel.org/powerpc/c/b6ac59d39a348af29477d7bfdc3ba23526e3f4ea
cheers
On Mon, 27 Jul 2020 17:42:01 -0500, Gustavo A. R. Silva wrote:
> Replace the existing /* fall through */ comments and its variants with
> the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
> fall-through markings when it is the case.
>
> [1]
>
On Tue, 28 Jul 2020 01:11:12 +0800, Wei Yongjun wrote:
> Gcc report warning as follows:
>
> arch/powerpc/platforms/powernv/pci-sriov.c:602:25: warning:
> variable 'phb' set but not used [-Wunused-but-set-variable]
> 602 | struct pnv_phb*phb;
> | ^~~
>
>
On Fri, 24 Jul 2020 19:25:24 +1000, Michael Ellerman wrote:
> We have custom stack expansion checks that it turns out are extremely
> badly tested and contain bugs, surprise. So add some tests that
> exercise the code and capture the current boundary conditions.
>
> The signal test currently
Hi Tomas,
On 7/30/20 02:02, Tomas Winkler wrote:
> wired_cmd_repeater_auth_stream_req_in has a variable
> length array at the end. we use struct_size() overflow
> macro to determine the size for the allocation and sending
> size.
>
My comments here:
On Mon, Jul 27, 2020 at 11:10:12PM +0200, Uladzislau Rezki (Sony) wrote:
> If the kernel is built with CONFIG_PROVE_RAW_LOCK_NESTING
> option, the lockedp will complain about violation of the
> nesting rules:
>
>
> [ 28.060389] =
> [ 28.060389] [ BUG: Invalid wait
Am Montag, 27. April 2020, 10:11:28 CEST schrieb Rolf Eike Beer:
> From 082ba542ca4c710dcf592a6f9233603b9275d05d Mon Sep 17 00:00:00 2001
> From: Rolf Eike Beer
> Date: Thu, 22 Nov 2018 16:40:49 +0100
> Subject: [PATCH 1/2] scripts: use pkg-config to locate libcrypto
>
> Otherwise build fails if
On Thu, Jul 30, 2020 at 05:38:15AM -0700, kan.li...@linux.intel.com wrote:
> From: Kan Liang
>
> The counter value of a perf task may leak to another RDPMC task.
Sure, but nowhere did you explain why that is a problem.
> The RDPMC instruction is only available for the X86 platform. Only apply
On Thu, 30 Jul 2020 13:27:23 +0100
Catalin Marinas wrote:
> On Thu, Jul 30, 2020 at 07:47:57PM +0800, Yue Hu wrote:
> > From: Yue Hu
> >
> > Just to identify the kernel fault more clearly.
> >
> > Signed-off-by: Yue Hu
> > ---
> > arch/arm64/mm/fault.c | 2 +-
> > 1 file changed, 1
This is the first driver for the MStar/SigmaStar chips.
All of the chips so far have two instances of this
controller.
One instance controls what are called "IRQ" interrupts
by the vendor code I have seen.
The other instance controls what are called "FIQ" interrupts
by the vendor code.
Add a driver for the two peripheral interrupt controllers
in MStar MSC313 and other MStar/Sigmastar Armv7 SoCs.
Supports both the "IRQ" and "FIQ" controllers that
forward interrupts from the various IP blocks inside the
SoC to the ARM GIC.
They are basically the same thing except for one
Adds a YAML description of the binding for the msc313-intc.
Signed-off-by: Daniel Palmer
Tested-by: Willy Tarreau
---
.../mstar,msc313-intc.yaml| 79 +++
MAINTAINERS | 1 +
2 files changed, 80 insertions(+)
create mode
Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7
dtsi. All of the know SoCs have both and at the same place with
their common IPs using the same interrupt lines.
Signed-off-by: Daniel Palmer
Tested-by: Willy Tarreau
---
arch/arm/boot/dts/mstar-v7.dtsi | 20
Hi all,
Gentle ping on this patch.
Thanks!
Hanks Chen
On Wed, 2020-07-22 at 17:21 +0200, Matthias Brugger wrote:
>
> On 22/07/2020 13:16, Hanks Chen wrote:
> > On Wed, 2020-07-22 at 10:43 +0200, Matthias Brugger wrote:
> >>
> >> On 22/07/2020 05:09, Hanks Chen wrote:
> >>> remove the
On Wed, Jul 29, 2020 at 08:43:28AM -0700, Sean Christopherson wrote:
> Rather than manually calculate the byte/bit indices just use __set_bit()
> and test_bit(). That will also solve the variable declaration issue.
>
> E.g.
>
> #define GHB_BITMAP_IDX(field) \
> (offsetof(struct
The name Unix seems to go back to a Scanza (pre-christian name of
Norway) tribe, also.
We earlier discussed the Sami Tor idol, and this is where it seems to go.
These facts also make the name sdX fit perfectly, again a supply and
demand principle based OS.
Serenity!
Ywe Cærlyn
On 7/30/20 03:41, Takashi Iwai wrote:
> On Thu, 30 Jul 2020 00:18:29 +0200,
> Gustavo A. R. Silva wrote:
>>
>> Make use of the flex_array_size() helper to calculate the size of a
>> flexible array member within an enclosing structure.
>>
>> This helper offers defense-in-depth against potential
Change i.MX27 nand node name from "nand" to "nand-controller" to
be compliant with yaml schema, it requires the nodename to be
"nand-controller".
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx27.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Thu, Jul 30, 2020 at 02:59:20PM +0300, Kirill Tkhai wrote:
> Currently, there is no a way to list or iterate all or subset of namespaces
> in the system. Some namespaces are exposed in /proc/[pid]/ns/ directories,
> but some also may be as open files, which are not attached to a process.
> When
Change i.MX SoCs nand node name from "gpmi-nand" to "nand-controller" to
be compliant with yaml schema, it requires the nodename to be
"nand-controller".
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx23-evk.dts| 2 +-
arch/arm/boot/dts/imx23.dtsi | 2 +-
> This is quite clever, but now I’m wondering just how much kernel help
> is really needed. In your series, the trampoline is an non-executable
> page. I can think of at least two alternative approaches, and I'd
> like to know the pros and cons.
>
> 1. Entirely userspace: a return trampoline
On Thu, 2020-07-30 at 12:51 +0100, David Howells wrote:
> Hi Linus, Trond/Anna, Steve, Eric,
>
> I have an fscache rewrite that I'm tempted to put in for the next merge
> window:
>
>
>
Hi, Philipp
> Subject: Re: [PATCH V3 3/3] pci: imx: Select RESET_IMX7 by default
>
> Hi Anson,
>
> On Thu, 2020-07-30 at 02:11 +, Anson Huang wrote:
> > Hi, Philipp/Rob
> >
> > > Subject: Re: [PATCH V3 3/3] pci: imx: Select RESET_IMX7 by default
> > >
> > > On Wed, 2020-07-29 at 09:26
From: Ofir Bitton
habanalabs driver uses dma-fence mechanism for synchronization.
dma-fence mechanism was designed solely for GPUs, hence we purpose
a simpler mechanism based on completions to replace current
dma-fence objects.
Signed-off-by: Ofir Bitton
Cc: Greg Kroah-Hartman
Cc: Daniel
From: Ofir Bitton
Update firmware header with new API for getting pcie info
such as tx/rx throughput and replay counter.
These counters are needed by customers for monitor and maintenance
of multiple devices.
Add new opcodes to the INFO ioctl to retrieve these counters.
Signed-off-by: Ofir
Linus Torvalds writes:
> On Tue, Jul 28, 2020 at 6:23 AM Eric W. Biederman
> wrote:
>>
>> For exec all I care about are user space threads. So it appears the
>> freezer infrastructure adds very little.
>
> Yeah. 99% of the freezer stuff is for just adding the magic notations
> for kernel
On 30.07.2020 15:18, Alexey Dobriyan wrote:
> On Thu, Jul 30, 2020 at 03:00:19PM +0300, Kirill Tkhai wrote:
>
>> # ls /proc/namespaces/ -l
>> lrwxrwxrwx 1 root root 0 Jul 29 16:50 'cgroup:[4026531835]' ->
>> 'cgroup:[4026531835]'
>> lrwxrwxrwx 1 root root 0 Jul 29 16:50 'ipc:[4026531839]' ->
>>
On Thu, Jul 30, 2020 at 01:40:42PM +0100, Julien Thierry wrote:
>
>
> On 7/30/20 10:57 AM, pet...@infradead.org wrote:
> > On Thu, Jul 30, 2020 at 10:41:41AM +0100, Julien Thierry wrote:
> > > + if (file->elf->changed)
> > > + return elf_write(file->elf);
> > > +
> On Thu, Jul 30, 2020 at 04:13:35PM +0800, Brent Lu wrote:
> > From: Yu-Hsuan Hsu
> >
> > The CRAS server does not set the period size in hw_param so ALSA will
> > calculate a value for period size which is based on the buffer size
> > and other parameters. The value may not always be aligned
On 2020/7/30 19:04, Jiri Slaby wrote:
On 13. 07. 20, 12:57, Yang Yingliang wrote:
I got a slab-out-of-bounds report when I doing fuzz test.
[ 334.989515]
==
[ 334.989577] BUG: KASAN: slab-out-of-bounds in
It is possible to turn the motor on/off just by enabling/disabling
the vcc-supply. Change the binding to require either enable-gpios
or vcc-supply or both.
Signed-off-by: Ondrej Jirman
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/input/gpio-vibrator.yaml | 7 ++-
1 file
Make enable-gpio optional to allow using this driver with boards that
have vibrator connected to a power supply without intermediate gpio
based enable circuitry.
Also avoid a case where neither regulator nor enable gpio is specified,
and bail out in probe in such a case.
Signed-off-by: Ondrej
Vibrator motor is weak at the current voltage. Increase the voltage.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
The board has a vibrator motor. Hook it to the input subsystem.
According to the PMIC specification, LDO needs to be enabled (value 0b11)
to achieve the specified max driving current of 150mA. We can't drive
the motor with just GPIO mode.
In GPIO mode the chip is probably just using the regular
The tablet has a vibrator motor. This patch series exposes it via
input subsystem (EV_FF).
I'd like to ask input maintainers to take the patches 1 and 2.
Patches 3 and 4 should go via the sunxi tree.
The change to the vibrator driver is meant to enable toggling the
vibrator motor just via a
Some compilers may put a subset of generated functions into '.text.*'
ELF sections and the linker may leverage this division to optimize ELF
layout. Unfortunately, the recently introduced HYPCOPY command assumes
that all executable code (with the exception of specialized sections
such as
On 7/30/20 04:21, Ido Schimmel wrote:
> On Wed, Jul 29, 2020 at 05:58:03PM -0500, Gustavo A. R. Silva wrote:
>> Make use of the flex_array_size() helper to calculate the size of a
>> flexible array member within an enclosing structure.
>>
>> This helper offers defense-in-depth against potential
On Thu, Jul 30, 2020 at 03:00:19PM +0300, Kirill Tkhai wrote:
> This is a new directory to show all namespaces, which can be
> accessed from this /proc tasks credentials.
>
> Every /proc is related to a pid_namespace, and the pid_namespace
> is related to a user_namespace. The items, we show in
On 7/30/20 2:22 PM, pet...@infradead.org wrote:
On Thu, Jul 30, 2020 at 01:40:42PM +0100, Julien Thierry wrote:
On 7/30/20 10:57 AM, pet...@infradead.org wrote:
On Thu, Jul 30, 2020 at 10:41:41AM +0100, Julien Thierry wrote:
+ if (file->elf->changed)
+
Add MT6779 UART0 clock support.
Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
Signed-off-by: Wendell Lin
Signed-off-by: Hanks Chen
Reviewed-by: Matthias Brugger
---
drivers/clk/mediatek/clk-mt6779.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Andy Teng
Add devicetree bindings for MediaTek MT6779 pinctrl driver.
Signed-off-by: Andy Teng
Signed-off-by: Hanks Chen
---
.../pinctrl/mediatek,mt6779-pinctrl.yaml | 202 ++
1 file changed, 202 insertions(+)
create mode 100644
this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
Signed-off-by: Hanks Chen
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
Change since v10:
Commit "dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC"
-- remove the patches which were applied to linux-next
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=b07b616214857c9db01e2807cde2f6bba8019fc3
-- follow the latest 'dt-schema' and
On 30.07.2020 15:23, Matthew Wilcox wrote:
> On Thu, Jul 30, 2020 at 03:00:08PM +0300, Kirill Tkhai wrote:
>> This patch introduces a new IDR and functions to add/remove and iterate
>> registered namespaces in the system. It will be used to list namespaces
>> in /proc/namespaces/... in next
On Thu, Jul 30, 2020 at 01:40:48PM +0100, Julien Thierry wrote:
>
>
> On 7/30/20 11:03 AM, pet...@infradead.org wrote:
> > On Thu, Jul 30, 2020 at 10:41:43AM +0100, Julien Thierry wrote:
> > > One orc_entry is associated with each instruction in the object file,
> > > but having the orc_entry
NACK!
Please, stop doing this. You clearly don't know what you're doing.
You're just blindly copying/pasting all this. The subject line
has nothing to do with what the patch does and we don't want
any of these transformations in UAPI for now.
As I already said here:
On Thu, Jul 30, 2020 at 02:59:25PM +0300, Kirill Tkhai wrote:
> Currently, every type of namespaces has its own counter,
> which is stored in ns-specific part. Say, @net has
> struct net::count, @pid has struct pid_namespace::kref, etc.
>
> This patchset introduces unified counter for all types
>
On 30. 07. 20, 15:24, Yang Yingliang wrote:
>
> On 2020/7/30 19:04, Jiri Slaby wrote:
>> On 13. 07. 20, 12:57, Yang Yingliang wrote:
>>> I got a slab-out-of-bounds report when I doing fuzz test.
>>>
>>> [ 334.989515]
>>> ==
>>> [
[Cc: linux-api]
On Thu, Jul 30, 2020 at 03:08:53PM +0200, Christian Brauner wrote:
> On Thu, Jul 30, 2020 at 02:59:20PM +0300, Kirill Tkhai wrote:
> > Currently, there is no a way to list or iterate all or subset of namespaces
> > in the system. Some namespaces are exposed in /proc/[pid]/ns/
Plane validation uses an API drm_calc_scale which will
return src/dst value as a scale ratio.
when viewing the range on a scale the values should fall in as
Upscale ratio < Unity scale < Downscale ratio for src/dst formula
Fix the min and max scale ratios to suit the API accordingly.
Hello,
On Wed, Jul 29, 2020 at 05:48:09PM +0200, Guido Günther wrote:
> Hi,
> On Sat, Jul 18, 2020 at 07:42:15PM +0200, Ondřej Jirman wrote:
> > Hello,
> >
> > On Sat, Jul 18, 2020 at 07:31:24PM +0200, Guido Günther wrote:
> > > Hi,
> > > On Thu, Jul 16, 2020 at 04:32:09PM +0200, Ondřej Jirman
Hi Dave,
On 7/27/20 3:21 PM, David Miller wrote:
From: Murali Karicheri
Date: Wed, 22 Jul 2020 10:40:15 -0400
This series is dependent on the following patches sent out to
netdev list. All (1-3) are already merged to net/master as of
sending this, but not on the net-next master branch. So
On 7/30/20 2:33 PM, pet...@infradead.org wrote:
On Thu, Jul 30, 2020 at 01:40:48PM +0100, Julien Thierry wrote:
On 7/30/20 11:03 AM, pet...@infradead.org wrote:
On Thu, Jul 30, 2020 at 10:41:43AM +0100, Julien Thierry wrote:
One orc_entry is associated with each instruction in the object
Hi Dave,
On 7/17/20 11:22 AM, Murali Karicheri wrote:
This patch enhances the iplink command to add a proto parameters to
create PRP device/interface similar to HSR. Both protocols are
quite similar and requires a pair of Ethernet interfaces. So re-use
the existing HSR iplink command to create
Le samedi 25 juillet 2020 à 22:30 +0900, Alexandre Courbot a écrit :
> On Thu, Jul 16, 2020 at 5:23 AM Ezequiel Garcia
> wrote:
> > The prediction weight parameters are only required under
> > certain conditions, which depend on slice header parameters.
> >
> > The slice header syntax specifies
On Thu, Jul 30, 2020 at 01:23:57PM +, Lu, Brent wrote:
> > On Thu, Jul 30, 2020 at 04:13:35PM +0800, Brent Lu wrote:
> > > From: Yu-Hsuan Hsu
> > >
> > > The CRAS server does not set the period size in hw_param so ALSA will
> > > calculate a value for period size which is based on the buffer
On Thu, Jul 30, 2020 at 1:48 PM Andy Shevchenko
wrote:
> On Thu, Jul 30, 2020 at 11:18:04AM +0200, Arnd Bergmann wrote:
> > The in_ia32_syscall() check should be completely reliable in telling whether
> > we are called from read() by an ia32 task or not, and we use the same
> > logic for
On Thu, 30 Jul 2020 14:25:19 +0100, David Brazdil wrote:
> Some compilers may put a subset of generated functions into '.text.*'
> ELF sections and the linker may leverage this division to optimize ELF
> layout. Unfortunately, the recently introduced HYPCOPY command assumes
> that all executable
1. The group_has_capacity() function is only called in
group_classify().
2. Before calling the group_has_capacity() function,
group_is_overloaded() will first judge the following
formula, if it holds, the group_classify() will directly
return the group_overloaded.
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