Hi,
On Tue, Mar 21, 2017 at 9:24 PM, Cao jin wrote:
> Include whitespace shooting; correction; typo fix; superfluous word
> dropping.
>
> diff --git a/Documentation/PCI/pci-error-recovery.txt
> b/Documentation/PCI/pci-error-recovery.txt
> index da3b217..0b6bb3e 100644
Hi,
On Tue, Mar 21, 2017 at 9:24 PM, Cao jin wrote:
> Include whitespace shooting; correction; typo fix; superfluous word
> dropping.
>
> diff --git a/Documentation/PCI/pci-error-recovery.txt
> b/Documentation/PCI/pci-error-recovery.txt
> index da3b217..0b6bb3e 100644
> ---
The SinA31s has a coaxial SPDIF output. Enable it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
The SinA31s has a coaxial SPDIF output. Enable it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index
On Tue, Mar 21, 2017 at 5:15 PM, Bard Liao wrote:
>> -Original Message-
>> From: Kai-Heng Feng [mailto:kai.heng.f...@canonical.com]
>> Sent: Tuesday, March 21, 2017 1:26 PM
>> To: Mark Brown
>> Cc: Liam Girdwood; Bard Liao; Oder Chiou; alsa-de...@alsa-project.org;
>>
On Tue, Mar 21, 2017 at 5:15 PM, Bard Liao wrote:
>> -Original Message-
>> From: Kai-Heng Feng [mailto:kai.heng.f...@canonical.com]
>> Sent: Tuesday, March 21, 2017 1:26 PM
>> To: Mark Brown
>> Cc: Liam Girdwood; Bard Liao; Oder Chiou; alsa-de...@alsa-project.org;
>>
Hi,
On Tue, Mar 21, 2017 at 02:39:34AM +1000, Nicholas Piggin wrote:
> > @@ -241,8 +240,9 @@ static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
> > * The default stop state that will be used by ppc_md.power_save
> > * function on platforms that support stop instruction.
> > */
> >
Hi,
On Tue, Mar 21, 2017 at 02:39:34AM +1000, Nicholas Piggin wrote:
> > @@ -241,8 +240,9 @@ static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
> > * The default stop state that will be used by ppc_md.power_save
> > * function on platforms that support stop instruction.
> > */
> >
Hi Nick,
On Tue, Mar 21, 2017 at 02:35:17AM +1000, Nicholas Piggin wrote:
> On Mon, 20 Mar 2017 21:24:15 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > Move the piece of code in
Hi Nick,
On Tue, Mar 21, 2017 at 02:35:17AM +1000, Nicholas Piggin wrote:
> On Mon, 20 Mar 2017 21:24:15 +0530
> "Gautham R. Shenoy" wrote:
>
> > From: "Gautham R. Shenoy"
> >
> > Move the piece of code in powernv/smp.c::pnv_smp_cpu_kill_self() which
> > transitions the CPU to the deepest
Add initial support for boards based on Satixfy's SX3000b (Catniss) SoC.
The SoC includes a MIPS interAptiv dual core 4 VPE processor and boots
using device-tree.
Signed-off-by: Amit Kama
The irqchip file (irq-sx3000b.c) is pertinent to the platform.
IRQCHIP maintainers
Add initial support for boards based on Satixfy's SX3000b (Catniss) SoC.
The SoC includes a MIPS interAptiv dual core 4 VPE processor and boots
using device-tree.
Signed-off-by: Amit Kama
The irqchip file (irq-sx3000b.c) is pertinent to the platform.
IRQCHIP maintainers - is it possible to
On Tue, Mar 21, 2017 at 4:59 PM, Bard Liao wrote:
>> -Original Message-
>> From: Kai-Heng Feng [mailto:kai.heng.f...@canonical.com]
>> Sent: Tuesday, March 21, 2017 1:39 PM
>> To: Bard Liao
>> Cc: broo...@kernel.org; lgirdw...@gmail.com; Oder Chiou;
>>
On Tue, Mar 21, 2017 at 4:59 PM, Bard Liao wrote:
>> -Original Message-
>> From: Kai-Heng Feng [mailto:kai.heng.f...@canonical.com]
>> Sent: Tuesday, March 21, 2017 1:39 PM
>> To: Bard Liao
>> Cc: broo...@kernel.org; lgirdw...@gmail.com; Oder Chiou;
>> alsa-de...@alsa-project.org;
On Wed, Mar 22, 2017 at 01:41:17PM +0900, Minchan Kim wrote:
> Hi Tim,
>
> On Tue, Mar 21, 2017 at 10:18:26AM -0700, Tim Murray wrote:
> > On Sun, Mar 19, 2017 at 10:59 PM, Minchan Kim wrote:
> > > However, I'm not sure your approach is good. It seems your approach just
> > >
On Wed, Mar 22, 2017 at 01:41:17PM +0900, Minchan Kim wrote:
> Hi Tim,
>
> On Tue, Mar 21, 2017 at 10:18:26AM -0700, Tim Murray wrote:
> > On Sun, Mar 19, 2017 at 10:59 PM, Minchan Kim wrote:
> > > However, I'm not sure your approach is good. It seems your approach just
> > > reclaims pages from
Greg, hope you had not faced any issue (tab converted to spaces) with this
patch.
In case still facing any issue please let me know.
> There is race condition when two USB class drivers try to call
> init_usb_class at the same time and leads to crash.
> code path:
Greg, hope you had not faced any issue (tab converted to spaces) with this
patch.
In case still facing any issue please let me know.
> There is race condition when two USB class drivers try to call
> init_usb_class at the same time and leads to crash.
> code path:
On Tue, Mar 21, 2017 at 9:27 PM, Andy Lutomirski wrote:
> On Tue, Mar 21, 2017 at 5:41 PM, Thomas Garnier wrote:
>> On Tue, Mar 21, 2017 at 4:51 PM, Andy Lutomirski wrote:
>>> On Tue, Mar 21, 2017 at 3:32 PM, Andy Lutomirski
On Tue, Mar 21, 2017 at 9:27 PM, Andy Lutomirski wrote:
> On Tue, Mar 21, 2017 at 5:41 PM, Thomas Garnier wrote:
>> On Tue, Mar 21, 2017 at 4:51 PM, Andy Lutomirski wrote:
>>> On Tue, Mar 21, 2017 at 3:32 PM, Andy Lutomirski
>>> wrote:
On Tue, Mar 21, 2017 at 2:11 PM, Linus Torvalds
hi,
Could you please give some feedback or review comments for this patch
On 3/14/17, Vinay Simha BN wrote:
> 4 macros already defined in hdmi.h,
> which is not required to redefine in hdmi_audio.c
>
> Signed-off-by: Vinay Simha BN
> ---
>
hi,
Could you please give some feedback or review comments for this patch
On 3/14/17, Vinay Simha BN wrote:
> 4 macros already defined in hdmi.h,
> which is not required to redefine in hdmi_audio.c
>
> Signed-off-by: Vinay Simha BN
> ---
> drivers/gpu/drm/msm/hdmi/hdmi_audio.c | 7 ---
>
Hi,
On 21 March 2017 at 16:07, Felipe Balbi wrote:
>
> Hi,
>
> Baolin Wang writes:
I don't yet understand why we can't just keep runtime pm disabled as a
default for xhci platform devices.
It could be enabled by whatever creates the
Hi,
On 21 March 2017 at 16:07, Felipe Balbi wrote:
>
> Hi,
>
> Baolin Wang writes:
I don't yet understand why we can't just keep runtime pm disabled as a
default for xhci platform devices.
It could be enabled by whatever creates the platform device by setting some
device
Hi Tim,
On Tue, Mar 21, 2017 at 10:18:26AM -0700, Tim Murray wrote:
> On Sun, Mar 19, 2017 at 10:59 PM, Minchan Kim wrote:
> > However, I'm not sure your approach is good. It seems your approach just
> > reclaims pages from groups (DEF_PRIORITY - memcg->priority) >=
Hi Tim,
On Tue, Mar 21, 2017 at 10:18:26AM -0700, Tim Murray wrote:
> On Sun, Mar 19, 2017 at 10:59 PM, Minchan Kim wrote:
> > However, I'm not sure your approach is good. It seems your approach just
> > reclaims pages from groups (DEF_PRIORITY - memcg->priority) >= sc->priority.
> > IOW, it is
On Tue, Mar 21, 2017 at 5:41 PM, Thomas Garnier wrote:
> On Tue, Mar 21, 2017 at 4:51 PM, Andy Lutomirski wrote:
>> On Tue, Mar 21, 2017 at 3:32 PM, Andy Lutomirski wrote:
>>> On Tue, Mar 21, 2017 at 2:11 PM, Linus Torvalds
>>>
Hi,
On Mon, Mar 20, 2017 at 4:16 PM, Quentin Schulz
wrote:
> The X-Powers AXP20X and AXP22X PMICs have multiple ADCs. They expose the
> battery voltage, battery charge and discharge currents, AC-in and VBUS
> voltages and currents, 2 GPIOs muxable in ADC mode
86_64-2016-04-22.cgz-b7ef62aa8a7aebb156ce093e3215fb821426fc1b-20170321-127060-hr3r1t-0.cgz
/lkp/lkp/lkp-x86_64.cgz
To reproduce:
git clone https://github.com/01org/lkp-tests.git
cd lkp-tests
bin/lkp qemu -k job-script # job-script is attached in this
email
On Tue, Mar 21, 2017 at 5:41 PM, Thomas Garnier wrote:
> On Tue, Mar 21, 2017 at 4:51 PM, Andy Lutomirski wrote:
>> On Tue, Mar 21, 2017 at 3:32 PM, Andy Lutomirski wrote:
>>> On Tue, Mar 21, 2017 at 2:11 PM, Linus Torvalds
>>> wrote:
On Tue, Mar 21, 2017 at 1:25 PM, Thomas Garnier
Hi,
On Mon, Mar 20, 2017 at 4:16 PM, Quentin Schulz
wrote:
> The X-Powers AXP20X and AXP22X PMICs have multiple ADCs. They expose the
> battery voltage, battery charge and discharge currents, AC-in and VBUS
> voltages and currents, 2 GPIOs muxable in ADC mode and PMIC temperature.
>
> This adds
86_64-2016-04-22.cgz-b7ef62aa8a7aebb156ce093e3215fb821426fc1b-20170321-127060-hr3r1t-0.cgz
/lkp/lkp/lkp-x86_64.cgz
To reproduce:
git clone https://github.com/01org/lkp-tests.git
cd lkp-tests
bin/lkp qemu -k job-script # job-script is attached in this
email
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
.../staging/media/atomisp/pci/atomisp2/atomisp_cmd.c | 12 ++--
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
drivers/staging/media/davinci_vpfe/dm365_ipipe.c | 2 +-
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
.../staging/media/atomisp/pci/atomisp2/atomisp_cmd.c | 12 ++--
.../media/atomisp/pci/atomisp2/atomisp_compat_css20.c | 6
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
drivers/staging/media/davinci_vpfe/dm365_ipipe.c | 2 +-
drivers/staging/media/davinci_vpfe/dm365_ipipeif.c | 2 +-
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
drivers/staging/media/omap4iss/iss_csi2.c| 2 +-
drivers/staging/media/omap4iss/iss_ipipe.c | 2
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
drivers/staging/media/omap4iss/iss_csi2.c| 2 +-
drivers/staging/media/omap4iss/iss_ipipe.c | 2 +-
On 03/21/17 at 10:18pm, Eric W. Biederman wrote:
> Dave Young writes:
>
> > On 03/20/17 at 10:33pm, Eric W. Biederman wrote:
> >> Xunlei Pang writes:
> >>
> >> > As Eric said,
> >> > "what we need to do is move the variable vmcoreinfo_note out
> >> > of
On 03/21/17 at 10:18pm, Eric W. Biederman wrote:
> Dave Young writes:
>
> > On 03/20/17 at 10:33pm, Eric W. Biederman wrote:
> >> Xunlei Pang writes:
> >>
> >> > As Eric said,
> >> > "what we need to do is move the variable vmcoreinfo_note out
> >> > of the kernel's .bss section. And modify
Hi all,
Changes since 20170321:
The drm tree gained conflicts against the drm-intel-fixes tree.
The char-misc tree gained a conflict against the tpmdd tree.
The char-misc tree still had its build failure for which I applied a
fix patch.
The livepatching tree gained a conflict against the tip
Hi all,
Changes since 20170321:
The drm tree gained conflicts against the drm-intel-fixes tree.
The char-misc tree gained a conflict against the tpmdd tree.
The char-misc tree still had its build failure for which I applied a
fix patch.
The livepatching tree gained a conflict against the tip
Replace a bit shift by a use of BIT in media driver.
Arushi Singhal (3):
staging: media: Replace a bit shift by a use of BIT.
staging: media: davinci_vpfe: Replace a bit shift by a use of BIT.
staging: media: omap4iss: Replace a bit shift by a use of BIT.
Replace a bit shift by a use of BIT in media driver.
Arushi Singhal (3):
staging: media: Replace a bit shift by a use of BIT.
staging: media: davinci_vpfe: Replace a bit shift by a use of BIT.
staging: media: omap4iss: Replace a bit shift by a use of BIT.
From: Kuninori Morimoto
SYS-DMAC can use 40bit address transfer, and it supports Descriptor
Mode too. Current SYS-DMAC driver disables Descriptor Mode if it was
40bit address today. But it can use Descriptor Mode with 40bit if
transfer Source/Destination
From: Kuninori Morimoto
SYS-DMAC can use 40bit address transfer, and it supports Descriptor
Mode too. Current SYS-DMAC driver disables Descriptor Mode if it was
40bit address today. But it can use Descriptor Mode with 40bit if
transfer Source/Destination address are located in same 4GiB region
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
drivers/staging/octeon/ethernet-tx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
drivers/staging/octeon/ethernet-tx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 22-03-17, 01:56, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> sugov_update_commit() calls trace_cpu_frequency() to record the
> current CPU frequency if it has not changed in the fast switch case
> to prevent utilities from getting confused (they may
On 22-03-17, 01:56, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> sugov_update_commit() calls trace_cpu_frequency() to record the
> current CPU frequency if it has not changed in the fast switch case
> to prevent utilities from getting confused (they may report that the
> CPU is idle if
On Tue, Mar 21, 2017 at 11:36 PM, Quentin Schulz
wrote:
> This adds almost all operating points allowed for the A33 as defined by
> fex files available at:
> https://github.com/linux-sunxi/sunxi-boards/tree/master/sys_config/a33
>
> There are more possible
On Tue, Mar 21, 2017 at 11:36 PM, Quentin Schulz
wrote:
> This adds almost all operating points allowed for the A33 as defined by
> fex files available at:
> https://github.com/linux-sunxi/sunxi-boards/tree/master/sys_config/a33
>
> There are more possible frequencies in this patch than there are
Hi Florian,
On Sun, Mar 19, 2017 at 12:50 PM, Florian Fainelli wrote:
> The CPU port of the BCM53125 is configured with RGMII (no delays) but
> this should actually be RGMII with transmit delay (rgmii-txid) because
> STMMAC takes care of inserting the transmitter delay.
Hi Florian,
On Sun, Mar 19, 2017 at 12:50 PM, Florian Fainelli wrote:
> The CPU port of the BCM53125 is configured with RGMII (no delays) but
> this should actually be RGMII with transmit delay (rgmii-txid) because
> STMMAC takes care of inserting the transmitter delay. This fixes
> occasional
Thanks for this, I'm getting enough questions about this, so it's nice to
have a link :)
First comment: I don't think rst requires unwrapped lines, so please break
those up.
Second comment: I'd really like to have a link to libevdev here. It has a
uinput interface that's a bit more obvious and
Thanks for this, I'm getting enough questions about this, so it's nice to
have a link :)
First comment: I don't think rst requires unwrapped lines, so please break
those up.
Second comment: I'd really like to have a link to libevdev here. It has a
uinput interface that's a bit more obvious and
Hello,
with commit: 0a943cb10ce7 (tools build: Add HOSTARCH Makefile variable),
the following build failure is seen with ARCH=x86_84 when build for perf
In file included from util/event.c:2:0:
tools/include/uapi/linux/mman.h:4:27: fatal error: uapi/asm/mman.h: No
such file or directory
Hello,
with commit: 0a943cb10ce7 (tools build: Add HOSTARCH Makefile variable),
the following build failure is seen with ARCH=x86_84 when build for perf
In file included from util/event.c:2:0:
tools/include/uapi/linux/mman.h:4:27: fatal error: uapi/asm/mman.h: No
such file or directory
On Tue, 21 Mar 2017 02:59:46 +1000
Nicholas Piggin wrote:
> On Mon, 20 Mar 2017 21:24:18 +0530
> This is quite neat now you've moved it to its own function. Nice.
> It will be only a trivial clash with my patches now, I think.
>
> Reviewed-by: Nicholas Piggin
On Tue, 21 Mar 2017 02:59:46 +1000
Nicholas Piggin wrote:
> On Mon, 20 Mar 2017 21:24:18 +0530
> This is quite neat now you've moved it to its own function. Nice.
> It will be only a trivial clash with my patches now, I think.
>
> Reviewed-by: Nicholas Piggin
Hmm... This won't actually work
On Tue, Mar 21, 2017 at 11:36 PM, Quentin Schulz
wrote:
> This adds the cpu-supply DT property to the cpu0 DT node needed by
> the board to adapt the regulator voltage depending on the currently used
> OPP.
>
> Signed-off-by: Quentin Schulz
On Tue, Mar 21, 2017 at 11:36 PM, Quentin Schulz
wrote:
> This adds the cpu-supply DT property to the cpu0 DT node needed by
> the board to adapt the regulator voltage depending on the currently used
> OPP.
>
> Signed-off-by: Quentin Schulz
Acked-by: Chen-Yu Tsai
There is of_property_read_u32_index but no u64 variant. This patch
adds one similar to the u32 version for u64.
Signed-off-by: Alistair Popple
---
drivers/of/base.c | 31 +++
include/linux/of.h | 3 +++
2 files changed, 34 insertions(+)
diff
There is of_property_read_u32_index but no u64 variant. This patch
adds one similar to the u32 version for u64.
Signed-off-by: Alistair Popple
---
drivers/of/base.c | 31 +++
include/linux/of.h | 3 +++
2 files changed, 34 insertions(+)
diff --git
The pnv_pci_get_{gpu|npu}_dev functions are used to find associations
between nvlink PCIe devices and standard PCIe devices. However they
lacked basic sanity checking which results in NULL pointer
dereferencing if they are incorrectly called which can be harder to
spot than an explicit WARN_ON.
The pnv_pci_get_{gpu|npu}_dev functions are used to find associations
between nvlink PCIe devices and standard PCIe devices. However they
lacked basic sanity checking which results in NULL pointer
dereferencing if they are incorrectly called which can be harder to
spot than an explicit WARN_ON.
Nvlink2 supports address translation services (ATS) allowing devices
to request address translations from an mmu known as the nest MMU
which is setup to walk the CPU page tables.
To access this functionality certain firmware calls are required to
setup and manage hardware context tables in the
Nvlink2 supports address translation services (ATS) allowing devices
to request address translations from an mmu known as the nest MMU
which is setup to walk the CPU page tables.
To access this functionality certain firmware calls are required to
setup and manage hardware context tables in the
On Thursday 09 March 2017 01:35 PM, Keerthy wrote:
> Currently the slope and offset values for calculating the
> hot spot temperature of a particular thermal zone is part
> of driver data. Pass them here instead and obtain the values
> while of node parsing.
>
> Tested for the slope and
On Thursday 09 March 2017 01:35 PM, Keerthy wrote:
> Currently the slope and offset values for calculating the
> hot spot temperature of a particular thermal zone is part
> of driver data. Pass them here instead and obtain the values
> while of node parsing.
>
> Tested for the slope and
On Tue, Mar 21, 2017 at 11:36 PM, Quentin Schulz
wrote:
> The OPP are declared as shared but no operating points are declared for
> cpu1, 2 and 3. Thus, the following error happens during the boot:
>
> cpu cpu1: dev_pm_opp_of_get_sharing_cpus: Couldn't find
On Tue, Mar 21, 2017 at 11:36 PM, Quentin Schulz
wrote:
> The OPP are declared as shared but no operating points are declared for
> cpu1, 2 and 3. Thus, the following error happens during the boot:
>
> cpu cpu1: dev_pm_opp_of_get_sharing_cpus: Couldn't find tcpu_dev node.
>
> This patch applies
On March 22, 2017 10:32 AM Naoya Horiguchi wrote:
>
> I found the race condition which triggers the following bug when
> move_pages() and soft offline are called on a single hugetlb page
> concurrently.
>
> [61163.578957] Soft offlining page 0x119400 at 0x7000
>
On March 22, 2017 10:32 AM Naoya Horiguchi wrote:
>
> I found the race condition which triggers the following bug when
> move_pages() and soft offline are called on a single hugetlb page
> concurrently.
>
> [61163.578957] Soft offlining page 0x119400 at 0x7000
>
On 2017/3/21 23:48, Jingoo Han wrote:
> (+cc: Joao Pinto, Zhou Wang, Gabriele Paoloni)
>
> On Tuesday, March 21, 2017 10:32 AM, Arnd Bergmann wrote:
>>
>> Without PCI_HOST_COMMON support enabled, we get a link error:
>>
>> drivers/pci/dwc/built-in.o: In function `hisi_pcie_map_bus':
>>
On 2017/3/21 23:48, Jingoo Han wrote:
> (+cc: Joao Pinto, Zhou Wang, Gabriele Paoloni)
>
> On Tuesday, March 21, 2017 10:32 AM, Arnd Bergmann wrote:
>>
>> Without PCI_HOST_COMMON support enabled, we get a link error:
>>
>> drivers/pci/dwc/built-in.o: In function `hisi_pcie_map_bus':
>>
Dave Young writes:
> On 03/20/17 at 10:33pm, Eric W. Biederman wrote:
>> Xunlei Pang writes:
>>
>> > As Eric said,
>> > "what we need to do is move the variable vmcoreinfo_note out
>> > of the kernel's .bss section. And modify the code to regenerate
>> >
Dave Young writes:
> On 03/20/17 at 10:33pm, Eric W. Biederman wrote:
>> Xunlei Pang writes:
>>
>> > As Eric said,
>> > "what we need to do is move the variable vmcoreinfo_note out
>> > of the kernel's .bss section. And modify the code to regenerate
>> > and keep this information in something
On Wed, Mar 22, 2017 at 01:58:30AM +0100, Rafael J. Wysocki wrote:
> On Wednesday, March 22, 2017 09:01:48 AM Lee, Chun-Yi wrote:
> > Just checking the state of container is not enough to confirm that
> > the whole container is offlined.
>
> And why is that so?
>
Actually there does not have
On Wed, Mar 22, 2017 at 01:58:30AM +0100, Rafael J. Wysocki wrote:
> On Wednesday, March 22, 2017 09:01:48 AM Lee, Chun-Yi wrote:
> > Just checking the state of container is not enough to confirm that
> > the whole container is offlined.
>
> And why is that so?
>
Actually there does not have
ild test ERROR on v4.11-rc3 next-20170321]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Dongjiu-Geng/kvm-pass-the-virtual-SEI-syndrome-to-guest-OS/20170321-152433
> b
ild test ERROR on v4.11-rc3 next-20170321]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Dongjiu-Geng/kvm-pass-the-virtual-SEI-syndrome-to-guest-OS/20170321-152433
> b
Currently we are adding all components from the dts, if one of their
drivers been disabled, we would not be able to bring up others.
Refactor component match logic, follow exynos drm.
Signed-off-by: Jeffy Chen
Reviewed-by: Andrzej Hajda
Acked-by:
Currently we are adding all components from the dts, if one of their
drivers been disabled, we would not be able to bring up others.
Refactor component match logic, follow exynos drm.
Signed-off-by: Jeffy Chen
Reviewed-by: Andrzej Hajda
Acked-by: Mark Yao
Tested-by: Heiko Stuebner
---
pgprot_dmachoerent() is not defined on every architecture. Having
COMPILE_TEST set for the driver causes it to be compiled on
architectures which do not have pgprot_dmachoerent():
drivers/misc/aspeed-lpc-ctrl.c: In function 'aspeed_lpc_ctrl_mmap':
drivers/misc/aspeed-lpc-ctrl.c:51:9:
pgprot_dmachoerent() is not defined on every architecture. Having
COMPILE_TEST set for the driver causes it to be compiled on
architectures which do not have pgprot_dmachoerent():
drivers/misc/aspeed-lpc-ctrl.c: In function 'aspeed_lpc_ctrl_mmap':
drivers/misc/aspeed-lpc-ctrl.c:51:9:
On 2017年03月21日 18:25, Sergei Shtylyov wrote:
Hello!
On 3/21/2017 7:04 AM, Jason Wang wrote:
Signed-off-by: Jason Wang
---
include/linux/ptr_ring.h | 65
1 file changed, 65 insertions(+)
diff --git
On 2017年03月21日 18:25, Sergei Shtylyov wrote:
Hello!
On 3/21/2017 7:04 AM, Jason Wang wrote:
Signed-off-by: Jason Wang
---
include/linux/ptr_ring.h | 65
1 file changed, 65 insertions(+)
diff --git a/include/linux/ptr_ring.h
On 03/21/2017 10:14 PM, Ming Lei wrote:
> When iterating busy requests in timeout handler,
> if the STARTED flag of one request isn't set, that means
> the request is being processed in block layer or driver, and
> isn't submitted to hardware yet.
>
> In current implementation of
On 03/21/2017 10:14 PM, Ming Lei wrote:
> When iterating busy requests in timeout handler,
> if the STARTED flag of one request isn't set, that means
> the request is being processed in block layer or driver, and
> isn't submitted to hardware yet.
>
> In current implementation of
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
drivers/staging/lustre/lnet/klnds/o2iblnd/o2iblnd.c | 2 +-
Hi guys,
so, after taking some time to understand how to work with uinput, and to grab
some examples
on web, I discovered that kernel doesn't have any "official" documentation
about it.
So, here we are :)
I added some examples based in my tests, there are samples of EV_REL and
EV_KEY, but
we
This patch replaces bit shifting on 1 with the BIT(x) macro.
This was done with coccinelle:
@@
constant c;
@@
-1 << c
+BIT(c)
Signed-off-by: Arushi Singhal
---
drivers/staging/lustre/lnet/klnds/o2iblnd/o2iblnd.c | 2 +-
drivers/staging/lustre/lnet/klnds/socklnd/socklnd_cb.c|
Hi guys,
so, after taking some time to understand how to work with uinput, and to grab
some examples
on web, I discovered that kernel doesn't have any "official" documentation
about it.
So, here we are :)
I added some examples based in my tests, there are samples of EV_REL and
EV_KEY, but
we
On 03/20/17 at 10:33pm, Eric W. Biederman wrote:
> Xunlei Pang writes:
>
> > As Eric said,
> > "what we need to do is move the variable vmcoreinfo_note out
> > of the kernel's .bss section. And modify the code to regenerate
> > and keep this information in something like the
Hello Xie XiuQi,
On 3/21/2017 8:48 PM, Xie XiuQi wrote:
Reviewed-by: Xie XiuQi
Thank you!
Tyler
On 2017/3/22 6:47, Tyler Baicar wrote:
Currently there are trace events for the various RAS
errors with the exception of ARM processor type errors.
Add a new trace event for
On 03/20/17 at 10:33pm, Eric W. Biederman wrote:
> Xunlei Pang writes:
>
> > As Eric said,
> > "what we need to do is move the variable vmcoreinfo_note out
> > of the kernel's .bss section. And modify the code to regenerate
> > and keep this information in something like the control page.
> >
>
Hello Xie XiuQi,
On 3/21/2017 8:48 PM, Xie XiuQi wrote:
Reviewed-by: Xie XiuQi
Thank you!
Tyler
On 2017/3/22 6:47, Tyler Baicar wrote:
Currently there are trace events for the various RAS
errors with the exception of ARM processor type errors.
Add a new trace event for such errors so that
On Tue, Mar 21, 2017 at 04:40:40PM -0500, Ming Ma wrote:
> When both "crct10dif-pclmul" algorithm and "crct10dif-generic" algorithm
> exist in crypto_alg_list, "crct10dif-pclmul" should be selected, since it
> has higher priority than "crct10dif-generic". However, both algorithms
> have the same
On Tue, Mar 21, 2017 at 04:40:40PM -0500, Ming Ma wrote:
> When both "crct10dif-pclmul" algorithm and "crct10dif-generic" algorithm
> exist in crypto_alg_list, "crct10dif-pclmul" should be selected, since it
> has higher priority than "crct10dif-generic". However, both algorithms
> have the same
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