On Fri, Mar 7, 2014 at 11:41 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, Mar 5, 2014 at 10:59 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 03/04/2014 07:37 PM, Linus Walleij wrote:
On Wed, Mar 5, 2014 at 10:18 AM, Stephen Warren swar...@wwwdotorg.org
wrote:
On 03/04/2014
On Fri, Mar 7, 2014 at 6:34 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Mar 07, 2014 at 11:07:51AM +0100, Maxime Ripard wrote:
Hi Russell,
On Fri, Mar 07, 2014 at 09:52:23AM +, Russell King - ARM Linux wrote:
On Tue, Mar 04, 2014 at 05:28:37PM +0100, Maxime Ripard
The A20 has EMAC and GMAC muxed on the same pins.
Add pin sets with gmac function for MII and RGMII mode to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 4019c55..18d211e 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch
.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 26 +++
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
The current .init and .exit callbacks requires access to driver
private data structures. This is not a good seperation and abstraction.
Instead, we add a new .setup callback for allocating private data, and
pass the returned pointer to the other callbacks.
Signed-off-by: Chen-Yu Tsai w
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 26
drivers
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++--
1 file changed, 12 insertions(+), 15 deletions(-)
diff
The CubieTruck uses the GMAC with an RGMII phy.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 28
1 file changed, 28
U-Boot will insert MAC address into the device tree image.
It looks up ethernet[0-5] aliases to find the ethernet nodes.
Alias GMAC as ethernet0, as it is the only ethernet controller used.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
1 file changed, 1
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff
, and default to PHY
address auto-detection.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 46 +-
include/linux/stmmac.h | 18 +
2 files changed, 54 insertions(+), 10 deletions(-)
diff --git
snps,force_sf_dma_mode is documented in stmmac device tree bindings,
but is never handled by the driver.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac
-by: Chen-Yu Tsai w...@csie.org
---
include/linux/reset.h | 39 +++
1 file changed, 39 insertions(+)
diff --git a/include/linux/reset.h b/include/linux/reset.h
index 6082247..38aa616 100644
--- a/include/linux/reset.h
+++ b/include/linux/reset.h
@@ -4,6 +4,8
stmmac callbacks have been extended for better seperation.
Update them to avoid breakage.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/blackfin/mach-bf609/boards/ezkit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c
b/arch
that Allwinner uses is unknown,
thus the exact feature set is unknown.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../bindings/net/allwinner,sun7i-a20-gmac.txt | 27 +
drivers/net/ethernet/stmicro/stmmac/Kconfig| 12 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1
The DWMAC has a reset assert line, which is used on some SoCs. Add an
optional reset control to stmmac driver core.
To support reset control deferred probing, this patch changes the driver
probe function to return the actual error, instead of just -EINVAL.
Signed-off-by: Chen-Yu Tsai w
features and callbacks,
instead of platform data, as discussed
* Seperated clock module glue layer into clock driver
Comments?
Thanks,
ChenYu
Chen-Yu Tsai (16):
reset: add non CONFIG_RESET_CONTROLLER routines
net: stmmac: Enable stmmac main clock when probing hardware
net: stmmac
of platform data. This patch specifies
the bindings that allow this platform data to be expressed in the
devicetree.
Cc: Chen-Yu Tsai w...@csie.org
Cc: Tomasz Figa tomasz.f...@gmail.com
Reviewed-by: Hante Meuleman meule...@broadcom.com
Reviewed-by: Pieter-Paul Giesberts piete...@broadcom.com
Hi,
On Fri, Feb 21, 2014 at 12:38 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 02/20/2014 05:51 AM, Heikki Krogerus wrote:
There is no use for them in this driver. This will fix a
static checker warning..
Didn't you remove the use:
- gpio = devm_gpiod_get_index(pdev-dev,
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 28
1 file changed, 28
routines for the above change
* Extended callback API, as discussed with Srinivas
* Used new stmmac_of_data to pass features and callbacks,
instead of platform data, as discussed
* Seperated clock module glue layer into clock driver
Cheers,
ChenYu
Chen-Yu Tsai (8):
clk: sunxi: Add Allwinner
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff
The CubieTruck uses the GMAC with an RGMII phy.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
All Allwinner A20 boards we support can only use either EMAC or GMAC,
as they share the same pins. As we have switched all supported to
GMAC, we should alias GMAC (the active controller) as ethernet0,
so u-boot will insert the MAC address for the correct controller.
Signed-off-by: Chen-Yu Tsai w
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index dd567ea..8eb4d54 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch
The A20 has EMAC and GMAC muxed on the same pins.
Add pin sets with gmac function for MII and RGMII mode to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++--
1 file changed, 12 insertions(+), 15 deletions(-)
diff
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 30 +++
drivers
On tha Allwinner A20 SoC, the external interrupts on the pin controller
device are connected to the GIC. Without chained_irq_{enter, exit},
external GPIO interrupts, such as used by mmc core card detect, cause
the system to hang.
Cc: sta...@vger.kernel.org
Signed-off-by: Chen-Yu Tsai w
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Hi,
This is v5 of the Allwinner A20 GMAC clock patch. Hans noted
Hi,
On Wed, Feb 12, 2014 at 3:33 AM, David Lanzendörfer
david.lanzendoer...@o2s.ch wrote:
This is based on the driver Allwinner ships in their Android kernel sources.
Initial porting to upstream kernels done by David Lanzendörfer, additional
fixes and cleanups by Hans de Goede.
It uses dma
this platform data to be expressed in the
devicetree.
Cc: Chen-Yu Tsai w...@csie.org
Cc: Tomasz Figa tomasz.f...@gmail.com
Reviewed-by: Hante Meuleman meule...@broadcom.com
Reviewed-by: Pieter-Paul Giesberts piete...@broadcom.com
Signed-off-by: Arend van Spriel ar...@broadcom.com
Hi,
On Mon, Jun 9, 2014 at 6:59 PM, LABBE Corentin
clabbe.montj...@gmail.com wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE
On Thu, May 8, 2014 at 11:17 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, May 07, 2014 at 07:25:54PM +0200, Boris BREZILLON wrote:
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.
Signed-off-by: Boris BREZILLON
The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.
This patch extends the sun6i-a31-apb0-clk driver to take divider
tables associated to compatibles, and adds a compatible for the A23
variant.
Signed-off-by: Chen-Yu Tsai
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.
This patch adds an option to the clock driver's config data structures
to define the difference.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-factors.c | 5
The A23 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
drivers/pinctrl/sunxi/Kconfig
factor starts from 1 instead of 0.
This patch adds support for PLL1 and all the basic clock gates.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 4 ++
drivers/clk/sunxi/clk-sunxi.c | 83 +++
2 files changed
-Yu Tsai (22):
serial: 8250_dw: Add optional reset control support
clk: sunxi: register clock gates with clkdev
clk: sunxi: add pll6 to sun6i protected clock list
clk: sunxi: move ahb_sdram to protected clock list
clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates
clk: sunxi: Support
-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index e0e24d5..3e33bc1 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1229,6 +1229,7
The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
and the APB0 clock has different divisors.
This patch adds a compatible with a modified subdevice list for
the A23.
Signed-off-by: Chen-Yu Tsai w...@csie.org
The new important clock protect code requires the clocks be
registered with clkdev. This was missing for sunxi_gates
type clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b
The N factor for PLL6 counts from 1 to 32, as specified in the A23
manual, and shown in Allwinner's original code.
This patch fixes the N factor in the clock driver, as well as the
comment describing it.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 5 +++--
1
The A23 has a R_PIO pin controller, similar to the one found on the A31 SoC.
Add support for the pins controlled by the R_PIO controller.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1
entry. This
results in an extra bogus clock being registered.
This patch adds an entry for the number of child clocks alongside
the data structures for them.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions
On the A31 and A23, the PLL6 input to the AHB1 clock has a 2 bit wide
pre-divider. This was verified from the A23 user manual and A31/A23 SDK
sources.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 ++
drivers/clk/sunxi/clk-sunxi.c
Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
This behavior is consistent with previous SoC's by Allwinner.
Signed-off-by: Chen-Yu Tsai w
The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/mach-sunxi/Kconfig | 8
arch/arm/mach-sunxi/sunxi.c | 12
2 files changed, 20 insertions
.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 51 +
2 files changed, 53 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
diff --git a/arch
On the A31, the PLL6 input to the AHB1 clock has a 2 bit wide
pre-divider. This was verified from the A23 user manual and
A31/A23 SDK sources.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the ahb_sdram clock, instead
of looking for it and adding CLK_IGNORE_UNUSED inline in the
clock setup code.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 10
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 524 +++
1 file changed, 524 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a23
the maximum gate index + 1, so
of_clk_src_onecell_get does not complain about indices greater
than gates registered.
This was tested on the A23 SoC, which has a similar APB0 clock,
but has holes for gates to removed IP blocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sun6i
The Allwinner A31 and A23 SoCs have a reset controller
maintaining the UART in reset by default.
This patch adds optional reset support to the driver.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt | 1 +
drivers/tty/serial/8250
PLL6 on sun6i has multiple outputs, just like the other sunxi platforms.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm
The A23 is a dual Cortex-A7. Add the logic to use the IPs used to
control the CPU configuration and the CPU power so that we can
bring up secondary CPUs at boot.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/mach-sunxi/platsmp.c | 69 +++
1 file
sun6i/sun8i have a UART in the RTC block group, which can be used
as an early console. This is most useful on sun8i as UART0 is muxed
with MMC0, which is not available if we boot from MMC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/Kconfig.debug | 10 ++
1 file changed, 10
On Tue, May 27, 2014 at 4:30 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Mon, May 26, 2014 at 12:36:38PM +0800, Chen-Yu Tsai wrote:
On Mon, May 26, 2014 at 3:14 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:20PM +0800, Chen-Yu Tsai
Hi,
On Fri, May 23, 2014 at 9:09 PM, Emilio López emi...@elopez.com.ar wrote:
Hi,
El 23/05/14 04:51, Chen-Yu Tsai escribió:
The N factor for PLL6 counts from 1 to 32, as specified in the A23
manual, and shown in Allwinner's original code.
Are you sure about this? The A23 manual I'm
Hi,
On Mon, May 26, 2014 at 2:56 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:12PM +0800, Chen-Yu Tsai wrote:
Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e
On Mon, May 26, 2014 at 3:26 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:23PM +0800, Chen-Yu Tsai wrote:
The A23 is a dual Cortex-A7. Add the logic to use the IPs used to
control the CPU configuration and the CPU power so that we can
bring up
On Mon, May 26, 2014 at 3:38 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:24PM +0800, Chen-Yu Tsai wrote:
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch
On Mon, May 26, 2014 at 3:39 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:25PM +0800, Chen-Yu Tsai wrote:
The Ippo-q8h is a tablet circiut board commonly found in cheap Android
tablets with A23 SoCs. There are at least 2 versions of the board
On Mon, May 26, 2014 at 3:14 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:20PM +0800, Chen-Yu Tsai wrote:
The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
and the APB0
On Mon, May 26, 2014 at 2:48 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:06PM +0800, Chen-Yu Tsai wrote:
PLL6 is used by some important but undocumented module, most likely
memory related, such as mbus or the actual memory controller. As we
do
On Mon, May 26, 2014 at 2:46 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Fri, May 23, 2014 at 03:51:22PM +0800, Chen-Yu Tsai wrote:
sun6i/sun8i have a UART in the RTC block group, which can be used
as an early console. This is most useful on sun8i as UART0 is muxed
On Mon, May 26, 2014 at 2:51 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:07PM +0800, Chen-Yu Tsai wrote:
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the ahb_sdram clock, instead
of looking
On Wed, May 28, 2014 at 4:25 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, May 28, 2014 at 9:18 AM, Lee Jones lee.jo...@linaro.org wrote:
On Tue, 27 May 2014, Rob Herring wrote:
On Tue, May 27, 2014 at 3:23 PM, Kevin Hilman khil...@linaro.org wrote:
On Fri, May 23, 2014 at 1:03
On Thu, May 22, 2014 at 8:34 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
The Allwinner A31 DMA controller is rather simple to describe in the DT. Add
the bindings documentation.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
Hi,
On Wed, Apr 30, 2014 at 6:54 PM, Александр Берсенев b...@hackerdom.ru wrote:
[PATCH v4 01/03] ARM: sunxi: Add documentation for sunxi consumer infrared
devices
This patch adds documentation for Device-Tree bindings for sunxi IR
controller.
Signed-off-by: Alexander Bersenev
Hi,
On Sat, May 10, 2014 at 8:56 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were
having
a single clock for all the phys.
Hi,
On Mon, May 26, 2014 at 3:08 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, May 23, 2014 at 03:51:18PM +0800, Chen-Yu Tsai wrote:
The A23 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller
PLL1 on sun6i is a factor clock with the N multiplier factor starting
from 1. Set the .n_from_one field in the clock data to match.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b
The A23 has a R_PIO pin controller, similar to the one found on the A31 SoC.
Add support for the pins controlled by the R_PIO controller.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt
.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 57 +
2 files changed, 59 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
diff --git a/arch
The Allwinner A31 and A23 SoCs have a reset controller
maintaining the UART in reset by default.
This patch adds optional reset support to the driver.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt | 1 +
drivers/tty/serial/8250
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 536 +++
1 file changed, 536 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a23
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the ahb_sdram clock, instead
of looking for it and adding CLK_IGNORE_UNUSED inline in the
clock setup code.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 8 +++-
1
factor starts from 1 instead of 0.
This patch adds support for PLL1 and all the basic clock gates.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 5 +
drivers/clk/sunxi/clk-sunxi.c | 115 ++
2 files changed
factor in the clock driver, calculates the
rate for PLL6x2, and fixes the comment describing it.
A further patch (to the DT) should add a fixed-factor /2 clock as
the normally used PLL6 output.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
sun6i/sun8i have a UART in the RTC block group, which can be used
as an early console. This is most useful on sun8i as UART0 is muxed
with MMC0, which is not available if we boot from MMC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/Kconfig.debug | 10 ++
1 file changed, 10
for
the A23, allwinner,sun8i-a23-apb0-gates-clk.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b
The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.
This patch extends the sun6i-a31-apb0-clk driver to take divider
tables associated to compatibles, and adds a compatible for the A23
variant.
Signed-off-by: Chen-Yu Tsai
The new important clock protect code requires the clocks be
registered with clkdev. This was missing for sunxi_gates
type clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sunxi.c | 44 +++
2 files changed, 45 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b
The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/mach-sunxi/Kconfig | 8
arch/arm/mach-sunxi/sunxi.c | 10 ++
2 files changed, 18 insertions(+)
diff
The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
the APB0 clock has different divisors, and some clock gates are
gone.
This patch adds a compatible with a modified subdevice list for
the A23.
Signed-off-by: Chen-Yu
The PLL6 clock driver actually manages the PLL6x2 output of PLL6, so
rename the node accordingly, and add a halved fixed-factor-clock for
normal PLL6 output used by most modules.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 ++-
1 file changed, 10
A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.
This patch adds support for optional divider tables,
so the clock framework will know about the odd values.
Signed-off-by: Chen-Yu Tsai w
the maximum gate index + 1, so
of_clk_src_onecell_get does not complain about indices greater
than gates registered.
This was tested on the A23 SoC, which has a similar APB0 clock,
but has holes for gates to removed IP blocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sun6i
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.
This patch adds an option to the clock driver's config data structures
to define the difference.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free
clocks to A23 DTSI (patch 19)
- Added memory node to sun8i DTSI (patch 19)
- Added i2c2 to sun8i DTSI and DTS (patch 19)
There are a lot of changes. Hopefully I didn't miss any.
Thanks
ChenYu
Chen-Yu Tsai (20):
serial: 8250_dw: Add optional reset control support
clk: sunxi: register clock
The A23 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff
The CubieTruck uses the GMAC with an RGMII phy.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
U-Boot will insert MAC address into the device tree image.
It looks up ethernet[0-5] aliases to find the ethernet nodes.
Alias GMAC as ethernet0, as it is the only ethernet controller used.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
1 file changed, 1
The A20 has EMAC and GMAC muxed on the same pins.
Add pin sets with gmac function for MII and RGMII mode to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++--
1 file changed, 12 insertions(+), 15 deletions(-)
diff
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