On 2013/2/1 5:57, Kirill Tkhai wrote:
31.01.2013, 20:08, Steven Rostedt rost...@goodmis.org:
On Mon, 2013-01-28 at 03:46 +0400, Kirill Tkhai wrote:
The patch aims to decrease the number of calls of push_rt_task()
in push_rt_tasks().
It's not necessary to push more than
On 2013/2/5 15:22, Kirill Tkhai wrote:
Suppose we have a large number of cpus(say 4096), with the last one running
a low-priority task on it. Is it possible with this patch we will never reach
the last cpu in case that previous cpu has complete the pulled task?
Yes. But this patch is about
On Fri, 2016-05-27 at 16:56 +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang <honghui.zh...@mediatek.com>
>
Is there will be some comments for this version patchset?
Any comments is welcome.
Thanks.
> Mediatek's m4u(Multimedia Memory Management Unit) and SMI(Sma
On Tue, 2016-06-21 at 11:41 +0200, Joerg Roedel wrote:
> On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > Add the dtsi node of iommu and smi for mt2701.
> >
> > S
On Wed, 2016-06-22 at 10:31 +0200, Joerg Roedel wrote:
> On Wed, Jun 22, 2016 at 03:45:47PM +0800, Honghui Zhang wrote:
> > This one is based on CCF "arm: dts: mt2701: Add clock controller device
> > nodes"[1] and power domain patch "Mediatek MT2701 SCPSYS
On Wed, 2016-06-22 at 13:45 +0800, Eddie Huang wrote:
> On Tue, 2016-06-21 at 17:57 +0800, Joerg Roedel wrote:
> > On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zh...@mediatek.com wrote:
> > > From: Honghui Zhang <honghui.zh...@mediatek.com>
> > >
> &g
Hi, Robin,
Thanks very much for your comments.
On Mon, 2016-05-23 at 20:31 +0100, Robin Murphy wrote:
> On 19/05/16 12:49, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > Mediatek SoC's M4U has two generations of HW
Hi, Robin, Thanks very much for your comment, and sorry for the last
reply format.
On Tue, 2016-05-10 at 11:28 +0100, Robin Murphy wrote:
> On 09/05/16 09:00, honghui.zh...@mediatek.com wrote:
> [...]
> > +static void *mtk_iommu_alloc_pgt(struct device *dev, size_t size, gfp_t
> > gfp)
> > +{
>
On Tue, 2016-05-24 at 16:36 +0100, Robin Murphy wrote:
> On 24/05/16 10:57, Honghui Zhang wrote:
> [...]
> >>> @@ -48,6 +48,9 @@ struct mtk_iommu_domain {
> >>> struct io_pgtable_ops *iop;
> >>>
> >>>
On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
>
> On 07/03/2016 08:24 AM, Matthias Brugger wrote:
> >
> >
> > On 06/08/2016 11:51 AM, honghui.zh...@mediatek.com wrote:
> >> From: Honghui Zhang <honghui.zh...@mediatek.com>
> >>
&g
On Wed, 2016-11-16 at 11:38 -0800, Stephen Boyd wrote:
> On 11/16, Arnd Bergmann wrote:
> > After the MT2701 clock driver was added, we get a harmless warning for
> > the iommu driver that selects it, when compile-testing without
> > COMMON_CLK.
> >
> > warning: (MTK_IOMMU_V1) selects
On Thu, 2016-11-17 at 15:35 -0800, Stephen Boyd wrote:
> On 11/17, Honghui Zhang wrote:
> > On Wed, 2016-11-16 at 11:38 -0800, Stephen Boyd wrote:
> > > On 11/16, Arnd Bergmann wrote:
> > > > After the MT2701 clock driver was added, we get a harmless warnin
On Mon, 2016-10-31 at 10:08 +0800, James Liao wrote:
> On Mon, 2016-10-31 at 01:08 +0100, Matthias Brugger wrote:
> > Hi James,
> >
> > On 10/20/2016 10:56 AM, James Liao wrote:
> > > Some power domain comsumers may init before module_init.
> > > So the power domain provider (scpsys) need to be
On Fri, 2017-01-13 at 16:05 +0100, Matthias Brugger wrote:
> Hi Erin,
>
> I just took the patch from Honghui he send in june.
> Please see my comment inline.
>
> On 13/01/17 09:42, Erin Lo wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
>
On Fri, 2017-01-13 at 15:54 +0100, Matthias Brugger wrote:
>
> On 04/07/16 10:00, Matthias Brugger wrote:
> >
> >
> > On 04/07/16 03:32, Honghui Zhang wrote:
> >> On Sun, 2016-07-03 at 21:12 +0200, Matthias Brugger wrote:
> >>>
> &g
On Fri, 2017-07-28 at 10:59 +0100, Robin Murphy wrote:
> On 28/07/17 02:15, Honghui Zhang wrote:
> > On Thu, 2017-07-27 at 17:42 +0200, Matthias Brugger wrote:
> >>
> >> On 07/27/2017 04:01 AM, honghui.zh...@mediatek.com wrote:
> >>> From: Ho
On Wed, 2017-07-26 at 20:37 +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang <honghui.zh...@mediatek.com>
>
> Replace custom code with generic helper to retrieve driver data.
Hi, Joerg, would you please take this one, because my last
patch[1]([patch v2 0/3] Add larb
Hi, Bjorn,
Thanks very much for your reviews.
The mis-spells will be fixed in next version.
On Thu, 2017-08-03 at 17:42 -0500, Bjorn Helgaas wrote:
..
> > +}
> > +
> > +static struct mtk_pcie_port *mtk_pcie_find_port(struct mtk_pcie *pcie,
> > +
On Thu, 2017-08-10 at 10:27 +0800, Jun Gao wrote:
> From: Jun Gao
>
> Add MT7622 i2c binding to binding file. Compare to MT8173 i2c
> controller, MT7622 limits message numbers to 255, and does not
> support 4GB DMA mode.
>
> Signed-off-by: Jun Gao
>
On Fri, 2017-08-11 at 09:37 +0800, Jun Gao wrote:
> On Thu, 2017-08-10 at 16:19 +0800, Honghui Zhang wrote:
> > On Thu, 2017-08-10 at 10:27 +0800, Jun Gao wrote:
> > > From: Jun Gao <jun@mediatek.com>
> > >
> > > Add MT7622 i2c binding to binding fi
properities.
> >
> > Signed-off-by: Ryder Lee <ryder....@mediatek.com>
> > Signed-off-by: Honghui Zhang <honghui.zh...@mediatek.com>
> > ---
> > .../devicetree/bindings/pci/mediatek-pcie.txt | 84
> > --
> > 1 file c
On Thu, 2017-07-27 at 14:58 +0200, Joerg Roedel wrote:
> On Thu, Jul 27, 2017 at 10:01:09AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > Mediatek's gen1 smi need the hardware larbid to identify the offset for
>
On Thu, 2017-07-27 at 17:42 +0200, Matthias Brugger wrote:
>
> On 07/27/2017 04:01 AM, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt270
On Wed, 2017-07-26 at 11:36 +0100, Robin Murphy wrote:
> On 26/07/17 10:59, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > * for mtk smi gen 1, we need to get the ao(always on) base to config
> > * m4u por
> some SoC-dependent related setting. In doing so, the common code which
> will be reused by future chips.
>
> In addition, we change the approaches to waiting Gen2 training by using
> readl_poll_timeout() calls.
>
> Signed-off-by: Ryder Lee <ryder@mediatek.com>
>
On Thu, 2017-07-27 at 11:19 +0800, Honghui Zhang wrote:
> On Thu, 2017-07-27 at 10:58 +0800, honghui.zh...@mediatek.com wrote:
> > From: Ryder Lee <ryder@mediatek.com>
> >
> > Introduce a structure "mtk_pcie_soc" to abstract the differences between
> &g
On Thu, 2017-07-27 at 10:58 +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee <ryder@mediatek.com>
>
> Add support for MediaTek new generation controller and update related
> properities.
>
> Signed-off-by: Ryder Lee <ryder@mediatek.com>
On Thu, 2017-07-27 at 10:58 +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee <ryder@mediatek.com>
>
> Add support for MediaTek new generation controller and update related
> properities.
>
> Signed-off-by: Ryder Lee <ryder@mediatek.com>
g.
And please send this one to Joerg and iommu mail list.
otherwise:
Acked-by: Honghui Zhang <honghui.zh...@mediatek.com>
[1]https://lkml.org/lkml/2017/8/3/968
Thanks.
> drivers/memory/mtk-smi.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drive
On Tue, 2017-08-08 at 15:19 -0500, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 08:18:09AM -0500, Bjorn Helgaas wrote:
> > On Fri, Aug 04, 2017 at 04:39:36PM +0800, Honghui Zhang wrote:
> > > On Thu, 2017-08-03 at 17:42 -0500, Bjorn Helgaas wrote:
>
> > &
On Sun, 2017-08-06 at 10:06 +0800, Ryder Lee wrote:
> Hi Honghui,
>
> If you plan to send next version, then I would suggest some minor
> changes.
>
> On Fri, 2017-08-04 at 20:06 +0800, honghui.zh...@mediatek.com wrote:
> > +#define PCIE_CRSTB BIT(3)
> > +#define PCIE_PERSTB
On Sat, 2017-08-05 at 14:16 +0800, Ryder Lee wrote:
> On Sat, 2017-08-05 at 12:52 +0800, Ryder Lee wrote:
> > Hi Honghui, Bjorn,
> >
> > On Fri, 2017-08-04 at 08:18 -0500, Bjorn Helgaas wrote:
> > > On Fri, Aug 04, 2017 at 04:39:36PM +0800, Honghui Zhang wrote:
>
On Wed, 2017-08-30 at 09:19 +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang <honghui.zh...@mediatek.com>
>
> Switch from using a custom NUM_INTX macro to the generic PCI_NUM_INTX
> definition for the number of INTx interrupts.
>
> Signed-off-by: H
On Fri, 2018-06-01 at 13:52 +0300, Andy Shevchenko wrote:
> On Fri, Jun 1, 2018 at 1:49 PM, Honghui Zhang
> wrote:
> > On Fri, 2018-06-01 at 13:17 +0300, Andy Shevchenko wrote:
> >> On Fri, Jun 1, 2018 at 6:04 AM, wrote:
> >> > From: Honghui Zhang
&g
On Thu, 2018-05-31 at 10:05 +0800, Ryder Lee wrote:
> On Wed, 2018-05-30 at 10:35 +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all
> > the internel control register
On Wed, 2018-05-30 at 23:20 -0500, Bjorn Helgaas wrote:
> On Wed, May 30, 2018 at 10:35:36AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all
> > the internel control r
On Fri, 2018-06-01 at 13:17 +0300, Andy Shevchenko wrote:
> On Fri, Jun 1, 2018 at 6:04 AM, wrote:
> > From: Honghui Zhang
>
> > +#ifdef CONFIG_PM_SLEEP
> > +static int mtk_pcie_suspend_noirq(struct device *dev)
>
> __maybe_unused
>
Hi, Andy, thanks for your
On Wed, 2018-06-27 at 19:35 +0300, Andy Shevchenko wrote:
> On Wed, Jun 27, 2018 at 12:21 PM, wrote:
> > From: Honghui Zhang
> >
> > Mediatek's host controller have two slots, each have it's own control
> > registers. The host driver need to identify which slot
On Wed, 2018-06-27 at 19:39 +0300, Andy Shevchenko wrote:
> On Wed, Jun 27, 2018 at 12:21 PM, wrote:
> > From: Honghui Zhang
> >
> > Implement remove callback function for Mediatek PCIe driver to add
> > loadable kernel module support.
>
> > +static void m
On Wed, 2018-06-27 at 19:45 +0300, Andy Shevchenko wrote:
> On Wed, Jun 27, 2018 at 12:21 PM, wrote:
> > From: Honghui Zhang
> >
> > The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system
> > suspend, and all the internal control register will be re
On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote:
> Hi Zhang,
>
> On 20/04/18 06:25, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > Using irq_chip solution to setup IRQs for the consistent with IRQ framework
On Wed, 2018-05-02 at 11:09 +0100, Marc Zyngier wrote:
> On 02/05/18 10:41, Honghui Zhang wrote:
> > On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote:
> >> Hi Zhang,
> >>
> >> On 20/04/18 06:25, honghui.zh...@mediatek.com wrote:
> >>>
On Thu, 2018-05-03 at 14:05 +0100, Marc Zyngier wrote:
> On 03/05/18 10:41, Honghui Zhang wrote:
> > On Wed, 2018-05-02 at 11:09 +0100, Marc Zyngier wrote:
> >> On 02/05/18 10:41, Honghui Zhang wrote:
> >>> On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote:
> &
On Thu, 2017-12-21 at 18:27 -0600, Bjorn Helgaas wrote:
> On Thu, Dec 21, 2017 at 03:01:12PM +0800, Honghui Zhang wrote:
> > On Thu, 2017-12-21 at 14:41 +0800, Yong Wu wrote:
> > > On Thu, 2017-12-21 at 10:11 +0800, honghui.zh...@mediatek.com wrote:
> > > > F
On Thu, 2018-01-04 at 19:04 +, Marc Zyngier wrote:
> On 04/01/18 18:40, Lorenzo Pieralisi wrote:
> > [+Marc]
> >
> > On Wed, Dec 27, 2017 at 08:59:53AM +0800, honghui.zh...@mediatek.com wrote:
> >> From: Honghui Zhang <honghui.zh...@mediatek.com>
>
On Mon, 2017-12-25 at 18:27 +0800, Ryder Lee wrote:
> On Fri, 2017-12-22 at 13:39 +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > The hardware default value of IDs and class type is not correct,
> > fix that b
On Tue, 2018-01-02 at 10:56 +, Lorenzo Pieralisi wrote:
> On Thu, Dec 28, 2017 at 09:39:12AM +0800, Honghui Zhang wrote:
> > On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote:
> > > On Wed, Dec 27, 2017 at 08:59:54AM +0800, honghui.zh...@mediatek.com
> > > w
On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote:
> On Wed, Dec 27, 2017 at 08:59:54AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > The hardware default value of IDs and class type is not correct,
> &
On Thu, 2017-12-21 at 14:41 +0800, Yong Wu wrote:
> On Thu, 2017-12-21 at 10:11 +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > The host bridge of MT7622 has hardware code the class code to an
> >
+0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zh...@mediatek.com>
> >
> > There maybe a same irq reentry scenario after irq received in current
> > irq handle flow:
> > EP device PCIe host driverEP driver
> &g
On Thu, 2017-12-21 at 10:08 +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang <honghui.zh...@mediatek.com>
>
> Two fixups for mediatek's host bridge:
> The first patch fixup the IRQ handle routine to avoid IRQ reentry which
> may exist for both MT2712 and MT762
On Tue, 2018-07-17 at 18:15 +0100, Lorenzo Pieralisi wrote:
> [+Rafael, Kevin, Ulf]
>
> On Mon, Jul 02, 2018 at 03:57:43PM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when
Hi, Bjorn, Lorenzo,
could you kindly take a look at this serial?
thanks.
On Mon, 2018-07-02 at 15:57 +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> This patchset includes misc patchs:
>
> The first patch fixup the mtk_pcie_find_port logical which will cause
gt; Signed-off-by: Gustavo A. R. Silva
> ---
> drivers/pci/controller/pcie-mediatek.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Hi, Gustavo, thanks for your help.
Acked-by: Honghui Zhang
> diff --git a/drivers/pci/controller/pcie-mediatek.c
> b/drivers/pci/co
On Wed, 2018-07-18 at 10:49 +0100, Lorenzo Pieralisi wrote:
> On Wed, Jul 18, 2018 at 02:02:41PM +0800, Honghui Zhang wrote:
>
>
>
> > > > +static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
> > > > +{
> > > > +
On Thu, 2018-06-28 at 08:07 -0500, Bjorn Helgaas wrote:
> On Wed, Jun 27, 2018 at 05:21:35PM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > Mediatek's host controller have two slots, each have it's own control
> > registers. The host driver
On Tue, 2018-10-02 at 11:59 +0100, Lorenzo Pieralisi wrote:
> On Mon, Oct 01, 2018 at 03:36:41PM +0100, Lorenzo Pieralisi wrote:
> > On Fri, Sep 28, 2018 at 06:04:32PM +0800, honghui.zh...@mediatek.com wrote:
> > > From: Honghui Zhang
> > >
> > > The Medi
On Mon, 2018-10-15 at 14:05 +0800, Ryder Lee wrote:
> On Mon, 2018-10-15 at 13:44 +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > This patchset includes misc patchs:
> >
> > The patch 1 fixup the mtk_pcie_find_port logic which will
On Fri, 2018-10-12 at 11:22 +0100, Lorenzo Pieralisi wrote:
> On Fri, Oct 12, 2018 at 04:01:29PM +0800, Honghui Zhang wrote:
> > On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote:
> > > On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote:
> > > &g
On Fri, 2018-10-12 at 09:12 -0500, Bjorn Helgaas wrote:
> On Fri, Oct 12, 2018 at 11:22:30AM +0100, Lorenzo Pieralisi wrote:
> > On Fri, Oct 12, 2018 at 04:01:29PM +0800, Honghui Zhang wrote:
> >> On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote:
> >>> On T
On Wed, 2018-10-17 at 08:22 -0500, Bjorn Helgaas wrote:
> On Tue, Oct 16, 2018 at 03:53:55PM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Oct 16, 2018 at 06:44:43PM +0800, honghui.zh...@mediatek.com wrote:
> > > From: Honghui Zhang
> > >
> > > The PCI con
On Wed, 2018-10-17 at 16:19 +0100, Lorenzo Pieralisi wrote:
> On Mon, Oct 15, 2018 at 04:08:51PM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > This patchset includes misc patchs:
> >
> > The patch 1 fixup the mtk_pcie_find_port logic
On Thu, 2018-10-11 at 12:38 +0100, Lorenzo Pieralisi wrote:
> On Tue, Oct 09, 2018 at 11:08:15AM +0800, Honghui Zhang wrote:
> > On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote:
> > > On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com
> &g
On Fri, 2018-11-02 at 14:36 +0800, Ryder Lee wrote:
> On Thu, 2018-10-18 at 11:23 +0800, Honghui Zhang (张洪辉) wrote:
> > From: Honghui Zhang
> >
> > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> > DT parser.
> >
On Wed, 2018-11-07 at 12:03 +, Lorenzo Pieralisi wrote:
> On Thu, Oct 18, 2018 at 11:23:34AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> > DT parser.
>
On Mon, 2018-10-08 at 12:31 -0500, Bjorn Helgaas wrote:
> On Mon, Oct 08, 2018 at 11:24:39AM +0800, honghui.zh...@mediatek.com wrote:
>
> > Honghui Zhang (9):
> > PCI: mediatek: Using slot's devfn for compare to fix
> > mtk_pcie_find_port logic
> > PCI: media
On Mon, 2018-10-08 at 18:23 +0100, Lorenzo Pieralisi wrote:
> On Mon, Oct 08, 2018 at 11:24:41AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The PCIe controller of MT7622 has TYPE 1 configuration space type, but
> > the HW default c
On Fri, 2018-09-28 at 23:41 +0800, Ryder Lee wrote:
> On Fri, 2018-09-28 at 18:04 +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > Part of mtk_pcie_register_host is an open-coded version of
> > pci_host_probe(). So instead of duplicating this c
On Fri, 2018-09-21 at 17:07 +0100, Lorenzo Pieralisi wrote:
> On Mon, Sep 10, 2018 at 05:50:20PM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The Mediatek's host controller has two slots, each with it's own control
> > registers. The host dr
On Fri, 2018-09-21 at 17:46 +0100, Lorenzo Pieralisi wrote:
> On Mon, Sep 10, 2018 at 05:50:21PM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The clocks was not enabled when enable MSI. This patch fix this
> > issue by
On Thu, 2018-11-29 at 11:33 +, Lorenzo Pieralisi wrote:
> On Thu, Nov 08, 2018 at 10:56:55AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > Use the devm_of_pci_get_host_bridge_resources() API in place of the PCI OF
> > DT parser.
>
On Thu, 2018-12-06 at 09:09 +0800, Jianjun Wang wrote:
> MT7629 is an arm platform SoC which has the same PCIe IP with MT7622.
>
> The read value of BAR0 is 0x_, it's size will be calculated as 4GB
> in arm64 but bogus alignment values at arm32, the pcie device and devices
:s /the pcie
On 2013/2/1 5:57, Kirill Tkhai wrote:
>
>
> 31.01.2013, 20:08, "Steven Rostedt" :
>> On Mon, 2013-01-28 at 03:46 +0400, Kirill Tkhai wrote:
>>
>>> The patch aims to decrease the number of calls of push_rt_task()
>>> in push_rt_tasks().
>>>
>>> It's not necessary to push more than
On 2013/2/5 15:22, Kirill Tkhai wrote:
>>
>> Suppose we have a large number of cpus(say 4096), with the last one running
>> a low-priority task on it. Is it possible with this patch we will never reach
>> the last cpu in case that previous cpu has complete the pulled task?
>
> Yes. But this patch
On Thu, 2018-05-03 at 14:05 +0100, Marc Zyngier wrote:
> On 03/05/18 10:41, Honghui Zhang wrote:
> > On Wed, 2018-05-02 at 11:09 +0100, Marc Zyngier wrote:
> >> On 02/05/18 10:41, Honghui Zhang wrote:
> >>> On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote:
> &
On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote:
> Hi Zhang,
>
> On 20/04/18 06:25, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > Using irq_chip solution to setup IRQs for the consistent with IRQ framework.
> >
> > Signed-off-
On Wed, 2018-05-02 at 11:09 +0100, Marc Zyngier wrote:
> On 02/05/18 10:41, Honghui Zhang wrote:
> > On Mon, 2018-04-30 at 12:03 +0100, Marc Zyngier wrote:
> >> Hi Zhang,
> >>
> >> On 20/04/18 06:25, honghui.zh...@mediatek.com wrote:
> >>> From: Ho
On Wed, 2017-08-30 at 09:19 +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Switch from using a custom NUM_INTX macro to the generic PCI_NUM_INTX
> definition for the number of INTx interrupts.
>
> Signed-off-by: Honghui Zhang
> ---
> drivers/pci/
igned-off-by: Ryder Lee
> > Signed-off-by: Honghui Zhang
> > ---
> > .../devicetree/bindings/pci/mediatek-pcie.txt | 84
> > --
> > 1 file changed, 79 insertions(+), 5 deletions(-)
> >
> > diff --git a/Documentation/devic
+0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > There maybe a same irq reentry scenario after irq received in current
> > irq handle flow:
> > EP device PCIe host driverEP driver
> > 1. issue an ir
On Thu, 2017-12-21 at 10:08 +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Two fixups for mediatek's host bridge:
> The first patch fixup the IRQ handle routine to avoid IRQ reentry which
> may exist for both MT2712 and MT7622.
> The second patch fixup cla
On Thu, 2017-12-21 at 14:41 +0800, Yong Wu wrote:
> On Thu, 2017-12-21 at 10:11 +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The host bridge of MT7622 has hardware code the class code to an
> > arbitrary, meaningless value, fix that.
>
On Thu, 2018-01-04 at 19:04 +, Marc Zyngier wrote:
> On 04/01/18 18:40, Lorenzo Pieralisi wrote:
> > [+Marc]
> >
> > On Wed, Dec 27, 2017 at 08:59:53AM +0800, honghui.zh...@mediatek.com wrote:
> >> From: Honghui Zhang
> >>
> >> There mayb
On Thu, 2017-12-21 at 18:27 -0600, Bjorn Helgaas wrote:
> On Thu, Dec 21, 2017 at 03:01:12PM +0800, Honghui Zhang wrote:
> > On Thu, 2017-12-21 at 14:41 +0800, Yong Wu wrote:
> > > On Thu, 2017-12-21 at 10:11 +0800, honghui.zh...@mediatek.com wrote:
> >
On Mon, 2017-12-25 at 18:27 +0800, Ryder Lee wrote:
> On Fri, 2017-12-22 at 13:39 +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The hardware default value of IDs and class type is not correct,
> > fix that by setup the correct values befor
On Wed, 2017-12-27 at 12:45 -0600, Bjorn Helgaas wrote:
> On Wed, Dec 27, 2017 at 08:59:54AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The hardware default value of IDs and class type is not correct,
> > fix that by setup the cor
On Fri, 2017-08-11 at 09:37 +0800, Jun Gao wrote:
> On Thu, 2017-08-10 at 16:19 +0800, Honghui Zhang wrote:
> > On Thu, 2017-08-10 at 10:27 +0800, Jun Gao wrote:
> > > From: Jun Gao
> > >
> > > Add MT7622 i2c binding to binding file. Compare to MT8173 i2c
>
Hi, Bjorn,
Thanks very much for your reviews.
The mis-spells will be fixed in next version.
On Thu, 2017-08-03 at 17:42 -0500, Bjorn Helgaas wrote:
..
> > +}
> > +
> > +static struct mtk_pcie_port *mtk_pcie_find_port(struct mtk_pcie *pcie,
> > +
On Sat, 2017-08-05 at 14:16 +0800, Ryder Lee wrote:
> On Sat, 2017-08-05 at 12:52 +0800, Ryder Lee wrote:
> > Hi Honghui, Bjorn,
> >
> > On Fri, 2017-08-04 at 08:18 -0500, Bjorn Helgaas wrote:
> > > On Fri, Aug 04, 2017 at 04:39:36PM +0800, Honghui Zhang wrote:
>
On Sun, 2017-08-06 at 10:06 +0800, Ryder Lee wrote:
> Hi Honghui,
>
> If you plan to send next version, then I would suggest some minor
> changes.
>
> On Fri, 2017-08-04 at 20:06 +0800, honghui.zh...@mediatek.com wrote:
> > +#define PCIE_CRSTB BIT(3)
> > +#define PCIE_PERSTB
rg and iommu mail list.
otherwise:
Acked-by: Honghui Zhang
[1]https://lkml.org/lkml/2017/8/3/968
Thanks.
> drivers/memory/mtk-smi.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> in
On Tue, 2017-08-08 at 15:19 -0500, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 08:18:09AM -0500, Bjorn Helgaas wrote:
> > On Fri, Aug 04, 2017 at 04:39:36PM +0800, Honghui Zhang wrote:
> > > On Thu, 2017-08-03 at 17:42 -0500, Bjorn Helgaas wrote:
>
> > &
On Thu, 2017-08-10 at 10:27 +0800, Jun Gao wrote:
> From: Jun Gao
>
> Add MT7622 i2c binding to binding file. Compare to MT8173 i2c
> controller, MT7622 limits message numbers to 255, and does not
> support 4GB DMA mode.
>
> Signed-off-by: Jun Gao
> ---
>
On Wed, 2017-07-26 at 20:37 +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Replace custom code with generic helper to retrieve driver data.
Hi, Joerg, would you please take this one, because my last
patch[1]([patch v2 0/3] Add larbid init routine for mediatek's gen1
On Wed, 2017-07-26 at 11:36 +0100, Robin Murphy wrote:
> On 26/07/17 10:59, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > * for mtk smi gen 1, we need to get the ao(always on) base to config
> > * m4u port, and we need to enable the aync
ated setting. In doing so, the common code which
> will be reused by future chips.
>
> In addition, we change the approaches to waiting Gen2 training by using
> readl_poll_timeout() calls.
>
> Signed-off-by: Ryder Lee
> Signed-off-by: Honghui Zhang
On Thu, 2017-07-27 at 11:19 +0800, Honghui Zhang wrote:
> On Thu, 2017-07-27 at 10:58 +0800, honghui.zh...@mediatek.com wrote:
> > From: Ryder Lee
> >
> > Introduce a structure "mtk_pcie_soc" to abstract the differences between
> > controller generat
On Thu, 2017-07-27 at 10:58 +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> Add support for MediaTek new generation controller and update related
> properities.
>
> Signed-off-by: Ryder Lee
> Signed-off-by: Honghui Zhang
> ---
> .../devicetree/bin
On Thu, 2017-07-27 at 10:58 +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> Add support for MediaTek new generation controller and update related
> properities.
>
> Signed-off-by: Ryder Lee
> Signed-off-by: Honghui Zhang
> ---
> .../devicetree/bin
On Thu, 2017-07-27 at 14:58 +0200, Joerg Roedel wrote:
> On Thu, Jul 27, 2017 at 10:01:09AM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > Mediatek's gen1 smi need the hardware larbid to identify the offset for
> > the register which co
1 - 100 of 155 matches
Mail list logo