magic numbers, and could not be revealed. These magic numbers are
received from Realtek via Pine64.
Signed-off-by: Icenowy Zheng
---
drivers/net/phy/realtek.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 677c45985338
Some of the Pine64+ boards are known to use a batch of broken RTL8211E
PHYs. A magic number that is in an undocumented field of a register is
passed from Realtek via Pine64.
Add the property to apply the hack to the Pine64+ device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts
From: Icenowy Zheng
Some RTL8211E Ethernet PHY have an issue that needs a workaround, and a
way to indicate the need of the workaround should be added.
Add the binding for a DT property that indicates this workaround.
Signed-off-by: Icenowy Zheng
---
.../bindings/net/realtek,rtl8211e.yaml
There're some Pine64+ boards known to have broken RTL8211E chips, and
a hack is given by Pine64+, which is said to be from Realtek.
This patchset adds the hack.
The hack is taken from U-Boot, and it contains magic numbers without
any document.
Icenowy Zheng (3):
dt-bindings: add binding
在 2019-08-20二的 15:58 +0200，Maxime Ripard写道：
> On Fri, Aug 16, 2019 at 04:00:16PM +0200, Corentin Labbe wrote:
> > On Fri, Aug 16, 2019 at 03:52:06PM +0200, Maxime Ripard wrote:
> > > On Fri, Aug 16, 2019 at 01:57:50PM +0200, Corentin Labbe wrote:
> > > > On Fri, Aug 16, 2019 at 01:36:50PM +0200,
board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Added missing compatible string.
- Set default USB role to "peripheral".
- Switch to use V3 DTSI.
No changes in v4.
Changes in v3:
- Drop common regulator DTSI usage and added vcc3v3
tree binding (the header file name).
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Fix MMC2 clock slices.
Changes in v4:
- Add the missing MMC2 clock slices.
No changes in v3/v2.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 228 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
) as the file's name.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Dropped dedicated S3/S3L DTSIs.
No changes until v5.
arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi
diff --git a/arch/arm/boot/dts/sun8i
The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.
Fix this issue.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Fix typo on hw_clk reference.
Patch introduced in v4.
d
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.
Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
---
No changes in v5.
Changes in v4:
- Removed bogus alignment change.
Changes in v3:
- Fixed code alignment.
- Fixed LVDS function number
SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng
Reviewed-by: Rob Herring
---
Changes in v5:
- Added V3 compatible to S3 board.
- Fixed S3 compatible string.
No changes until v5
the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (6):
pinctrl: sunxi: v3s: introduce support for V3
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
clk: sunxi-ng: v3s
在 2019-07-23 03:29，Maxime Ripard 写道：
On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote:
于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard
写到:
>On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
>> The Lichee Zero Plus is a core board made by Sipeed, with a
于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
>> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
>> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI
>Flash.
>&
于 2019年7月20日 GMT+08:00 下午5:48:14, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote:
>> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
>> but with more GPIO wired out of the package.
>>
>> Add DTSI files for these
于 2019年7月20日 GMT+08:00 下午5:44:49, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote:
>> The MMC2 clock slices are currently not defined in V3s CCU driver,
>which
>> makes MMC2 not working.
>>
>> Fix this issue.
>>
>>
SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng
---
No changes since v3.
Patch introduced in v2.
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5
board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng
---
No changes in v4.
Changes in v3:
- Drop common regulator DTSI usage and added vcc3v3 regulator.
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/sun8i-s3-lichee-zero-plus.dts| 8
: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Icenowy Zheng
+ */
+
+#include "sun8i-v3.dtsi"
diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi
new file mode 100644
index ..0f41a25ecb30
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-s3l.dtsi
@@
tree binding (the header file name).
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Add the missing MMC2 clock slices.
No changes in v3/v2.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 228 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
include/dt-bindings/clock/sun8i
The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
when developing the V3s CCU driver.
Add back the missing PLL_DDR1.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
No changes since v1.
drivers/clk/sunxi-ng/ccu-s
The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.
Fix this issue.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
New patch in v4.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
1 file
Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
is only available on V3, and thus the clocks is not declared for V3s
CCU.
Add a V3 CCU compatible string to the binding to prepare for a CCU
driver that provide I2S clock on V3, but not on V3s.
Signed-off-by: Icenowy Zheng
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Removed bogus alignment change.
Changes in v3:
- Fixed code alignment.
- Fixed LVDS function number.
Changes in v2:
- Dropped the driver rename patch
the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (8):
pinctrl: sunxi: v3s: introduce support for V3
clk: sunxi-ng: v3s: add the missing PLL_DDR1
dt-bindings: clk: sunxi-ccu: add compatible
于 2019年6月24日 GMT+08:00 下午8:43:01, Maxime Ripard 写到:
>On Sun, Jun 23, 2019 at 12:38:01PM +0800, Icenowy Zheng wrote:
>> Lichee zero plus is a core board made by Sipeed, which includes
>on-board
>> TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug
>>
board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Drop common regulator DTSI usage and added vcc3v3 regulator.
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/sun8i-s3-lichee-zero-plus.dts| 8
.../dts/sun8i-s3-s3l
Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
is only available on V3, and thus the clocks is not declared for V3s
CCU.
Add a V3 CCU compatible string to the binding to prepare for a CCU
driver that provide I2S clock on V3, but not on V3s.
Signed-off-by: Icenowy Zheng
: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Icenowy Zheng
+ */
+
+#include "sun8i-v3.dtsi"
diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi
new file mode 100644
index ..0f41a25ecb30
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-s3l.dtsi
@@
Shenzhen SoChip Technology Co., Ltd. is a hardware vendor that produces
EVBs with Allwinner chips. There's also a SoC named S3 that is developed
by Allwinner (based on Allwinner V3/V3s) but branded SoChip.
Add the vendor prefix for SoChip.
Signed-off-by: Icenowy Zheng
Reviewed-by: Rob Herring
tree binding (the header file name).
Signed-off-by: Icenowy Zheng
---
No changes in v3/v2.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 225 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
include/dt-bindings/reset/sun8i
SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng
---
No changes in v3.
Patch introduced in v2.
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5
Shenzhen Sipeed Technology Co., Ltd. is a company focused on development
kits, which also contains rebranded Lichee Pi series.
Add its vendor prefix binding.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Rebased because of the addition of sinlinx and sinovoip.
Patch introduced in v2
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Fixed code alignment.
- Fixed LVDS function number.
Changes in v2:
- Dropped the driver rename patch and apply the changes directly on V3s
driver
The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
when developing the V3s CCU driver.
Add back the missing PLL_DDR1.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
No changes in v3/v2.
drivers/clk/sunxi-ng/ccu-s
the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (9):
pinctrl: sunxi: v3s: introduce support for V3
clk: sunxi-ng: v3s: add the missing PLL_DDR1
dt-bindings: clk: sunxi-ccu: add compatible
Shenzhen SoChip Technology Co., Ltd. is a hardware vendor that produces
EVBs with Allwinner chips. There's also a SoC named S3 that is developed
by Allwinner (based on Allwinner V3/V3s) but branded SoChip.
Add the vendor prefix for SoChip.
Signed-off-by: Icenowy Zheng
Reviewed-by: Rob Herring
SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng
---
New patch in v2.
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git
Shenzhen Sipeed Technology Co., Ltd. is a company focused on development
kits, which also contains rebranded Lichee Pi series.
Add its vendor prefix binding.
Signed-off-by: Icenowy Zheng
---
New patch in v2.
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2
-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Icenowy Zheng
+ */
+
+#include "sun8i-v3.dtsi"
diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi
new file mode 100644
index ..0f41a25ecb30
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-s3l.dtsi
@@ -0,0 +1,6 @
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the driver rename patch and apply the changes directly on V3s
driver.
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 265
The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
when developing the V3s CCU driver.
Add back the missing PLL_DDR1.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
No changes in v2.
drivers/clk/sunxi-ng/ccu-sun8i-
The Allwinner V3 SoC, despite come with the same die with V3s, has more
GPIO pins than V3s, and a different compatible string for pinctrl is
needed.
Add the compatible string for V3 pinctrl.
Signed-off-by: Icenowy Zheng
Reviewed-by: Rob Herring
---
Changes in v2:
- Add the review tag by Rob
board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng
---
New patch in v2.
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/sun8i-s3-lichee-zero-plus.dts| 8
.../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi| 39 +++
3 files
Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
is only available on V3, and thus the clocks is not declared for V3s
CCU.
Add a V3 CCU compatible string to the binding to prepare for a CCU
driver that provide I2S clock on V3, but not on V3s.
Signed-off-by: Icenowy Zheng
tree binding (the header file name).
Signed-off-by: Icenowy Zheng
---
No changes in v2.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 225 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
include/dt-bindings/reset/sun8i-v3s
The pinctrl driver of V3s is already available and used in the kernel,
but the compatible string of it is forgotten to be added.
Add the missing compatible string.
Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
---
Changes in v2:
- Add the ACK tag by Maxime
the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (11):
dt-bindings: pinctrl: add missing compatible string for V3s
dt-bindings: pinctrl: add compatible string for Allwinner V3 pinctrl
在 2019-05-06一的 14:28 +0200，Maxime Ripard写道：
> Hi,
>
> On Sun, May 05, 2019 at 04:22:15PM +0100, Jonathan Cameron wrote:
> > On Fri, 3 May 2019 03:28:07 -0400
> > Yangtao Li wrote:
> >
> > > For some SOCs, there are more than one thermal sensor, and there
> > > are
> > > currently four sensors
The Allwinner H6 SoC features tweakable VCC for PC, PD, PG, PL and PM
banks.
This patch adds supplies for these banks except PL bank. PL bank is
where PMIC is attached, and currently if a PMIC regulator is added
for it a dependency loop will happen.
Signed-off-by: Icenowy Zheng
---
Changes
The Allwinner V3/V3s/S3L/SoChip S3 Ethernet MAC and internal PHY is quite
similar to the ones on Allwinner H3, except for V3s the external MII is
not wired out.
Add ethernet support to V3/V3s/S3/S3L.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3.dtsi | 13
arch/arm/boot
initialization code is not
shared because the acquisition of GPIO configuration in OTP ROM is
similar to CP2105, not CP2102N.
Signed-off-by: Icenowy Zheng
---
drivers/usb/serial/cp210x.c | 82 +++--
1 file changed, 78 insertions(+), 4 deletions(-)
diff --git a/drivers/usb
The SMI SM3350 USB-UFS bridge controller cannot handle long sense request
correctly and will make the chip refuse to do read/write when requested
long sense.
Add a bad sense quirk for it.
Signed-off-by: Icenowy Zheng
---
drivers/usb/storage/unusual_devs.h | 12
1 file changed, 12
US_FL_BAD_SENSE for SM3350 fail
(as it claims SPC4).
Fix this conflicting quirk issue, and add the quirk for SM3350.
Icenowy Zheng (2):
USB: storage: don't insert sane sense for SPC3+ when bad sense
specified
USB: storage: add quirk for SMI SM3350
drivers/usb/storage/scsiglue.c | 8
state that cannot read/write anything).
Check the presence of US_FL_BAD_SENSE when assuming US_FL_SANE_SENSE on
SPC4+ devices.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Changed the comment to note the check.
drivers/usb/storage/scsiglue.c | 8 ++--
1 file changed, 6 insertions
在 2018-12-27四的 22:34 +0800，Icenowy Zheng写道：
> The SMI SM3350 USB-UFS bridge controller cannot handle long sense
> request
> correctly and will make the chip refuse to do read/write when
> requested
> long sense.
>
> Add a bad sense quirk for it.
>
> Signed-off-by: Ice
在 2018-12-27四的 22:34 +0800，Icenowy Zheng写道：
> Currently the code will set US_FL_SANE_SENSE flag unconditionally if
> device claims SPC3+, however we should allow US_FL_BAD_SENSE flag to
> prevent this behavior, because SMI SM3350 UFS-USB bridge controller,
> which claims SPC4, will
state that cannot read/write anything).
Check the presence of US_FL_BAD_SENSE when assuming US_FL_SANE_SENSE on
SPC4+ devices.
Signed-off-by: Icenowy Zheng
---
drivers/usb/storage/scsiglue.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/storage/scsiglue.c b
The SMI SM3350 USB-UFS bridge controller cannot handle long sense request
correctly and will make the chip refuse to do read/write when requested
long sense.
Add a bad sense quirk for it.
Signed-off-by: Icenowy Zheng
---
drivers/usb/storage/unusual_devs.h | 12
1 file changed, 12
US_FL_BAD_SENSE for SM3350 fail
(as it claims SPC4).
Fix this conflicting quirk issue, and add the quirk for SM3350.
Icenowy Zheng (2):
USB: storage: don't insert sane sense for SPC3+ when bad sense
specified
USB: storage: add quirk for SMI SM3350
drivers/usb/storage/scsiglue.c | 3
nodes")
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 45bbb5116446..d1ed451f4d9e 100644
nodes")
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 45bbb5116446..d1ed451f4d9e 100644
于 2018年11月13日 GMT+08:00 下午1:50:45, Sasha Levin 写到:
>From: Icenowy Zheng
>
>[ Upstream commit c2ff8383cc33c2d9c169e4daf1e37a434c3bb420 ]
>
>On the H6, the MMC module clocks are fixed in the new timing mode,
>i.e. they do not have a bit to select the mode. These clocks
于 2018年11月13日 GMT+08:00 下午1:50:45, Sasha Levin 写到:
>From: Icenowy Zheng
>
>[ Upstream commit c2ff8383cc33c2d9c169e4daf1e37a434c3bb420 ]
>
>On the H6, the MMC module clocks are fixed in the new timing mode,
>i.e. they do not have a bit to select the mode. These clocks
-by: Icenowy Zheng
---
Changes for v4:
- none
Changes for v3.1:
- Refactor commit log to make it more clear.
Changes for v3:
- collect Rob r-w-b tag
Changes for v2:
- Add fallback compatible
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
-by: Icenowy Zheng
---
Changes for v4:
- none
Changes for v3.1:
- Refactor commit log to make it more clear.
Changes for v3:
- collect Rob r-w-b tag
Changes for v2:
- Add fallback compatible
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rename the supply name to "hvcc".
Changes in v3.1:
- New patch. (Replaced "drm: sun4i: add support for HVCC regulator
for DWC HDMI glue" by Icenowy.)
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 17 -
drivers/gpu/drm/su
From: Jagan Teki
Enable all necessary device tree nodes and add connector node to device
trees for all supported A64 boards with HDMI.
Signed-off-by: Jagan Teki
[Icenowy: squash all board patches altogether and change supply name]
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rebase some
Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC"
pin, which is the VCC of HDMI part.
Add a supply property to specify HVCC's regulator in the device tree.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rename the supply name to "hvcc".
Changes
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rename the supply name to "hvcc".
Changes in v3.1:
- New patch. (Replaced "drm: sun4i: add support for HVCC regulator
for DWC HDMI glue" by Icenowy.)
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 17 -
drivers/gpu/drm/su
From: Jagan Teki
Enable all necessary device tree nodes and add connector node to device
trees for all supported A64 boards with HDMI.
Signed-off-by: Jagan Teki
[Icenowy: squash all board patches altogether and change supply name]
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rebase some
Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC"
pin, which is the VCC of HDMI part.
Add a supply property to specify HVCC's regulator in the device tree.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rename the supply name to "hvcc".
Changes
From: Jagan Teki
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Dropped PLL_VIDEO1
and the TCON1 HDMI one.
Signed-off-by: Jagan Teki
[Icenowy: refactor commit message and add 1st pipeline]
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Misc fixes
- Dropped second PLL from HDMI PHY clock
Changes for v3.1:
- Refactor commit message to make it more clear.
- Added first pipeline
From: Jagan Teki
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Dropped PLL_VIDEO1
and the TCON1 HDMI one.
Signed-off-by: Jagan Teki
[Icenowy: refactor commit message and add 1st pipeline]
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Misc fixes
- Dropped second PLL from HDMI PHY clock
Changes for v3.1:
- Refactor commit message to make it more clear.
- Added first pipeline
From: Jagan Teki
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
From: Jagan Teki
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Add support for them.
Signed-off-by: Jagan Teki
[Icenowy: Add mixer1]
Signed-off-by: Icenowy Zheng
Reviewed-by: Jernej Skrabec
---
Changes for v4:
- none
Changes for v3.1:
- Add mixer0
Changes for v3
From: Jagan Teki
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
From: Jagan Teki
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Add support for them.
Signed-off-by: Jagan Teki
[Icenowy: Add mixer1]
Signed-off-by: Icenowy Zheng
Reviewed-by: Jernej Skrabec
---
Changes for v4:
- none
Changes for v3.1:
- Add mixer0
Changes for v3
From: Jagan Teki
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
: Refactor and also cover TCON1]
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- none
Changes for v3.1:
- added mixer0 and TCON0
Changes for v3:
- collect Rob r-w-b tag
Changes for v2:
- Add fallback compatible for tcon1
- Add separate compatible for mixer1
.../devicetree/bindings/display/sunxi
for
other SoCs, so more faith is put in BSP clock driver.
Signed-off-by: Icenowy Zheng
---
New patch in v4.
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 50 ++-
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk
From: Jagan Teki
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
: Refactor and also cover TCON1]
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- none
Changes for v3.1:
- added mixer0 and TCON0
Changes for v3:
- collect Rob r-w-b tag
Changes for v2:
- Add fallback compatible for tcon1
- Add separate compatible for mixer1
.../devicetree/bindings/display/sunxi
for
other SoCs, so more faith is put in BSP clock driver.
Signed-off-by: Icenowy Zheng
---
New patch in v4.
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 50 ++-
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk
two display pipelines, and enables
the HDMI output on several boards. The first pipeline is not enabled in
this patchset yet, although it's added.
Icenowy Zheng (2):
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
dt-bindings: sun4i-drm: add HDMI VCC supply property for sun8i-dw
two display pipelines, and enables
the HDMI output on several boards. The first pipeline is not enabled in
this patchset yet, although it's added.
Icenowy Zheng (2):
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
dt-bindings: sun4i-drm: add HDMI VCC supply property for sun8i-dw
在 2017-09-26二的 09:22 +0200，Corentin Labbe写道：
> The unit address and register address does not match.
> This patch fix the register address with the good one.
>
> Acked-by: Maxime Ripard
> Signed-off-by: Corentin Labbe
This patch should be backported.
Older LTS also needs patches, but the
在 2017-09-26二的 09:22 +0200，Corentin Labbe写道：
> The unit address and register address does not match.
> This patch fix the register address with the good one.
>
> Acked-by: Maxime Ripard
> Signed-off-by: Corentin Labbe
This patch should be backported.
Older LTS also needs patches, but the
于 2018年7月25日 GMT+08:00 下午11:31:26, Rob Herring 写到:
>On Sun, Jul 22, 2018 at 02:10:33PM +0800, Chen-Yu Tsai wrote:
>> On Sun, Jul 22, 2018 at 1:57 PM, Icenowy Zheng
>wrote:
>> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
>> > external USB3
于 2018年7月25日 GMT+08:00 下午11:31:26, Rob Herring 写到:
>On Sun, Jul 22, 2018 at 02:10:33PM +0800, Chen-Yu Tsai wrote:
>> On Sun, Jul 22, 2018 at 1:57 PM, Icenowy Zheng
>wrote:
>> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
>> > external USB3
于 2018年7月25日 GMT+08:00 下午8:19:47, Maxime Ripard 写到:
>On Tue, Jul 24, 2018 at 10:42:32PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年7月24日 GMT+08:00 下午10:41:51, Maxime Ripard
> 写到:
>> >On Tue, Jul 24, 2018 at 10:37:51AM +0800, Chen-Yu Tsai wrote:
>&
于 2018年7月25日 GMT+08:00 下午8:19:47, Maxime Ripard 写到:
>On Tue, Jul 24, 2018 at 10:42:32PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年7月24日 GMT+08:00 下午10:41:51, Maxime Ripard
> 写到:
>> >On Tue, Jul 24, 2018 at 10:37:51AM +0800, Chen-Yu Tsai wrote:
>&
dw_hdmi_setup when setting mode, in order to prevent such
situation.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index
dw_hdmi_setup when setting mode, in order to prevent such
situation.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index
于 2018年7月12日 GMT+08:00 下午2:46:01, Maxime Ripard 写到:
>On Wed, Jul 11, 2018 at 11:15:50PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年7月11日 GMT+08:00 下午11:05:32, Maxime Ripard
> 写到:
>> >Hi,
>> >
>> >On Wed, Jul 11, 2018 at 09:22:32PM +0800,
于 2018年7月12日 GMT+08:00 下午2:46:01, Maxime Ripard 写到:
>On Wed, Jul 11, 2018 at 11:15:50PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年7月11日 GMT+08:00 下午11:05:32, Maxime Ripard
> 写到:
>> >Hi,
>> >
>> >On Wed, Jul 11, 2018 at 09:22:32PM +0800,
在 2018-07-09一的 10:01 +0530，'Kishon Vijay Abraham I' via linux-sunxi写道：
> Hi,
>
> On Friday 06 July 2018 09:08 PM, Icenowy Zheng wrote:
> > Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> > controlled).
> >
> > Add a driver for it.
在 2018-07-09一的 10:01 +0530，'Kishon Vijay Abraham I' via linux-sunxi写道：
> Hi,
>
> On Friday 06 July 2018 09:08 PM, Icenowy Zheng wrote:
> > Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> > controlled).
> >
> > Add a driver for it.
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