As DE2 support for more SoCs are introducing, there's many reports that
the DE2 is not functional due to DE2 CCU code not included in kernel.
Defaultly enable DE2 CCU for sun8i/sun50i to reduce this kind of
problems.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/clk/su
As DE2 support for more SoCs are introducing, there's many reports that
the DE2 is not functional due to DE2 CCU code not included in kernel.
Defaultly enable DE2 CCU for sun8i/sun50i to reduce this kind of
problems.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/Kconfig | 2 ++
1 file
于 2018年1月7日 GMT+08:00 上午6:12:57, Hans de Goede <hdego...@redhat.com> 写到:
>Hi,
>
>On 05-01-18 17:56, Icenowy Zheng wrote:
>> The UAS mode of Norelsys NS1068(X) is reported to fail to work on
>> several platforms with the following error message:
>>
>> x
于 2018年1月7日 GMT+08:00 上午6:12:57, Hans de Goede 写到:
>Hi,
>
>On 05-01-18 17:56, Icenowy Zheng wrote:
>> The UAS mode of Norelsys NS1068(X) is reported to fail to work on
>> several platforms with the following error message:
>>
>> xhci-hcd xhci-hcd.0.auto: ERROR
and "Expansion" pin header
- 2 USB 2.0 ports and 1 USB 3.0 ports
- Audio jack
- MicroSD slot and eMMC module slot
- on-board SPI NOR flash
- 1Gbps Ethernet port (via RTL8211E PHY)
- HDMI port
Adds initial support for it, including the UART on the Expansion pin
header.
Signed-off-by:
and "Expansion" pin header
- 2 USB 2.0 ports and 1 USB 3.0 ports
- Audio jack
- MicroSD slot and eMMC module slot
- on-board SPI NOR flash
- 1Gbps Ethernet port (via RTL8211E PHY)
- HDMI port
Adds initial support for it, including the UART on the Expansion pin
header.
Signed-off-by: Icenowy Z
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.
This commit adds the basical DTSI file of it, including the clock
support and UART support.
Signed-off-by: Icenowy Zheng <icen...@aosc
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.
This commit adds the basical DTSI file of it, including the clock
support and UART support.
Signed-off-by: Icenowy Zheng
---
arch/arm64
The Allwinner H6 SoC has a CCU which has been largely rearranged.
Add support for it in the sunxi-ng CCU framework.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
.../devicetree/bindings/clock/sunxi-ccu.txt|1 +
drivers/clk/sunxi-ng/Kconfig
The Allwinner H6 SoC has a CCU which has been largely rearranged.
Add support for it in the sunxi-ng CCU framework.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-ccu.txt|1 +
drivers/clk/sunxi-ng/Kconfig |5 +
drivers/clk/sunxi-ng
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.
Add fixed post divider support to the NKMP style clocks.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/clk/sunxi-ng/ccu_nkmp.
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.
Add fixed post divider support to the NKMP style clocks.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu_nkmp.c | 20 +---
drivers/clk/sunxi-ng
t.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 4 +-
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.
t.
Signed-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 4 +-
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 679
to hardware IRQ bank map, so
the new situation in H6 main pin controller can be processed. The old
special situation which uses a constant offset (on A33 and V3s, both
with a offset of 1) can be also processed with the new code.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl
to hardware IRQ bank map, so
the new situation in H6 main pin controller can be processed. The old
special situation which uses a constant offset (on A33 and V3s, both
with a offset of 1) can be also processed with the new code.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
The Allwinner H6 pin controllers (both the main one and the CPUs one)
have no bus gate clocks.
Add support for this kind of pin controllers.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 --
drivers/pinctrl
The Allwinner H6 pin controllers (both the main one and the CPUs one)
have no bus gate clocks.
Add support for this kind of pin controllers.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 --
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1
).
This patchset adds the most basical support for it, including the main pin
controller, the main CCU and the basical device tree.
Icenowy Zheng (7):
pinctrl: sunxi: add support for pin controllers without bus gate
pinctrl: sunxi: support pin controllers with holes among IRQ banks
pinctrl
).
This patchset adds the most basical support for it, including the main pin
controller, the main CCU and the basical device tree.
Icenowy Zheng (7):
pinctrl: sunxi: add support for pin controllers without bus gate
pinctrl: sunxi: support pin controllers with holes among IRQ banks
pinctrl
-by: Icenowy Zheng <icen...@aosc.io>
---
The NS1066 chip from the same vendor seems to also suffer from this
problem (its USB ID is 2537:1066) according to the report of Armbian
community. However I don't have such device (I have a USB HDD enclosure
with USB ID 2537:1066, but it doesn't repo
-by: Icenowy Zheng
---
The NS1066 chip from the same vendor seems to also suffer from this
problem (its USB ID is 2537:1066) according to the report of Armbian
community. However I don't have such device (I have a USB HDD enclosure
with USB ID 2537:1066, but it doesn't report UAS function at all
于 2018年1月4日 GMT+08:00 上午5:32:26, "Jernej Škrabec" 写到:
>Hi Rob,
>
>Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > This commit adds all necessary compatibles and descriptions
于 2018年1月4日 GMT+08:00 上午5:32:26, "Jernej Škrabec" 写到:
>Hi Rob,
>
>Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > This commit adds all necessary compatibles and descriptions needed
>to
>> > implement
于 2018年1月5日 GMT+08:00 上午2:52:10, Maxime Ripard
写到:
>On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej Škrabec wrote:
>> Hi Rob,
>>
>> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej
于 2018年1月5日 GMT+08:00 上午2:52:10, Maxime Ripard
写到:
>On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej Škrabec wrote:
>> Hi Rob,
>>
>> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > > This commit
Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
When resending, the ACK's by Maxime
Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
Add support for it.
Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Acked-by: Rob Herring
---
When resending, the ACK's by Maxime and Rob are added.
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1
在 2018年1月2日星期二 CST 下午4:11:04,Chen-Yu Tsai 写道:
> On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng <icen...@aosc.io> wrote:
> > The H3/H5 SoCs have a HDMI output and a TV Composite output.
> >
> > Add simplefb nodes for these outputs.
> >
> > Signed
在 2018年1月2日星期二 CST 下午4:11:04,Chen-Yu Tsai 写道:
> On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng wrote:
> > The H3/H5 SoCs have a HDMI output and a TV Composite output.
> >
> > Add simplefb nodes for these outputs.
> >
> > Signed-off-by: Icenowy Zheng
> &g
e Ripard wrote:
> >>> On Sun, Oct 08, 2017 at 04:29:01AM +, Icenowy Zheng wrote:
> >>>> Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
> >>>>
> >>>> Add support for it.
> >>>>
> >>>
e Ripard wrote:
> >>> On Sun, Oct 08, 2017 at 04:29:01AM +, Icenowy Zheng wrote:
> >>>> Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
> >>>>
> >>>> Add support for it.
> >>>>
> >>>> Sig
device node.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
New patch introduced in v4.
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 4
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
device node.
Signed-off-by: Icenowy Zheng
---
New patch introduced in v4.
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 4
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts| 4
arch/arm64
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.
Adds the device tree nodes for the SRAM controller and the DE2 CCU.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Fixed the alliwnner,sram property (the 1
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.
Adds the device tree nodes for the SRAM controller and the DE2 CCU.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Fixed the alliwnner,sram property (the 1 after SRAM phadle
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for these pipelines on A64 SoC.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Dropped extra clocks.
- Added labels to the SimpleFB device tree
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for these pipelines on A64 SoC.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Dropped extra clocks.
- Added labels to the SimpleFB device tree nodes as boards may have
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Use a struct to maintain both ccu desc and quirks as Chen-Yu Tsai
suggested.
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Use a struct to maintain both ccu desc and quirks as Chen-Yu Tsai
suggested.
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 117
<r...@kernel.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Added Rob's ACK.
Changes in v2:
- Adds description of the situation when the SRAM is not claimed.
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Added Rob's ACK.
Changes in v2:
- Adds description of the situation when the SRAM is not claimed.
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings
for HVCC pin (a power supply pin on A64 SoC that is used by the HDMI
controller) on these boards.
Icenowy Zheng (6):
ARM: sunxi: h3/h5: add simplefb nodes
dt-bindings: add binding for A64 DE2 CCU SRAM
clk: sunxi-ng: add support for Allwinner A64 DE2 CCU
arm64: allwinner: a64: add DE2 CCU for A64
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the
clocks that are needed to display frame
for HVCC pin (a power supply pin on A64 SoC that is used by the HDMI
controller) on these boards.
Icenowy Zheng (6):
ARM: sunxi: h3/h5: add simplefb nodes
dt-bindings: add binding for A64 DE2 CCU SRAM
clk: sunxi-ng: add support for Allwinner A64 DE2 CCU
arm64: allwinner: a64: add DE2 CCU for A64
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the
clocks that are needed to display framebuffer to the monitor.
arch/arm
于 2017年12月29日 GMT+08:00 下午4:55:34, Chen-Yu Tsai <w...@csie.org> 写到:
>On Thu, Dec 28, 2017 at 10:05 PM, Icenowy Zheng <icen...@aosc.io>
>wrote:
>> Orange Pi R1 uses a Realtek RTL8152B USB Ethernet chip, which is
>easily
>> seen on the board but not sh
于 2017年12月29日 GMT+08:00 下午4:55:34, Chen-Yu Tsai 写到:
>On Thu, Dec 28, 2017 at 10:05 PM, Icenowy Zheng
>wrote:
>> Orange Pi R1 uses a Realtek RTL8152B USB Ethernet chip, which is
>easily
>> seen on the board but not show in the schematics. A regulator for the
>>
to the device tree, and bind it to USB1.
Tested-by: Hauke Mehrtens <ha...@hauke-m.de>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orange
to the device tree, and bind it to USB1.
Tested-by: Hauke Mehrtens
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
b/arch/arm/boot/dts/sun8i-h2-plus
rk.kette...@xs4all.nl>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 295e48fc94bc.
When merging A20 pinctrl support to A10 pinctrl driver, the I2C function
of PI3 is wrongly written as "i2c3" (it should be "i2c4").
Fix this typo.
Fixes: cad4e209c102 ("pinctrl: sunxi: add support of R40 to A10 pinctrl driver")
Reported-by: Mark Kettenis
在 2017年12月27日星期三 CST 下午12:09:41,Chen-Yu Tsai 写道:
> On Fri, Dec 22, 2017 at 8:22 PM, Icenowy Zheng <icen...@aosc.io> wrote:
> > This patchset adds support for the SimpleFB on Allwinner SoCs with
> > "Display Engine 2.0".
> >
> > PATCH 1 to PATCH 3 are DE2
在 2017年12月27日星期三 CST 下午12:09:41,Chen-Yu Tsai 写道:
> On Fri, Dec 22, 2017 at 8:22 PM, Icenowy Zheng wrote:
> > This patchset adds support for the SimpleFB on Allwinner SoCs with
> > "Display Engine 2.0".
> >
> > PATCH 1 to PATCH 3 are DE2 CCU fixes
在 2017年12月24日星期日 CST 下午4:02:08,Priit Laes 写道:
> On Sun, Dec 24, 2017 at 01:40:29PM +0800, Icenowy Zheng wrote:
> > Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form
> > factor and GPIO holes similar to Raspberry Pi Zero.
> >
> > It featur
在 2017年12月24日星期日 CST 下午4:02:08,Priit Laes 写道:
> On Sun, Dec 24, 2017 at 01:40:29PM +0800, Icenowy Zheng wrote:
> > Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form
> > factor and GPIO holes similar to Raspberry Pi Zero.
> >
> > It featur
to power the board and
the other features OTG functionality)
- Two keys, a reset and a GPIO-connected key.
- HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+.
- CSI connector to connect the camera sensor provided by Sinovoip.
Signed-off-by: Icenowy Zheng <icen...@aosc
to power the board and
the other features OTG functionality)
- Two keys, a reset and a GPIO-connected key.
- HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+.
- CSI connector to connect the camera sensor provided by Sinovoip.
Signed-off-by: Icenowy Zheng
---
Changes in v3
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for these pipelines on A64 SoC.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 31 +++
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for these pipelines on A64 SoC.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 31 +++
1 file changed, 31 insertions
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.
Adds the device tree nodes for the SRAM controller and the DE2 CCU.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Fixed the alliwnner,sram property (the 1
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.
Adds the device tree nodes for the SRAM controller and the DE2 CCU.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Fixed the alliwnner,sram property (the 1 after SRAM phadle
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drive
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i
<r...@kernel.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Add Rob's ACK.
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
b/Documentatio
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Add Rob's ACK.
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/su
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
Signed-off-by: Icenowy Zheng <i
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
Signed-off-by: Icenowy Zheng
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.
Add the compatible string of H5 DE2 CCU in H5 DTSI file.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.
Add the compatible string of H5 DE2 CCU in H5 DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4
1
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 2db5d4e00ea7..468d1abaf0ee 100644
--- a/drivers/
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 2db5d4e00ea7..468d1abaf0ee 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-d
As we're going to add simplefb support for Allwinner SoCs with DE2, add
suitable pipeline strings in the device tree binding.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Adds Rob's ACK.
.../devicetree/bindings/di
As we're going to add simplefb support for Allwinner SoCs with DE2, add
suitable pipeline strings in the device tree binding.
Acked-by: Rob Herring
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Adds Rob's ACK.
.../devicetree/bindings/display/simple-framebuffer-sunxi.txt | 4
Allwinner H3 features a DE2 CCU like the one on A83T, however the
parent of the clocks is the DE module clock, not the PLL_DE clock.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 47
Allwinner H3 features a DE2 CCU like the one on A83T, however the
parent of the clocks is the DE module clock, not the PLL_DE clock.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 47
1 file changed, 47
the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).
Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
1
the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).
Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
1 file changed, 3 insert
CH 8 to 11 are for Allwinner A64 SoC to enable SimpleFB.
Icenowy Zheng (11):
dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
dt-bindings: simplefb-sunxi: add pipelin
CH 8 to 11 are for Allwinner A64 SoC to enable SimpleFB.
Icenowy Zheng (11):
dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
dt-bindings: simplefb-sunxi: add pipelin
As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-li
As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
b/arch/arm
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/ar
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi
As the PHY dual-route property is added to 4.15-rc, the EHCI/OHCI nodes
are now necessary.
Please apply these patches to 4.15, Thanks!
Icenowy Zheng (2):
ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
arch/arm/boot/dts/sun8i-v3s-licheepi
As the PHY dual-route property is added to 4.15-rc, the EHCI/OHCI nodes
are now necessary.
Please apply these patches to 4.15, Thanks!
Icenowy Zheng (2):
ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
arch/arm/boot/dts/sun8i-v3s-licheepi
在 2017-11-28 04:57,Jernej Skrabec 写道:
Base addresses of channel output CSC (CCSC) depends whether mixer in
question is first or second and if it is second, if supports VEP or
not.
This new property will tell which set of base addresses to take.
0 - first mixer or second mixer with VEP support
在 2017-11-28 04:57,Jernej Skrabec 写道:
Base addresses of channel output CSC (CCSC) depends whether mixer in
question is first or second and if it is second, if supports VEP or
not.
This new property will tell which set of base addresses to take.
0 - first mixer or second mixer with VEP support
在 2017-11-28 17:02,Maxime Ripard 写道:
Hi,
On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard
napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by:
在 2017-11-28 17:02,Maxime Ripard 写道:
Hi,
On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard
napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
>
-off-by: Icenowy Zheng <icen...@aosc.io>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 525 +
4 files
to power the board and
the other features OTG functionality)
- Two keys, a reset and a GPIO-connected key.
- HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+.
- CSI connector to connect the camera sensor provided by Sinovoip.
Signed-off-by: Icenowy Zheng <icen...@aosc
to power the board and
the other features OTG functionality)
- Two keys, a reset and a GPIO-connected key.
- HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+.
- CSI connector to connect the camera sensor provided by Sinovoip.
Signed-off-by: Icenowy Zheng
---
Changes in v2
Orange Pi R1 is a board design based on Orange Pi Zero, with XR819 Wi-Fi
chip replaced by RTL8189ETV Wi-Fi module and the USB Type-A jack
replaced by an onboard USB RTL8152B USB-Ethernet adapter.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/Ma
Orange Pi R1 is a board design based on Orange Pi Zero, with XR819 Wi-Fi
chip replaced by RTL8189ETV Wi-Fi module and the USB Type-A jack
replaced by an onboard USB RTL8152B USB-Ethernet adapter.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile
On several A64 boards the Ethernet PHY is powered by the DC1SW regulator
on the AXP803 PMIC.
Add phy-handle property to these boards' emac node.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1 +
arch/arm64/boot/dts/all
On several A64 boards the Ethernet PHY is powered by the DC1SW regulator
on the AXP803 PMIC.
Add phy-handle property to these boards' emac node.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1 +
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64
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