/write requires 2 interrupts plus
one interrupt per transferred byte. Since the interrupts are costly using
the HLC improves the performance. Also, the HLC provides improved error
handling.
Signed-off-by: David Daney <dda...@caviumnetworks.com>
Signed-off-by: Jan Glauber <jglau...@cavium.co
easure ~5.2kB/s, about 1/2 what's
achievable, and much better than the worst-case 100 bytes/sec before.
Signed-off-by: Peter Swain <psw...@cavium.com>
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Acked-by: David Daney <dda...@caviumnetworks.com>
---
drivers/i2c/
On Wed, Mar 23, 2016 at 09:32:15PM +0100, Wolfram Sang wrote:
> On Fri, Mar 18, 2016 at 09:46:30AM +0100, Jan Glauber wrote:
> > From: David Daney <david.da...@cavium.com>
> >
> > Use High Level Controller when possible.
>
> Can you give me a one line descrip
Convert the adapter timeout to 2 ms independently of depending on CONFIG_HZ.
CONFIG_HZ is 100 for MIPS Cavium-Octeon so the timeout value is not changed.
Also set retries to 5 to improve robustness.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon.c | 3
No functional change, just moving the functions upward in
preparation of improving the recovery.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon.c | 126
1 file changed, 63 insertions(+), 63 deletions(-)
diff
From: Peter Swain <psw...@cavium.com>
Consider more status codes and improve error handling.
Distinguish handling for first and last part of a message.
TODO: Convert to use the i2c recovery framework.
Signed-off-by: Peter Swain <psw...@cavium.com>
Signed-off-by: Jan Glauber <jgla
Add compatible string for Cavium Octeon cn78XX SOCs TWSI.
Cc: Rob Herring <robh...@kernel.org>
Cc: Pawel Moll <pawel.m...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Ian Campbell <ijc+devicet...@hellion.org.uk>
Cc: Kumar Gala <ga...@codeaurora.org>
Sig
From: David Daney <david.da...@cavium.com>
cn78xx has a different interrupt architecture, so we have to manage
the interrupts differently.
Signed-off-by: David Daney <dda...@caviumnetworks.com>
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/
From: Peter Swain <psw...@cavium.com>
Signed-off-by: Peter Swain <psw...@cavium.com>
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Acked-by: David Daney <dda...@caviumnetworks.com>
---
drivers/i2c/busses/i2c-octeon.c | 19 ---
1 file changed, 12 in
Just sorting the functions to be consistent with the other
read/write variants.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon.c | 94 -
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/i2c/
From: David Daney <david.da...@cavium.com>
CN3860 does not interrupt the CPU when the i2c status changes. If
we get a timeout, and see the status has in fact changed, we know we
have this problem, and drop back to polling.
Signed-off-by: David Daney <dda...@caviumnetworks.com>
Signed
: octeon: Add support for cn78xx chips
i2c: octeon: Add workaround for broken irqs on CN3860
Jan Glauber (8):
i2c: octeon: Increase retry default and use fixed timeout value
i2c: octeon: Move set-clock and init-lowlevel upward
dt-bindings: i2c: Add Octeon cn78xx TWSI
i2c: octeon: Move read
On Wed, Apr 13, 2016 at 10:44:09AM +0200, Wolfram Sang wrote:
> On Mon, Apr 11, 2016 at 05:28:34PM +0200, Jan Glauber wrote:
> > octeon_i2c_read_sw -> octeon_i2c_reg_read
> > octeon_i2c_write_sw -> octeon_i2c_reg_write
> >
> > Signed-off-by: Jan Glauber <
Add compatible string for Cavium Octeon cn78XX SOCs TWSI.
Cc: Rob Herring <robh...@kernel.org>
Cc: Pawel Moll <pawel.m...@arm.com>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Ian Campbell <ijc+devicet...@hellion.org.uk>
Cc: Kumar Gala <ga...@codeaurora.org>
Sig
Add smbus alert interrupt support.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-cavium.h| 6 ++
drivers/i2c/busses/i2c-thunderx-core.c | 35 ++
2 files changed, 41 insertions(+)
diff --git a/drivers/i2c/buss
The ThunderX SOC uses the same i2c block as the Octeon SOC.
The main difference is that on ThunderX the device is a PCI device
so device probing is done via PCI, interrupts are MSIX and the
clock is taken from device tree.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/
wrong in this case).
EEPROM reads on 100kHz i2c now measure ~5.2kB/s, about 1/2 what's
achievable, and much better than the worst-case 100 bytes/sec before.
While at it remove the debug print from the low-level wait function.
Signed-off-by: Peter Swain <psw...@cavium.com>
Signed-off-by: Jan Gl
The register offsets are different between Octeon and ThunderX so move
them into the algorithm struct and get rid of the define.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-cavium.c| 28 +--
drivers/i2c/busses/i2c-ca
l read/write requires 2 interrupts
plus one interrupt per transferred byte. Since the interrupts are costly
using the HLC improves the performance. Also, the HLC provides improved
error handling.
Signed-off-by: David Daney <dda...@caviumnetworks.com>
Signed-off-by: Jan Glauber <jgla
: Add workaround for broken irqs on CN3860
Jan Glauber (10):
i2c: octeon: Improve error status checking
i2c: octeon: Use i2c recovery framework
i2c: octeon: Remove I2C_FUNC_SMBUS_QUICK support
dt-bindings: i2c: Add Octeon cn78xx TWSI
i2c: octeon: Move read function before write
i2c
er receive mode until the last byte is
requested. The state check needs to consider if this bit was set.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon.c | 129 +---
1 file changed, 106 insertions(+), 23 deletions(-)
diff
the
xfer debug message (i2c core already provides a debug message
for this).
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon.c | 160
1 file changed, 97 insertions(+), 63 deletions(-)
diff --git a/drivers/i2c/buss
From: Peter Swain <psw...@cavium.com>
Add helper function that reads back a value after writing to
make sure the write is finished and use it in octeon_i2c_write_int().
Signed-off-by: Peter Swain <psw...@cavium.com>
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
driv
Move common functionality into a separate file in preparation of the
re-use from the ThunderX i2c driver.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/Makefile | 3 +-
drivers/i2c/busses/i2c-cavium.c | 799 +
drive
This is an intermediate commit in preparation of the driver split.
The module rename in this commit will be reverted in the next patch,
this is just done to make the series bisectible.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/Makefile
Just sorting the functions to be consistent with the other
read/write variants.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon.c | 78 -
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/i2c/
From: David Daney <david.da...@cavium.com>
CN3860 does not interrupt the CPU when the i2c status changes. If
we get a timeout, and see the status has in fact changed, we know we
have this problem, and drop back to polling.
Signed-off-by: David Daney <dda...@caviumnetworks.com>
Signed
From: David Daney <david.da...@cavium.com>
cn78xx has a different interrupt architecture, so we have to manage
the interrupts differently.
Signed-off-by: David Daney <dda...@caviumnetworks.com>
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/
SMBUS QUICK never worked for the read case, because EINVAL was returned
for a zero length message. The hardware does not support SMBUS QUICK
messages so disable the support and remove the zero length check.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon
On Thu, Apr 21, 2016 at 03:54:50PM +0200, Wolfram Sang wrote:
>
> > I assumed this check was bogus and there are no valid 0-length
> > messages...
>
> They are valid (check SMBUS_QUICK), but not every controller can handle
> them correctly. Your driver has SMBUS_QUICK enabled, so this is a
>
On Mon, Apr 25, 2016 at 02:19:07PM +0100, Will Deacon wrote:
> On Mon, Apr 25, 2016 at 02:02:22PM +0200, Jan Glauber wrote:
> > On Mon, Apr 25, 2016 at 12:22:07PM +0100, Will Deacon wrote:
> > > On Mon, Apr 04, 2016 at 02:19:54PM +0200, Jan Glauber wrote:
> >
On Tue, Apr 26, 2016 at 09:36:20AM +0200, Wolfram Sang wrote:
>
> > > Yes, I thought briefly about splitting SMBUS_QUICK into read-write
> > > variants too. To me the question is if this feature is still used on
> > > modern
> > > devices or if this is more a relict of the past. I don't know
-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index 9f11e19..e8a65f5 100644
--- a/drivers/i2c/busses/i2c-octeon.c
On Tue, Apr 26, 2016 at 02:53:54PM +0100, Will Deacon wrote:
[...]
> >
> > That sounds like a good compromise.
> >
> > So I could do the following:
> >
> > 1) In the uncore setup check for CONFIG_NUMA, if set use the NUMA
> >information to determine the device node
> >
> > 2) If
From: David Daney <david.da...@cavium.com>
CN3860 does not interrupt the CPU when the i2c status changes. If
we get a timeout, and see the status has in fact changed, we know we
have this problem, and drop back to polling.
Signed-off-by: David Daney <dda...@caviumnetworks.com>
Signed
On Tue, Apr 26, 2016 at 11:17:59PM +0200, Wolfram Sang wrote:
> On Mon, Apr 25, 2016 at 04:33:38PM +0200, Jan Glauber wrote:
> > From: David Daney <david.da...@cavium.com>
> >
> > CN3860 does not interrupt the CPU when the i2c status changes. If
> > we get
On Mon, Apr 25, 2016 at 11:44:29PM +0200, Wolfram Sang wrote:
> On Mon, Apr 25, 2016 at 04:33:34PM +0200, Jan Glauber wrote:
> > From: David Daney <dda...@caviumnetworks.com>
> >
> > Use High-Level Controller (HLC) when possible. The HLC can read/write
> > up to 8
On Tue, Apr 26, 2016 at 12:16:22AM +0200, Wolfram Sang wrote:
> On Mon, Apr 25, 2016 at 04:33:32PM +0200, Jan Glauber wrote:
> > SMBUS QUICK never worked for the read case, because EINVAL was returned
> > for a zero length message. The hardware does not support SMBUS QUICK
> >
On Tue, Apr 26, 2016 at 07:58:45AM +0200, Jan Glauber wrote:
> On Tue, Apr 26, 2016 at 12:16:22AM +0200, Wolfram Sang wrote:
> > On Mon, Apr 25, 2016 at 04:33:32PM +0200, Jan Glauber wrote:
> > > SMBUS QUICK never worked for the read case, because EINVAL was returned
>
Hi Will,
On Mon, Apr 25, 2016 at 12:22:07PM +0100, Will Deacon wrote:
> Hi Jan,
>
> On Mon, Apr 04, 2016 at 02:19:54PM +0200, Jan Glauber wrote:
> > Hi Mark,
> >
> > can you have a look at these patches?
>
> Looks like Mark reviewed this last week -- are you p
Hi Wolfram,
we want to add ACPI support to the ThunderX i2c driver
because it is meant for servers and some distributions
require ACPI there. The changes are small but I'll post
a new version of the remaining patches shortly.
Thanks,
Jan
On Mon, May 02, 2016 at 07:35:40PM +0200, Jan Glauber
Sort include files alphabetically to reduce probability of merge
conflicts.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon-core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/busses/i2c-octeon-core.c
b/drive
The register offsets are different between Octeon and ThunderX so move
them into the algorithm struct and get rid of the define.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-cavium.c| 28 +--
drivers/i2c/busses/i2c-ca
The i2c Octeon and ThunderX drivers are maintained by Cavium.
While at it fix the whitespace errors of the next entry.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Acked-by: David Daney <david.da...@cavium.com>
---
MAINTAINERS | 25 +
1 file changed, 1
Add SMBUS alert interrupt support. For now only device tree is
supported for specifying the alert. In case of ACPI an error
is returned.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-cavium.h| 6
drivers/i2c/busses/i2c-thunderx-core.
Move common functionality into a separate file in preparation of the
re-use from the ThunderX i2c driver.
Functions are slightly re-ordered but no other changes are included.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/Makefile | 3 +-
drivers/i2c/
driver on MIPS
- Re-ordered some thunderx probe functions for readability
- Fix missing of_irq.h and i2c-smbus.h includes
- Use IS_ENABLED for CONFIG options
Thanks,
Jan
-
Jan Glauber (8):
i2c: octeon: Rename driver to prepare for split
i2c
The ThunderX SOC uses the same i2c block as the Octeon SOC.
The main difference is that on ThunderX the device is a PCI device
so device probing is done via PCI, interrupts are MSI-X. The
clock rates can be set via device tree or ACPI.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
d
Initialize booleon values with true instead of 1.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-cavium.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-cavium.c b/drivers/i2c/busses/i2c-cavium.c
index e95ee5c..1
This is an intermediate commit in preparation of the driver split.
The module rename in this commit will be reverted in the next patch,
this is just done to make the series bisectible.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/Makefile
The register offsets are different between Octeon and ThunderX so move
them into the algorithm struct and get rid of the define.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-cavium.c| 28 +--
drivers/i2c/busses/i2c-ca
Sort include files alphabetically to reduce probability of merge
conflicts.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon-core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/busses/i2c-octeon-core.c
b/drive
Move common functionality into a separate file in preparation of the
re-use from the ThunderX i2c driver.
Functions are slightly re-ordered but no other changes are included.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/Makefile | 3 +-
drivers/i2c/
The i2c Octeon and ThunderX drivers are maintained by Cavium.
While at it fix the whitespace errors of the next entry.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Acked-by: David Daney <david.da...@cavium.com>
---
MAINTAINERS | 25 +
1 file changed, 1
The ThunderX SOC uses the same i2c block as the Octeon SOC.
The main difference is that on ThunderX the device is a PCI device
so device probing is done via PCI, interrupts are MSIX and the
clock is taken from device tree.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/
Initialize booleon values with true instead of 1.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-cavium.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-cavium.c b/drivers/i2c/busses/i2c-cavium.c
index e95ee5c..1
Add smbus alert interrupt support.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-cavium.h| 6 ++
drivers/i2c/busses/i2c-thunderx-core.c | 35 ++
2 files changed, 41 insertions(+)
diff --git a/drivers/i2c/buss
This is an intermediate commit in preparation of the driver split.
The module rename in this commit will be reverted in the next patch,
this is just done to make the series bisectible.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/Makefile
-smbus.h includes
- Use IS_ENABLED for CONFIG options
Jan
-
Jan Glauber (8):
i2c: octeon: Rename driver to prepare for split
i2c: octeon: Split the driver into two parts
i2c: thunderx: Add i2c driver for ThunderX SOC
i2c: thunderx: Add smbus alert
On Mon, Apr 18, 2016 at 01:19:31PM +0100, Will Deacon wrote:
> On Mon, Apr 18, 2016 at 09:43:33AM +0200, Jan Glauber wrote:
> > On Fri, Apr 15, 2016 at 12:37:06PM +0100, Will Deacon wrote:
> > > You can remove stop_lock altogether now, right? I also wonder whether
> > >
On Tue, Apr 19, 2016 at 04:06:08PM +0100, Mark Rutland wrote:
> On Wed, Mar 09, 2016 at 05:21:03PM +0100, Jan Glauber wrote:
> > Provide "uncore" facilities for different non-CPU performance
> > counter units. Based on Intel/AMD uncore pmu support.
> >
> > The
On Wed, Apr 13, 2016 at 10:55:20AM +0200, Wolfram Sang wrote:
>
> Please have a look at Documentation/i2c/fault-codes. -EAGAIN is only for
> arbitration loss.
>
> > + /* ACK allowed on pre-terminal bytes only */
> > + case STAT_RXDATA_ACK:
> > + if (!final_read)
> > +
On Wed, Apr 13, 2016 at 10:45:21AM +0200, Wolfram Sang wrote:
> On Mon, Apr 11, 2016 at 05:28:35PM +0200, Jan Glauber wrote:
> > Add helper functions for control, data and status register access.
> >
> > Signed-off-by: Jan Glauber <jglau...@cavium.com>
>
> Sa
Hi Jeremy,
I've tested the patches on ThunderX and got perf running with ACPI,
so you can add my Tested-by if you like.
Thanks,
Jan
On Tue, Apr 12, 2016 at 03:21:05PM -0500, Jeremy Linton wrote:
> v3->v4:
> Correct build issues with ARM (!ARM64) kernels.
> Add ThunderX to list of PMU types.
>
with data
about all other CPUs too.
Therefore remove the stack dump and printk of other CPUs
and only print a single line that the other CPUs are going to be
stopped.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
arch/arm64/kernel/smp.c | 11 +++
1 file changed, 3 insertions
On Wed, Apr 20, 2016 at 11:31:21PM +0200, Wolfram Sang wrote:
> On Mon, Apr 11, 2016 at 05:28:38PM +0200, Jan Glauber wrote:
> > Switch to the i2c bus recovery framework using generic SCL recovery.
> > If this fails try to reset the hardware. The recovery is triggered
> > du
On Wed, Apr 20, 2016 at 02:55:15PM -0700, David Daney wrote:
> On 04/20/2016 02:43 PM, Wolfram Sang wrote:
> >On Mon, Apr 11, 2016 at 05:28:39PM +0200, Jan Glauber wrote:
> [...]
> >>+ */
> >>+static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c
On Wed, Apr 20, 2016 at 11:43:54PM +0200, Wolfram Sang wrote:
> On Mon, Apr 11, 2016 at 05:28:39PM +0200, Jan Glauber wrote:
> > From: David Daney <dda...@caviumnetworks.com>
> >
> > Use High-Level Controller (HLC) when possible. The HLC can read/write
> > up to 8
Mark,
are these patches still queued or should I repost them?
--Jan
On Mon, Apr 04, 2016 at 01:03:13PM +0200, Jan Glauber wrote:
> Hi Mark,
>
> can you have a look at these patches?
>
> Thanks,
> Jan
>
> 2016-03-09 17:21 GMT+01:00 Jan Glauber <jglau...@cavium.com&g
are going to be
stopped and, in case any CPUs remain online list them.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
arch/arm64/kernel/smp.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index b2d5f4e.
On Sun, Jul 24, 2016 at 02:38:11PM -0400, Paul Gortmaker wrote:
> On Sat, Jul 23, 2016 at 6:42 AM, Jan Glauber <jglau...@cavium.com> wrote:
> > Separate driver probing from SPI transfer functions.
> >
> > Signed-off-by: Jan Glauber <jglau...@cavium.com>
> &
On Sun, Jul 24, 2016 at 09:54:16PM +0100, Mark Brown wrote:
> On Sat, Jul 23, 2016 at 12:42:54PM +0200, Jan Glauber wrote:
>
> > + dev_info(>dev, "OCTEON SPI bus driver\n");
>
> This is just noise, remove it.
I'll remove these in both drivers.
Thanks,
Jan
On Sun, Jul 24, 2016 at 10:04:52PM +0100, Mark Brown wrote:
> On Sat, Jul 23, 2016 at 12:42:55PM +0200, Jan Glauber wrote:
>
> > +config SPI_THUNDERX
> > + tristate "Cavium ThunderX SPI controller"
> > + depends on 64BIT && PCI && !CAVIUM
Separate driver probing from SPI transfer functions.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/spi/Makefile | 1 +
drivers/spi/spi-cavium-octeon.c| 102
drivers/spi/{spi-octeon.c => spi-cavium
Add ThunderX SPI driver using the shared part from the Octeon
driver. The main difference of the ThunderX driver is that it
is a PCI device so probing is different. The system clock settings
can be specified in device tree.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/spi/K
merged patches
thanks,
Jan
--
Jan Glauber (2):
spi: octeon: Split driver into Octeon specific and common parts
spi: octeon: Add thunderx driver
drivers/spi/Kconfig| 7 ++
drivers/spi/Makefile | 3 +
drivers/spi/spi-cavium-octeon.c
Add ThunderX SPI driver using the shared part from the Octeon
driver. The main difference of the ThunderX driver is that it
is a PCI device so probing is different. The system clock settings
can be specified in device tree.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/spi/K
Separate driver probing from SPI transfer functions.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/spi/Makefile | 1 +
drivers/spi/spi-cavium-octeon.c| 102
drivers/spi/{spi-octeon.c => spi-cavium
On Wed, Jul 27, 2016 at 07:08:24PM +0100, Mark Brown wrote:
> On Mon, Jul 25, 2016 at 07:56:22PM +0200, Jan Glauber wrote:
> > Add ThunderX SPI driver using the shared part from the Octeon
> > driver. The main difference of the ThunderX driver is that it
> > is a PCI device so
On Tue, Jun 28, 2016 at 11:24:20AM +0100, Will Deacon wrote:
> Hi Jan,
>
> On Wed, Mar 09, 2016 at 05:21:02PM +0100, Jan Glauber wrote:
> > This patch series provides access to various counters on the ThunderX SOC.
> >
> > For details of the uncore implementation see
Add ThunderX SPI driver using the shared part from the Octeon
driver. The main difference of the ThunderX driver is that it
is a PCI device so probing is different. The system clock settings
can be specified in device tree.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/spi/K
Storing the system clock frequency in struct octeon_spi avoids
calling the MIPS specific octeon_get_io_clock_rate() for every transfer.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Tested-by: Steven J. Hill <steven.h...@cavium.com>
---
drivers/spi/spi-octeon.c | 7 +++
1 fil
From: "Steven J. Hill" <steven.h...@cavium.com>
Remove all calls to cvmx_read_csr()/cvmx_write_csr() and use
the portable readq()/writeq() functions.
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
d
Instead of hard-coding the register offsets put them into a struct
and set them in the probe function.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Tested-by: Steven J. Hill <steven.h...@cavium.com>
---
drivers/spi/spi-octeon.c | 41 +++--
1
Move the register definitions to the drivers directory because they
are only used there.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Tested-by: Steven J. Hill <steven.h...@cavium.com>
---
.../cvmx-mpi-defs.h => drivers/spi/spi-cavium.h| 32 +-
prepare the Octeon driver for re-use.
Patch #6 adds the ThunderX driver.
The series was tested on MIPS (Edge Router PRO and cn71xx) and ThunderX.
Feedback welcome!
thanks,
Jan
Jan Glauber (5):
spi: octeon: Store system clock freqency in struct octeon_spi
spi: octeon: Put register offsets
Separate driver probing from SPI transfer functions.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Tested-by: Steven J. Hill <steven.h...@cavium.com>
---
drivers/spi/Makefile | 1 +
drivers/spi/spi-cavium-octeon.c| 104 +
Add Support for the scatter-gather DMA available in the
ThunderX MMC units. Up to 16 DMA requests can be processed
together.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
://marc.info/?l=linux-mmc=147431759215233=2
Cheers,
Jan
---
Jan Glauber (9):
dt-bindings: mmc: Add Cavium SOCs MMC bindings
mmc: cavium: Add core MMC driver for Cavium SOCs
mmc: cavium: Add MMC platform driver for Octeon SOCs
mmc: cavium: Work-around hardware bug on cn6xxx and cnf7xxx
Prevent data corruption on cn6xxx and cnf7xxx.
Due to an imperfection in the design of the MMC bus hardware,
the 2nd to last cache block of a DMA read must be locked into the L2
cache.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
Add support for switching to DDR mode for eMMC devices.
Although the host controller only supports 3.3 Volt
and DDR52 uses 1.8 Volt according to the specification
it is possible to use DDR also with 3.3 Volt for eMMC chips.
To switch to DDR mode MMC_CAP_1_8V_DDR is required.
Signed-off-by: Jan
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2c171
The MMC unit on Octeon cn7890 differs in that it has multiple
interrupts. Requires a lock for the interrupt handler. DMA addresses
have a dedicated 64 bit register now, so use that when available.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Signed-off-by: David Daney <david.da...@c
Add description of Cavium Octeon and ThunderX SOC device tree bindings.
CC: Ulf Hansson <ulf.hans...@linaro.org>
CC: Rob Herring <robh...@kernel.org>
CC: Mark Rutland <mark.rutl...@arm.com>
CC: devicet...@vger.kernel.org
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Si
ices is required because the host
controller is shared.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
---
drivers/mmc/host/cavium-mmc.c | 1029
Add a platform driver for ThunderX ARM SOCs.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
---
drivers/mmc/host/Kconfig | 10 ++
drivers
Add a platform driver for Octeon MIPS SOCs.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
Signed-off-by: David Daney <david.da...@cavium.com>
Signed-off-by: Steven J. Hill <steven.h...@cavium.com>
---
drivers/mmc/host/Kconfig | 10 ++
drivers
the child node of the
slot.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/mmc/core/host.c| 8 +++-
drivers/mmc/host/davinci_mmc.c | 2 +-
drivers/mmc/host/dw_mmc.c | 2 +-
drivers/mmc/host/meson-gx-mmc.c| 2 +-
drivers/mmc/host/mmci.c
On Tue, Jan 24, 2017 at 09:56:55AM +0100, Ulf Hansson wrote:
> On 21 January 2017 at 11:59, Jan Glauber <jglau...@cavium.com> wrote:
> > Extend mmc_of_parse to get the device node pointer as an
> > additional argument instead of using the device node of the
> > mmc dev
Using pci_alloc_irq_vectors() instead of the deprecated
pci_enable_msix() allows to remove the msix_entry from
struct octeon_i2c and thus to get rid of the config symbol check.
Signed-off-by: Jan Glauber <jglau...@cavium.com>
---
drivers/i2c/busses/i2c-octeon-core.h | 4
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