RISC-V systems use device tree to specify the memory layout of the
system. This patch reserves the "riscv" vendor prefix, which will be
used for devices that are specified by the various RISC-V ISA
specifications.
Signed-off-by: Palmer Dabbelt
---
Documentation/devicetree/bindi
On Tue, 27 Jun 2017 16:37:40 PDT (-0700), helg...@kernel.org wrote:
> [+cc Lorenzo]
>
> Hi Palmer,
>
> On Fri, Jun 23, 2017 at 02:45:38PM -0700, Palmer Dabbelt wrote:
>> We wanted to add RISC-V to the list of architectures that used the
>> generic PCI setu
On Wed, 12 Jul 2017 04:04:00 PDT (-0700), m...@ellerman.id.au wrote:
> Palmer Dabbelt writes:
>
>> On Mon, 10 Jul 2017 23:21:07 PDT (-0700), m...@ellerman.id.au wrote:
>>> Palmer Dabbelt writes:
>>>>
>>> ...
>>>> +#ifdef CONFIG_EARLY_PRINTK
On Wed, 12 Jul 2017 04:07:51 PDT (-0700), james.ho...@imgtec.com wrote:
> On Tue, Jul 11, 2017 at 06:31:29PM -0700, Palmer Dabbelt wrote:
>> diff --git a/arch/riscv/include/asm/unistd.h
>> b/arch/riscv/include/asm/unistd.h
>> new file mode 100644
>> index 000
On Wed, 12 Jul 2017 05:40:49 PDT (-0700), boqun.f...@gmail.com wrote:
> On Tue, Jul 11, 2017 at 06:31:23PM -0700, Palmer Dabbelt wrote:
> [...]
>> diff --git a/arch/riscv/include/asm/bitops.h
>> b/arch/riscv/include/asm/bitops.h
>> new file mode 100644
>> in
On Wed, 12 Jul 2017 15:50:42 PDT (-0700), helg...@kernel.org wrote:
> On Tue, Jul 11, 2017 at 06:31:15PM -0700, Palmer Dabbelt wrote:
>> Multiple architectures define this as trivial function, and I'm adding
>> another one as part of the RISC-V port. This adds a
On Wed, 12 Jul 2017 10:09:55 PDT (-0700), james.ho...@imgtec.com wrote:
> On Wed, Jul 12, 2017 at 09:24:24AM -0700, Palmer Dabbelt wrote:
>> On Wed, 12 Jul 2017 04:07:51 PDT (-0700), james.ho...@imgtec.com wrote:
>> > On Tue, Jul 11, 2017 at 06:31:29PM -0700, Palmer Dabbelt wrote
On Thu, 13 Jul 2017 05:32:26 PDT (-0700), james.ho...@imgtec.com wrote:
> On Thu, Jul 13, 2017 at 09:59:53PM +1000, Michael Ellerman wrote:
>> Palmer Dabbelt writes:
>>
>> > On Wed, 12 Jul 2017 04:04:00 PDT (-0700), m...@ellerman.id.au wrote:
>> >> Palmer Dabb
On Mon, 10 Jul 2017 13:00:29 PDT (-0700), Palmer Dabbelt wrote:
> On Thu, 06 Jul 2017 08:45:13 PDT (-0700), will.dea...@arm.com wrote:
>> On Thu, Jul 06, 2017 at 08:34:27AM -0700, Christoph Hellwig wrote:
>>> On Thu, Jul 06, 2017 at 09:55:03AM +0100, Will Deacon w
On Fri, 07 Jul 2017 01:08:19 PDT (-0700), pet...@infradead.org wrote:
> On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote:
>> +/*
>> + * TODO_RISCV_MEMORY_MODEL: I don't think RISC-V is allowed to perform a
>> + * speculative load, but we're going to wa
On Fri, 07 Jul 2017 06:16:07 PDT (-0700), j.neuschae...@gmx.net wrote:
> On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote:
> [...]
>> +/* These barries need to enforce ordering on both devices or memory. */
>
> Very minor nit: s/barries/barriers/ (in severa
On Fri, 07 Jul 2017 05:58:55 PDT (-0700), j.neuschae...@gmx.net wrote:
> On Thu, Jul 06, 2017 at 03:34:39PM -0700, Palmer Dabbelt wrote:
>> On Tue, 04 Jul 2017 14:54:01 PDT (-0700), j.neuschae...@gmx.net wrote:
> [...]
>> >> +#define DO_ERROR_INF
On Thu, 06 Jul 2017 19:14:25 PDT (-0700), boqun.f...@gmail.com wrote:
> On Thu, Jul 06, 2017 at 06:04:13PM -0700, Palmer Dabbelt wrote:
> [...]
>> >> +#define __smp_load_acquire(p)
building locally.
Signed-off-by: Palmer Dabbelt
---
Makefile | 3 +-
arch/riscv/Kconfig| 294 ++
arch/riscv/Makefile | 64 +++
arch/riscv/configs/freedom-u500_defconfig | 52 ++
arch
memory model by the end of the year, but my
understanding is that the basic definitions we're relying on here won't
change significantly.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/atomic.h | 328
arch/riscv/include/asm/barrier.h| 68
pcibios_fixup_bus. None of the other architectures export this, so I
just dropped it.
Signed-off-by: Palmer Dabbelt
---
arch/cris/arch-v32/drivers/pci/bios.c | 4
arch/microblaze/pci/pci-common.c | 6 --
arch/s390/pci/pci.c | 4
arch/sh/drivers/pci/pci.c
are
functionally identical to the various other copies. These are
availiable via Kconfig as CONFIG_LIB_$ROUTINE, which currently isn't
used anywhere.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Geert Uytterhoeven
---
include/lib/libgcc.h | 44
lib/Kconfig | 18
controller). Per-hart local interrupt
controllers are found on all RISC-V systems.
Signed-off-by: Palmer Dabbelt
---
drivers/irqchip/Kconfig | 14 +++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-riscv-intc.c | 213 +++
3 files changed, 228
This patch adds a driver for the Platform Level Interrupt Controller
(PLIC) specified as part of the RISC-V supervisor level ISA manual.
The PLIC connocts global interrupt sources to the local interrupt
controller on each hart. A PLIC is present on all RISC-V systems.
Signed-off-by: Palmer
This patch contains code that is more specific to the RISC-V ISA than it
is to Linux. It contains string and math operations, C wrappers for
various assembly instructions, stack walking code, and uaccess.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm.h| 76
This patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal
handling. It also contains some generic code that is ABI visible.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu.h | 26 +++
arch/riscv
This patch contains the code that interfaces with ELF objects on RISC-V
systems, the vast majority of which is present to load kernel modules.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/compat.h | 29 ++
arch/riscv/include/asm/elf.h| 84
This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm-offsets.h | 1 +
arch/riscv/include/asm/current.h | 45
arch/riscv/include/asm/kprobes.h | 22 ++
arch/riscv
This patch contains code to manage the RISC-V MMU, including definitions
of the page tables and the page walking code.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu_context.h | 69 ++
arch/riscv/include/asm/page.h | 134 +++
arch/riscv/include/asm/pgalloc.h
This patch contains code that interfaces with devices that are mandated
by the RISC-V supervisor specification and that don't have explicit
drivers anywhere else in the tree. This includes the staticly defined
interrupts, the CSR-mapped timer, and virtualized SBI devices.
Signed-off-by: Palmer
From: Jonathan Neuschäfer
RISC-V needs a MAINTAINERS entry. Let's add one.
Signed-off-by: Jonathan Neuschäfer
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d8eab9322ba2..3ead16565003 100644
The RISC-V ISA defines a simple console that is availiable via SBI calls
on all systems. This patch adds a driver for this console interface
that can act as both a target for early printk and as the system
console.
Signed-off-by: Palmer Dabbelt
---
drivers/tty/hvc/Kconfig | 11
pcibios_fixup_bus. Only some architectures export this, so I
just dropped it.
Signed-off-by: Palmer Dabbelt
---
arch/arc/kernel/pcibios.c| 13 -
arch/arm64/kernel/pci.c | 17 -
arch/ia64/pci/pci.c | 7 ---
arch/microblaze/pci/pci
This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system. When a file was
init-related this patch contains the entire file.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/bug.h | 88 +++
arch/riscv/include
Thanks to everyone who has participated in the review process so far. I've
based this patch set on the current master. Things have really started to
calmn down, so this is fairly similar to the v4 patch set. The most
interesting changes include:
* We've moved back to a single patch set.
*
the hardware from the clocksource driver by taking a pair of
function pointers to issue the actual RISC-V specific instructions.
Signed-off-by: Palmer Dabbelt
---
drivers/clocksource/Kconfig | 8 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/riscv_timer.c | 64
On Mon, 10 Jul 2017 19:02:19 PDT (-0700), s...@canb.auug.org.au wrote:
> Hi Palmer,
>
> On Mon, 10 Jul 2017 18:39:08 -0700 Palmer Dabbelt wrote:
>>
>> This patch adds a new copy of these library routine files, which are
>> functionally identical
On Mon, 10 Jul 2017 19:03:44 PDT (-0700), rdun...@infradead.org wrote:
> On 07/10/2017 07:02 PM, Stephen Rothwell wrote:
>> Hi Palmer,
>>
>> On Mon, 10 Jul 2017 18:39:08 -0700 Palmer Dabbelt wrote:
>>>
>>> This patch adds a new copy of these library ro
On Mon, 10 Jul 2017 23:21:07 PDT (-0700), m...@ellerman.id.au wrote:
> Palmer Dabbelt writes:
>>
> ...
>> +#ifdef CONFIG_EARLY_PRINTK
>> +static void sbi_console_write(struct console *co, const char *buf,
>> + unsigned int n)
>> +{
&g
On Mon, 10 Jul 2017 23:31:18 PDT (-0700), m...@ellerman.id.au wrote:
> Palmer Dabbelt writes:
>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> new file mode 100644
>> index ..366f5f2cf106
>> --- /dev/null
>> +++ b/
On Tue, 11 Jul 2017 06:22:15 PDT (-0700), will.dea...@arm.com wrote:
> On Mon, Jul 10, 2017 at 01:00:29PM -0700, Palmer Dabbelt wrote:
>> On Thu, 06 Jul 2017 08:45:13 PDT (-0700), will.dea...@arm.com wrote:
>> > On Thu, Jul 06, 2017 at 08:34:27AM -0700, Christoph Hellwig wrote:
On Tue, 11 Jul 2017 06:55:28 PDT (-0700), h...@infradead.org wrote:
> On Tue, Jul 11, 2017 at 02:22:15PM +0100, Will Deacon wrote:
>> The problem is that by supporting these hypothetical designs that can't do
>> atomics, you hurt sensible designs that *can* do the atomics because you
>> force them
On Tue, 11 Jul 2017 07:01:32 PDT (-0700), james.ho...@imgtec.com wrote:
> Hi Christoph,
>
> On Tue, Jul 11, 2017 at 06:39:48AM -0700, Christoph Hellwig wrote:
>> > +#ifdef CONFIG_64BIT
>> > +SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
>> > + unsigned long, prot, unsigned long,
On Tue, 11 Jul 2017 11:39:19 PDT (-0700), mcg...@kernel.org wrote:
> On Mon, Jul 10, 2017 at 06:39:07PM -0700, Palmer Dabbelt wrote:
>> Thanks to everyone who has participated in the review process so far. I've
>> based this patch set on the current master. Things have really star
While it's only been a day since the last patch set (which might be a bit
fast), I've generally been spinning new patch sets whenever I get through my
inbox. For my other patch sets I've managed to get buried in a week's worth of
email in a few hours, but for this one it appears there's been
pcibios_fixup_bus. None of the other architectures export this, so I
just dropped it.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Luis R. Rodriguez
---
arch/cris/arch-v32/drivers/pci/bios.c | 4
arch/microblaze/pci/pci-common.c | 6 --
arch/s390/pci/pci.c | 4
arch/sh
memory model by the end of the year, but my
understanding is that the basic definitions we're relying on here won't
change significantly.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/atomic.h | 328
arch/riscv/include/asm/barrier.h| 68
This patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal
handling. It also contains some generic code that is ABI visible.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu.h | 26 +++
arch/riscv
This patch contains the code that interfaces with ELF objects on RISC-V
systems, the vast majority of which is present to load kernel modules.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/compat.h | 29 ++
arch/riscv/include/asm/elf.h| 84
This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm-offsets.h | 1 +
arch/riscv/include/asm/current.h | 45
arch/riscv/include/asm/kprobes.h | 22 ++
arch/riscv
the hardware from the clocksource driver by taking a pair of
function pointers to issue the actual RISC-V specific instructions.
Signed-off-by: Palmer Dabbelt
---
drivers/clocksource/Kconfig | 8 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/riscv_timer.c | 64
building locally.
Signed-off-by: Palmer Dabbelt
---
Makefile | 3 +-
arch/riscv/Kconfig| 283 ++
arch/riscv/Makefile | 64 +++
arch/riscv/configs/freedom-u500_defconfig | 52 ++
arch
This patch contains code to manage the RISC-V MMU, including definitions
of the page tables and the page walking code.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu_context.h | 69 ++
arch/riscv/include/asm/page.h | 134 +++
arch/riscv/include/asm/pgalloc.h
This patch contains code that interfaces with devices that are mandated
by the RISC-V supervisor specification and that don't have explicit
drivers anywhere else in the tree. This includes the staticly defined
interrupts, the CSR-mapped timer, and virtualized SBI devices.
Signed-off-by: Palmer
This patch contains code that is more specific to the RISC-V ISA than it
is to Linux. It contains string and math operations, C wrappers for
various assembly instructions, stack walking code, and uaccess.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm.h| 76
From: Jonathan Neuschäfer
RISC-V needs a MAINTAINERS entry. Let's add one.
Signed-off-by: Jonathan Neuschäfer
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2af3ab3f7702..3f39f16046dd 100644
This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system. When a file was
init-related this patch contains the entire file.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/bug.h | 88 +++
arch/riscv/include
pcibios_fixup_bus. Only some architectures export this, so I
just dropped it.
Signed-off-by: Palmer Dabbelt
---
arch/arc/kernel/pcibios.c| 13 -
arch/arm64/kernel/pci.c | 17 -
arch/ia64/pci/pci.c | 7 ---
arch/microblaze/pci/pci
This patch adds a driver for the Platform Level Interrupt Controller
(PLIC) specified as part of the RISC-V supervisor level ISA manual.
The PLIC connocts global interrupt sources to the local interrupt
controller on each hart. A PLIC is present on all RISC-V systems.
Signed-off-by: Palmer
The RISC-V ISA defines a simple console that is availiable via SBI calls
on all systems. This patch adds a driver for this console interface
that can act as both a target for early printk and as the system
console.
Signed-off-by: Palmer Dabbelt
---
drivers/tty/hvc/Kconfig | 11
controller). Per-hart local interrupt
controllers are found on all RISC-V systems.
Signed-off-by: Palmer Dabbelt
---
drivers/irqchip/Kconfig | 14 +++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-riscv-intc.c | 213 +++
3 files changed, 228
are
functionally identical to the various other copies. These are
availiable via Kconfig as CONFIG_GENERIC_$ROUTINE, which currently isn't
used anywhere.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Geert Uytterhoeven
---
include/lib/libgcc.h | 44
lib/Kconfig | 18
rivers that are
required to build and boot a RISC-V system. A tree that contains this patch
set merged with all our other patch sets lives at
https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v3
commit 319a127e0685ed294996e0e6b25b229f42ec1d6e
Merge: a980edd4a4b7 e67734c51bc9
Author:
memory model by the end of the year, but my
understanding is that the basic definitions we're relying on here won't
change significantly.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/atomic.h | 330
arch/riscv/include/asm/barrier.h| 139
This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system. When a file was
init-related, it contains
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/bug.h | 88 +++
arch/riscv/include/asm/cache.h | 22
This patch contains the code that interfaces with ELF objects on RISC-V
systems, the vast majority of which is present to load kernel modules.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/compat.h | 31 +++
arch/riscv/include/asm/elf.h| 85
This patch contains code that interfaces with devices that are mandated
by the RISC-V supervisor specification and that don't have explicit
drivers anywhere else in the tree. This includes the staticly defined
interrupts, the CSR-mapped timer, and virtualized SBI devices.
Signed-off-by: Palmer
This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm-offsets.h | 1 +
arch/riscv/include/asm/current.h | 43
arch/riscv/include/asm/kprobes.h | 22 ++
arch/riscv
This patch contains code that is more specific to the RISC-V ISA than it
is to Linux. It contains string and math operations, C wrappers for
various assembly instructions, stack walking code, and uaccess.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm.h| 76
This patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal
handling. It also contains some generic code that is ABI visible.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu.h | 26 +++
arch/riscv
building locally.
Signed-off-by: Palmer Dabbelt
---
Makefile | 3 +-
arch/riscv/Kconfig| 318 ++
arch/riscv/Makefile | 64 ++
arch/riscv/configs/freedom-u500_defconfig | 53 +
arch
This patch contains code to manage the RISC-V MMU, including definitions
of the page tables and the page walking code.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu_context.h | 69 ++
arch/riscv/include/asm/page.h | 138 +++
arch/riscv/include/asm/pgalloc.h
On Wed, 28 Jun 2017 14:05:14 PDT (-0700), mer...@debian.org wrote:
> On Wed, Jun 28, 2017 at 11:55:38AM -0700, Palmer Dabbelt wrote:
>> This patch contains all the build infastructure that actually enables
>> the RISC-V port. This includes Makefiles, linker scripts, and Kconfig
>
On Wed, 28 Jun 2017 13:47:40 PDT (-0700), t...@linutronix.de wrote:
> On Mon, 26 Jun 2017, Palmer Dabbelt wrote:
>> +DEFINE_PER_CPU(struct riscv_irq_data, riscv_irq_data);
>> +DEFINE_PER_CPU(atomic_long_t, riscv_early_sie);
>> +
>> +static void riscv_software_inter
On Wed, 28 Jun 2017 14:25:00 PDT (-0700), james.ho...@imgtec.com wrote:
> Hi Palmer,
>
> On Wed, Jun 28, 2017 at 11:55:38AM -0700, Palmer Dabbelt wrote:
>> +select SYSRISCV_ATOMIC if !ISA_A
> ...
>> +config SYSRISCV_ATOMIC
>> +bool "Include su
On Wed, 28 Jun 2017 14:49:44 PDT (-0700), t...@linutronix.de wrote:
> On Wed, 28 Jun 2017, Palmer Dabbelt wrote:
>> +
>> +SYSCALL_DEFINE3(sysriscv_cmpxchg32, unsigned long, arg1, unsigned long,
>> arg2,
>> +unsigned long, arg3)
>> +{
>> +uns
On Wed, 28 Jun 2017 15:42:37 PDT (-0700), james.ho...@imgtec.com wrote:
> Hi Palmer,
>
> On Wed, Jun 28, 2017 at 11:55:37AM -0700, Palmer Dabbelt wrote:
>> diff --git a/arch/riscv/include/asm/syscalls.h
>> b/arch/riscv/include/asm/syscalls.h
>> new file mode 1
On Wed, 28 Jun 2017 16:09:59 PDT (-0700), james.ho...@imgtec.com wrote:
> On Wed, Jun 28, 2017 at 11:55:36AM -0700, Palmer Dabbelt wrote:
>> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
>> new file mode 100644
>> index ..e1491c20
On Wed, 28 Jun 2017 15:54:42 PDT (-0700), james.ho...@imgtec.com wrote:
> On Wed, Jun 28, 2017 at 11:55:38AM -0700, Palmer Dabbelt wrote:
>> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
>> new file mode 100644
>> index ..7f58cd251ab8
>
On Wed, 28 Jun 2017 16:32:55 PDT (-0700), james.ho...@imgtec.com wrote:
> On Wed, Jun 28, 2017 at 11:55:34AM -0700, Palmer Dabbelt wrote:
>> diff --git a/arch/riscv/include/asm/kprobes.h
>> b/arch/riscv/include/asm/kprobes.h
>> new file mode 100644
>> index 000
On Thu, 29 Jun 2017 01:39:25 PDT (-0700), tklau...@distanz.ch wrote:
> On 2017-06-28 at 20:55:35 +0200, Palmer Dabbelt wrote:
> [...]
>> diff --git a/arch/riscv/include/asm/device.h
>> b/arch/riscv/include/asm/device.h
>> new file mode 100644
>> index .
On Thu, 29 Jun 2017 02:44:32 PDT (-0700), ge...@linux-m68k.org wrote:
> Hi Palmer,
>
> On Wed, Jun 28, 2017 at 8:55 PM, Palmer Dabbelt wrote:
>> This contains the various __init C functions, the initial assembly
>> kernel entry point, and the code to reset the system. Wh
On Thu, 29 Jun 2017 01:22:23 PDT (-0700), tklau...@distanz.ch wrote:
> On 2017-06-28 at 20:55:34 +0200, Palmer Dabbelt wrote:
> [...]
>> diff --git a/arch/riscv/include/asm/kprobes.h
>> b/arch/riscv/include/asm/kprobes.h
>> new file mode 100644
>> index
On Thu, 29 Jun 2017 13:35:15 PDT (-0700), r...@kernel.org wrote:
> On Mon, Jun 26, 2017 at 10:21:22PM -0700, Palmer Dabbelt wrote:
>> RISC-V systems use device tree to specify the memory layout of the
>> system. This patch reserves the "riscv" vendor prefix, which wi
This patch contains code that is more specific to the RISC-V ISA than it
is to Linux. It contains string and math operations, C wrappers for
various assembly instructions, stack walking code, and uaccess.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm.h| 76
memory model by the end of the year, but my
understanding is that the basic definitions we're relying on here won't
change significantly.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/atomic.h | 337
arch/riscv/include/asm/barrier.h| 143
On Mon, 03 Jul 2017 16:06:39 PDT (-0700), james.ho...@imgtec.com wrote:
> On Thu, Jun 29, 2017 at 02:42:38PM -0700, Palmer Dabbelt wrote:
>> On Wed, 28 Jun 2017 15:42:37 PDT (-0700), james.ho...@imgtec.com wrote:
>> > On Wed, Jun 28, 2017 at 11:55:37AM -0700, Palmer Dabbelt wrote
On Tue, 04 Jul 2017 14:54:01 PDT (-0700), j.neuschae...@gmx.net wrote:
> Hi, below are some small comments.
>
> On Tue, Jul 04, 2017 at 12:50:54PM -0700, Palmer Dabbelt wrote:
>> This contains the various __init C functions, the initial assembly
>> kernel entry point,
On Wed, 05 Jul 2017 01:43:21 PDT (-0700), pet...@infradead.org wrote:
> On Tue, Jul 04, 2017 at 12:50:55PM -0700, Palmer Dabbelt wrote:
>> +/*
>> + * FIXME: I could only find documentation that atomic_{add,sub,inc,dec} are
>> + * barrier-free. I'm assuming that and
On Mon, 03 Jul 2017 04:13:34 PDT (-0700), t...@linutronix.de wrote:
> On Thu, 29 Jun 2017, Palmer Dabbelt wrote:
>> On Wed, 28 Jun 2017 13:47:40 PDT (-0700), t...@linutronix.de wrote:
>> In this case the software interrupt is to handle IPIs, so it doesn't really
>> make an
Thanks to everyone who has participated in the review process so far. There
have only been a few changes since the v3 patch set:
* The cmpxchg64 syscall is no longer enabled on 32-bit systems. It's not
possible to provide this on SMP systems, and it's not necessary as glibc
knows not to
This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm-offsets.h | 1 +
arch/riscv/include/asm/current.h | 44
arch/riscv/include/asm/kprobes.h | 22 ++
arch/riscv
This patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal
handling. It also contains some generic code that is ABI visible.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/elf.h | 3 +-
arch/riscv
This patch contains code that interfaces with devices that are mandated
by the RISC-V supervisor specification and that don't have explicit
drivers anywhere else in the tree. This includes the staticly defined
interrupts, the CSR-mapped timer, and virtualized SBI devices.
Signed-off-by: Palmer
This patch contains code to manage the RISC-V MMU, including definitions
of the page tables and the page walking code.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu_context.h | 69 ++
arch/riscv/include/asm/page.h | 134 +++
arch/riscv/include/asm/pgalloc.h
This patch contains the code that interfaces with ELF objects on RISC-V
systems, the vast majority of which is present to load kernel modules.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/compat.h | 29 ++
arch/riscv/include/asm/elf.h| 83
building locally.
Signed-off-by: Palmer Dabbelt
---
Makefile | 3 +-
arch/riscv/Kconfig| 304 ++
arch/riscv/Makefile | 64 +++
arch/riscv/configs/freedom-u500_defconfig | 52 +
arch
This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system. When a file was
init-related, it contains
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/bug.h | 88 +++
arch/riscv/include/asm/cache.h | 22
On Tue, 23 May 2017 06:35:23 PDT (-0700), Arnd Bergmann wrote:
>> +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
>
> Please move the majority of this file into drivers/irqchip as a
> standalone driver.
OK.
On Tue, 23 May 2017 14:23:50 PDT (-0700), b...@kernel.crashing.org wrote:
> On Tue, 2017-05-23 at 14:55 +0200, Arnd Bergmann wrote:
>> > +
>> > +#include
>>
>> I would recommend providing your own {read,write}{b,w,l,q}{,_relaxed}
>> helpers using inline assembly, to prevent the compiler for
On Wed, 24 May 2017 01:52:13 PDT (-0700), matt.redfe...@imgtec.com wrote:
> Hi Palmer
>
>
> On 23/05/17 23:05, Palmer Dabbelt wrote:
>> Many ports (m32r, microblaze, mips, parisc, score, and sparc) use
>> functionally identical copies of various GCC library routine files
On Wed, 24 May 2017 02:01:39 PDT (-0700), matt.redfe...@imgtec.com wrote:
> Hi Palmer,
> This patch doesn't quite match the subject, since it only removes the
> mips specific implementation of __ucmpdi2. The following patch removes
> all of the intrinsics that you added to lib/ from arch/mips/lib.
On Wed, 24 May 2017 02:21:22 PDT (-0700), ge...@linux-m68k.org wrote:
> Hi Palmer,
>
> On Wed, May 24, 2017 at 12:05 AM, Palmer Dabbelt wrote:
>> I'm in the process of submitting the RISC-V Linux port, and someone noticed
>> that we were adding copies of some libgcc emulati
On Thu, 25 May 2017 10:05:05 PDT (-0700), pa...@ucw.cz wrote:
>> +static void ci_leaf_init(struct cacheinfo *this_leaf,
>> + struct device_node *node,
>> + enum cache_type type, unsigned int level)
>> +{
>> +this_leaf->of_node = node;
>> +
On Tue, 21 Nov 2017 07:58:29 PST (-0800), Christoph Hellwig wrote:
While we're at cleanups, I don't think arch/riscv/kernel/sys_riscv.c
needs to include for the mmap syscall stubs.
Thanks.
commit b43b17317dad57739721d459d7ab50f78432750b
Author: Palmer Dabbelt
Date: Tue Nov 21 07:59:28
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