From c23d712fe924b929c2eb39eba644fe74bcccfd37 Mon Sep 17 00:00:00 2001
From: Peter Rosin p...@axentia.se
Date: Thu, 23 Oct 2014 13:52:03 +0200
Subject: [PATCH] ARM: at91/dt: Fix sama5d3x typos.
The DT compatible strings also need binding documentation, but that is for
someone else to write
Hi Peter,
Thanks for your patch.
And thanks for the Ack!
Btw, do you use git send-email command to send the patch?
No, I didn't, git format-patch and paste into the mail body. Was there some
whitespace issues with the patch?
Cheers,
Peter
--
To unsubscribe from this list: send the
Ok, I'm trying with git send-email, sorry for the inconvenience.
Cheers,
Peter
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at
) {
perror(SNDCTL_DSP_SPEED);
return 1;
}
return 0;
}
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/atmel/atmel_ssc_dai.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel
From 1e5621d7b9887c648d1a66238dc82d715c1e2cad Mon Sep 17 00:00:00 2001
From: Peter Rosin p...@axentia.se
Date: Mon, 20 Oct 2014 14:38:04 +0200
Subject: [PATCH] ASoC: atmel_ssc_dai: Track playback and capture CMR dividers
separately.
The CMR divider register is shared by playback and capture
Hi!
(and thank you for the pointer to the example with the ssc-dai in master mode)
Hi Peter,
On 10/20/2014 09:45 PM, Peter Rosin wrote:
From 1e5621d7b9887c648d1a66238dc82d715c1e2cad Mon Sep 17 00:00:00
2001
From: Peter Rosin p...@axentia.se
Date: Mon, 20 Oct 2014 14:38:04 +0200
Hi again!
Hi Peter,
On 10/21/2014 03:55 PM, Peter Rosin wrote:
Hi!
(and thank you for the pointer to the example with the ssc-dai in
master mode)
Hi Peter,
On 10/20/2014 09:45 PM, Peter Rosin wrote:
From 1e5621d7b9887c648d1a66238dc82d715c1e2cad Mon Sep 17
00:00:00
2001
Hi again,
-Original Message-
From: Peter Rosin
Sent: Tuesday, October 21, 2014 13:05
To: 'Bo Shen'
Cc: Liam Girdwood; Mark Brown; Jaroslav Kysela; Takashi Iwai; 'alsa-
de...@alsa-project.org'; linux-kernel@vger.kernel.org
Subject: RE: [alsa-devel] [PATCH] ASoC: atmel_ssc_dai: Track
Hi!
Hi Peter,
On 10/21/2014 09:05 PM, Peter Rosin wrote:
I did some further tests, and the following program fails without the patch:
With the patch, it is OK?
Yes.
#include sys/ioctl.h
#include unistd.h
#include fcntl.h
#include sys/soundcard.h
int
main(void
Hi!
With the patch, it is OK?
Yes.
#include sys/ioctl.h
#include unistd.h
#include fcntl.h
#include sys/soundcard.h
int
main(void)
{
int fd;
int format;
int channels;
if ((fd = open(/dev/dsp, O_WRONLY, 0)) == -1) {
perror(open);
Bo Chen wrote:
with this piece of code, I reproduce your issue.
Now, I know the reason of this issue, work in oss mode, it will set the
default
clock to 8KHz, and then if change to other sample rate, for example 48KHz,
the div is different, then it reports -EBUSY.
Indeed.
So, I think we
From 86be84c4de4e7b21cfda9656a02a902c543210af Mon Sep 17 00:00:00 2001
From: Peter Rosin p...@axentia.se
Date: Wed, 22 Oct 2014 16:45:29 +0200
Subject: [PATCH v2] ASoC: atmel_ssc_dai: Match the CMR divider only in full
duplex.
The CMR divider register is shared by playback and capture. The SSC
Thanks for the review! I'm answering here, but would like to thank
Lars-Peter for the review as well.
Mark Brown wrote:
On Thu, Nov 06, 2014 at 01:54:00PM +0100, Peter Rosin wrote:
+#define TFA9879_REG(codec, reg, field, value) \
+ snd_soc_update_bits(codec, TFA9879_ ## reg
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
MAINTAINERS|6 +
sound/soc/codecs/Kconfig |5 +
sound/soc/codecs/Makefile |2 +
sound/soc/codecs/tfa9879.c | 323
sound/soc/codecs/tfa9879
On 2014-11-06 17:02, Mark Brown wrote: On Thu, Nov 06, 2014 at 02:37:31PM
+, Peter Rosin wrote:
Mark Brown wrote:
+if (tfa9879-lsb_justified)
+TFA9879_REG(codec, SERIAL_INTERFACE_1, I2S_SET,
i2s_set);
Why does this need to be reset every time, shouldn't we
Mark Brown wrote:
On Thu, Nov 06, 2014 at 05:39:45PM +0100, Peter Rosin wrote:
+ { TFA9879_MISC_STATUS, 0x }, /* 0x15, read-only
*/
The fix here is the wrong way round - if the device is reporting status
here there should be no default and there should be a volatile
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
MAINTAINERS|6 +
sound/soc/codecs/Kconfig |5 +
sound/soc/codecs/Makefile |2 +
sound/soc/codecs/tfa9879.c | 328
sound/soc/codecs/tfa9879
From: Peter Rosin p...@axentia.se
The DDRSDR controller (on the ATSAMA5D31) fails miserably to put LPDDR1
memories in self-refresh. Force the controller to think it has DDR2
memories during the self-refresh period, as the DDR2 self-refresh spec
is equivalent to LPDDR1, and is correctly
Hi!
Sorry for not sending this from my axentia.se account, but I tend to
get high spam-scores from there when I use git send-email.
This is a new driver, and it's pretty minimalistic with support for
only a few basic controls. However, it is usable and I'd be happy
to see it included.
I don't
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
MAINTAINERS|6 +
sound/soc/codecs/Kconfig |5 +
sound/soc/codecs/Makefile |2 +
sound/soc/codecs/tfa9879.c | 334
sound/soc/codecs/tfa9879
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/tfa9879.c | 16
1 file changed, 16 insertions(+)
diff --git a/sound/soc/codecs/tfa9879.c b/sound/soc/codecs/tfa9879.c
index 90cc28f7e6ed..0d62962542e2 100644
--- a/sound/soc
From: Peter Rosin p...@axentia.se
If a snd_soc_card has any DAPM routes when it calls
snd_soc_of_parse_audio_routing, those are clobbered without this change.
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/soc-core.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions
Mark Brown wrote:
On Thu, Nov 27, 2014 at 10:02:42PM +0100, Peter Rosin wrote:
- routes = devm_kzalloc(card-dev, num_routes * sizeof(*routes),
+ old_routes = card-num_dapm_routes;
+ routes = devm_kzalloc(card-dev,
+ (old_routes + num_routes) * sizeof
From: Peter Rosin p...@axentia.se
When the codec is connected using i2c, it will only auto-increment
register addresses if msb (0x80) of the register address byte is set.
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x-i2c.c |7 ++-
1 file changed, 6 insertions
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
Documentation/devicetree/bindings/sound/pcm512x.txt |3 ++-
sound/soc/codecs/pcm512x-i2c.c |4
sound/soc/codecs/pcm512x-spi.c |4
3 files changed, 10
Sylvain Rochet wrote:
Hello Nicolas,
On Mon, Jan 26, 2015 at 02:34:38PM +0100, Nicolas Ferre wrote:
Le 26/01/2015 11:36, Sylvain Rochet a écrit :
I think we should explain we are dealing with an errata here, this
is not obvious at first sight, the patch summary may find its place
Mark Brown wrote:
On Wed, Feb 04, 2015 at 12:52:25PM +0100, Peter Rosin wrote:
One thing remains a bit unclear, and that is the 500ppm deduction. Is
that really warranted? The number was just pulled out of my hat...
I don't really get what this is supposed to be protecting against
From: Peter Rosin p...@axentia.se
When the SSC acts as BCK master, use a ratnum rule to limit
the rate instead of only doing the standard rates. When the SSC
acts as BCK slave, allow any BCK frequency up to within 500ppm
of the SSC master clock, possibly divided by 2, 3 or 6.
Put a cap at 384kHz
Bo Shen wrote:
Hi Peter,
Hi!
On 02/07/2015 06:51 PM, Peter Rosin wrote:
Mark Brown wrote:
On Wed, Feb 04, 2015 at 12:52:25PM +0100, Peter Rosin wrote:
One thing remains a bit unclear, and that is the 500ppm deduction.
Is that really warranted? The number was just pulled out of my hat
Bo Shen wrote:
Hi Peter,
On 02/09/2015 04:09 PM, Peter Rosin wrote:
[Snip]
/*-*\
* DAI functions
@@ -200,6 +290,7 @@ static int atmel_ssc_startup(struct
snd_pcm_substream *substream
Nicolas Ferre wrote:
Le 14/01/2015 14:20, Peter Rosin a écrit :
From: Peter Rosin p...@axentia.se
The DDRSDR controller (on the ATSAMA5D31) fails miserably to put
LPDDR1 memories in self-refresh. Force the controller to think it has
DDR2 memories during the self-refresh period
As the clock can be get from TK/RK pin, so remove the comments.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
sound/soc/atmel/atmel_ssc_dai.c | 4
1 file changed, 4 deletions(-)
diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
index e691aab..198661b
From: Peter Rosin p...@axentia.se
Hi!
I wasn't sure if I should add Documentation/* for these sysfs knobs
or not? A lot of knobs do not seem to have docs (no specific example,
just a gut feeling). And I'm not sure how I should name the doc-file
since the pcm512x driver handles devices connected
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 884784fb1566..f13ff7578c78 100644
From: Peter Rosin p...@axentia.se
When using non-standard rates, a relatively small amount of overclocking
can make a big difference to a number of cases.
- Not all rates are possible to achieve with the PLL, due to divider
restrictions.
- The higher oversampling rates that can be used
From: Peter Rosin p...@axentia.se
Hi!
I wasn't sure if I should add Documentation/* for these sysfs knobs
or not? A lot of knobs do not have docs... And I'm not sure how I
should name the doc-file since the pcm512x driver handles devices
connected with both i2c and spi. So, this isn't perfect
From: Peter Rosin p...@axentia.se
Add helper functions to allow drivers to specify several disjoint
ranges for a variable. In particular, there is a codec (PCM512x) that
has a hole in its supported range of rates, due to PLL and divider
restrictions.
This is like snd_pcm_hw_constraint_list
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c |2 +-
sound/soc/codecs/pcm512x.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index
From: Peter Rosin p...@axentia.se
Hi!
[ Note that the dt change is in patch 5/7, for those only interested
in that particular bit. ]
This series implements BCLK master modes for the pcm512x driver. It has
only been tested with the pcm5142 chip, but they are from the same family
and should
From: Peter Rosin p...@axentia.se
Use register field names from the seemingly compatible PCM5242 datasheet,
as the PCM512x and PCM514x datasheets are severly lacking.
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 452
From: Peter Rosin p...@axentia.se
Using the PLL in master mode requires using an external connection
between one of the GPIO pins (configured as PLL/4 output) and the
SCK pin. It also requires the external clock to be fed to some other
GPIO pin instead of the SCK pin.
This is described
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 7f45cc468fa1..33aa18c8c88e 100644
From: Peter Rosin p...@axentia.se
The PLL introduces jitter, which in turn introduces noice if used
to clock the DAC. Thus, avoid the PLL output, and use the PLL input
to drive the DAC clock, if possible.
This is described for the PCM5142/PCM5242 chips in the answers to the
forum post PCM5142
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 874723c36d65..4c65eb9ab59b 100644
--- a/sound/soc
I wrote:
Sergei Shtylyov wrote:
On 1/27/2015 8:53 AM, Wenyou Yang wrote:
From: Peter Rosin p...@axentia.se
The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2
Sergei Shtylyov wrote:
Hello.
Hi!
On 1/27/2015 8:53 AM, Wenyou Yang wrote:
From: Peter Rosin p...@axentia.se
The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2
Hi Mark,
First of all, thanks for taking the rest of the series!
Mark Brown wrote:
On Wed, Jan 28, 2015 at 03:16:08PM +0100, Peter Rosin wrote:
@@ -78,7 +78,7 @@ static const struct reg_default
pcm512x_reg_defaults[] = {
{ PCM512x_DIGITAL_VOLUME_2, 0x30
From: Peter Rosin p...@axentia.se
Hi!
[ Note that the dt change is in patch 5/7, for those only interested
in that particular bit. ]
This series implements BCLK master modes for the pcm512x driver. It has
only been tested with the pcm5142 chip, but they are from the same family
and should
From: Peter Rosin p...@axentia.se
Add helper functions to allow drivers to specify several disjoint
ranges for a variable. In particular, there is a codec (PCM512x) that
has a hole in its supported range of rates, due to PLL and divider
restrictions.
This is like snd_pcm_hw_constraint_list
From: Peter Rosin p...@axentia.se
The PLL introduces jitter, which in turn introduces noice if used
to clock the DAC. Thus, avoid the PLL output, and use the PLL input
to drive the DAC clock, if possible.
This is described for the PCM5142/PCM5242 chips in the answers to the
forum post PCM5142
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 874723c36d65..4c65eb9ab59b 100644
--- a/sound/soc
From: Peter Rosin p...@axentia.se
Using the PLL in master mode requires using an external connection
between one of the GPIO pins (configured as PLL/4 output) and the
SCK pin. It also requires the external clock to be fed to some other
GPIO pin instead of the SCK pin.
This is described
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index d46d6cdb6b87..64be85fb2748 100644
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c |2 +-
sound/soc/codecs/pcm512x.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index
From: Peter Rosin p...@axentia.se
Use register field names from the seemingly compatible PCM5242 datasheet,
as the PCM512x and PCM514x datasheets are severly lacking.
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 441
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/atmel/atmel_ssc_dai.c | 48 +++
1 file changed, 48 insertions(+)
diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
index 3cd70597d109
From: Peter Rosin p...@axentia.se
Reported-by: kbuild test robot fengguang...@intel.com
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index
From: Peter Rosin p...@axentia.se
This was overlooked in the late change to remove the I2S padding bits
from S24_LE mode. The patch also limits S32_LE mode to 384kHz, the
maximum according to the datasheets.
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 39
From: Peter Rosin p...@axentia.se
These fixups can either be squashed in with 5/7 from the Clock master mode
series, or they can be added on top of the current topic/pcm512x. Sorry for
the trouble.
I can squash them, and resend the Clock master modes series if that helps.
Let me know how you'd
From: Peter Rosin p...@axentia.se
The DSP programs are listed out of order.
Signed-off-by: Peter Rosin p...@axentia.se
Cc: sta...@vger.kernel.org
---
sound/soc/codecs/pcm512x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs
From: Peter Rosin p...@axentia.se
The DDRSDR controller (on the ATSAMA5D31) fails miserably to put LPDDR1
memories in self-refresh. Force the controller to think it has DDR2
memories during the self-refresh period, as the DDR2 self-refresh spec
is equivalent to LPDDR1, and is correctly
From: Peter Rosin p...@axentia.se
Add helper functions to allow drivers to specify several disjoint
ranges for a variable. In particular, there is a codec (PCM512x) that
has a hole in its supported range of rates, due to PLL and divider
restrictions.
Signed-off-by: Peter Rosin p...@axentia.se
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c |2 +-
sound/soc/codecs/pcm512x.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index
From: Peter Rosin p...@axentia.se
Use register field names from the seemingly compatible PCM5242 datasheet,
as the PCM512x and PCM514x datasheets are severly lacking.
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 452
From: Peter Rosin p...@axentia.se
Using the PLL in master mode requires using an external connection
between one of the GPIO pins (configured as PLL/4 output) and the
SCK pin. It also requires the external clock to be fed to some other
GPIO pin instead of the SCK pin.
This is described
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 2a50c58a2fb1..511d98b3afa4 100644
From: Peter Rosin p...@axentia.se
Hi!
This series implements BCLK master modes for the pcm512x driver. It has
only been tested with the pcm5142 chip, but they are from the same family
and should be compatible. I have mainly used the spec for the newer
pcm5242 chip (also from the same family
From: Peter Rosin p...@axentia.se
The PLL introduces jitter, which in turn introduces noice if used
to clock the DAC. Thus, avoid the PLL output, and use the PLL input
to drive the DAC clock, if possible.
This is described for the PCM5142/PCM5242 chips in the answers to the
forum post PCM5142
From: Peter Rosin p...@axentia.se
Signed-off-by: Peter Rosin p...@axentia.se
---
sound/soc/codecs/pcm512x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 355a8543c8b1..78dc3306d2f2 100644
--- a/sound/soc
From: Peter Rosin p...@axentia.se
When the SSC acts as BCK master, use a ratnum rule to limit
the rate instead of only doing the standard rates. When the SSC
acts as BCK slave, allow any BCK frequency up to the SSC master
clock, divided by either of 2, 3 or 6.
Put a cap at 384kHz. Who's /ever
Bo Shen wrote:
Hi Peter,
Hi!
On 02/04/2015 07:52 PM, Peter Rosin wrote:
From: Peter Rosin p...@axentia.se
When the SSC acts as BCK master, use a ratnum rule to limit the rate
instead of only doing the standard rates. When the SSC acts as BCK
slave, allow any BCK frequency up
Bo Shen wrote:
Hi Peter,
On 02/09/2015 03:35 PM, Peter Rosin wrote:
Bo Shen wrote:
Hi Peter,
Hi!
On 02/07/2015 06:51 PM, Peter Rosin wrote:
Mark Brown wrote:
On Wed, Feb 04, 2015 at 12:52:25PM +0100, Peter Rosin wrote:
One thing remains a bit unclear, and that is the 500ppm
Bo Shen wrote:
Hi Peter,
Hi!
On 02/09/2015 05:07 PM, Peter Rosin wrote:
Bo Shen wrote:
Hi Peter,
On 02/09/2015 04:09 PM, Peter Rosin wrote:
[Snip]
/*-*\
* DAI functions
@@ -200,6 +290,7
Bo Shen write:
Hi Peter,
Hi!
[Snip]
/*-*\
* DAI functions
@@ -200,6 +290,7 @@ static int atmel_ssc_startup(struct
snd_pcm_substream *substream,
struct atmel_ssc_info *ssc_p =
broken and never actually ran, we have been
using 16MHz pllin_rate, and I apparently never hit this code path.
Signed-off-by: Howard Mitchell h...@hmbedded.co.uk
Acked-by: Peter Rosin p...@axentia.se
Cheers,
Peter
---
sound/soc/codecs/pcm512x.c |4 ++--
1 file changed, 2 insertions(+), 2
Howard Mitchell wrote:
Currently the PLL Lock output signal is hardcoded to GPIO4. This
makes it seletable in the same way as pll-in and pll-out.
Oops, I never intended the plllock code the hit upstream. I thought
I had removed that testing code and was very surprised to see it, that
was an odd
Howard Mitchell wrote:
On 22/03/15 16:24, Mark Brown wrote:
On Fri, Mar 20, 2015 at 09:22:43PM +, Howard Mitchell wrote:
+ if (pcm512x-pll_lock) {
+if (of_property_read_u32(np, pll-lock, val) = 0) {
+if (val 6) {
+
From: Peter Rosin p...@axentia.se
When using non-standard rates, a relatively small amount of overclocking
can make a big difference to a number of cases.
- Not all rates are possible to achieve with the PLL, due to divider
restrictions.
- The higher oversampling rates that can be used
From: Peter Rosin p...@axentia.se
On 2015-02-23 15:31, Mark Brown wrote:
On Sun, Feb 22, 2015 at 12:24:12AM +, Peter Rosin wrote:
...but I'm not sure everybody agrees that overclocking games should
be allowed by any and all users?
I don't see why not, ASoC controls are already way
Mark Brown wrote:
On Mon, Feb 16, 2015 at 10:02:48PM +0100, Peter Rosin wrote:
From: Peter Rosin p...@axentia.se
When using non-standard rates, a relatively small amount of
overclocking can make a big difference to a number of cases.
This is all basically fine but I'm wondering why
Howard Mitchell wrote:
Currently GPIO4 is hardcoded to output the pll-lock signal.
Unfortunately this is after the pll-out GPIO is configured which
is selectable in the device tree. Therefore it is not possible to
use GPIO4 for pll-out. Therefore this patch removes the
configuration of GPIO4.
From: Peter Rosin p...@axentia.se
When the SSC acts as BCK master, use a ratnum rule to limit
the rate instead of only doing the standard rates. When the SSC
acts as BCK slave, allow any BCK frequency up to within 500ppm
of the SSC master clock, possibly divided by 2, 3 or 6.
Put a cap at 384kHz
diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c
index f07a618..058fb4b 100644
--- a/drivers/net/wireless/adm8211.c
+++ b/drivers/net/wireless/adm8211.c
@@ -1098,14 +1098,18 @@ static void adm8211_hw_init(struct ieee80211_hw *dev)
Wei Yongjun wrote:
In case of error, the function devm_kzalloc() returns NULL not ERR_PTR().
The IS_ERR() test in the return value check should be replaced with NULL
test.
Acked-by: Peter Rosin p...@axentia.se
Thanks,
Peter
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On 2015-10-19 10:51, Ludovic Desroches wrote:
> Hi Peter,
>
> On Fri, Oct 16, 2015 at 11:08:42AM +0200, Peter Rosin wrote:
>> On 2015-10-16 01:47, Peter Rosin wrote:
>>> On 2015-10-14 07:43, Ludovic Desroches wrote:
>>>> On Tue, Oct 13, 2015 at 08:01:34PM +02
On 2015-10-14 07:43, Ludovic Desroches wrote:
> On Tue, Oct 13, 2015 at 08:01:34PM +0200, Peter Rosin wrote:
>> On 2015-10-13 18:47, Cyrille Pitchen wrote:
>>> Le 13/10/2015 17:19, Peter Rosin a écrit :
>>>> On 2015-10-13 16:21, Ludovic Desroches wrote:
>>>
On 2015-10-16 01:47, Peter Rosin wrote:
> On 2015-10-14 07:43, Ludovic Desroches wrote:
>> On Tue, Oct 13, 2015 at 08:01:34PM +0200, Peter Rosin wrote:
>>> On 2015-10-13 18:47, Cyrille Pitchen wrote:
>>>> Le 13/10/2015 17:19, Peter Rosin a écrit :
>>>>>
On 2015-10-20 15:27, Ludovic Desroches wrote:
> On Mon, Oct 19, 2015 at 12:49:03PM +0200, Peter Rosin wrote:
>> On 2015-10-19 10:51, Ludovic Desroches wrote:
>>> Hi Peter,
>>>
>>> On Fri, Oct 16, 2015 at 11:08:42AM +0200, Peter Rosin wrote:
>>
On 2015-10-21 09:21, Peter Rosin wrote:
> On 2015-10-20 15:27, Ludovic Desroches wrote:
>> On Mon, Oct 19, 2015 at 12:49:03PM +0200, Peter Rosin wrote:
>>> On 2015-10-19 10:51, Ludovic Desroches wrote:
>>>> Hi Peter,
>>>>
>>>> On Fr
On 2015-10-05 17:09, Peter Rosin wrote:
> But what trouble does the i2c bus driver see? Admittedly I only
> have a simple logic level bus viewer, and not a full-blown
> oscilloscope, so there might be something analogue going on?
> I don't think so though, those signals looked fine
On 2015-10-12 18:13, Cyrille Pitchen wrote:
> Le 12/10/2015 17:13, Peter Rosin a écrit :
>> On 2015-10-05 17:09, Peter Rosin wrote:
>>> But what trouble does the i2c bus driver see? Admittedly I only
>>> have a simple logic level bus viewer, and not a full-blown
>&
91
> kernel image. Adapted to linux-next.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitc...@atmel.com>
> Fixes: 93563a6a71bb ("i2c: at91: fix a race condition when using the DMA
> controller")
> Reported-by: Peter Rosin <p...@lysator.liu.se>
> Signed-o
On 2015-10-13 14:57, Nicolas Ferre wrote:
> Le 13/10/2015 12:38, Peter Rosin a écrit :
>> On 2015-10-12 18:13, Cyrille Pitchen wrote:
>>> Le 12/10/2015 17:13, Peter Rosin a écrit :
>>>> On 2015-10-05 17:09, Peter Rosin wrote:
>>>>> But what trouble d
On 2015-10-13 18:47, Cyrille Pitchen wrote:
> Le 13/10/2015 17:19, Peter Rosin a écrit :
>> On 2015-10-13 16:21, Ludovic Desroches wrote:
>>> From: Cyrille Pitchen <cyrille.pitc...@atmel.com>
>>>
>>> In some cases a NACK interrupt may be pending i
On 2015-10-03 01:05, Peter Rosin wrote:
> I looked around and found that if I revert
> a839ce663b3183209fdf7b1fc4796bfe2a4679c3
> "eeprom: at24: extend driver to allow writing via i2c_smbus_write_byte_data"
> eeprom writing starts working again.
>
> AFAICT, t
On 2015-10-03 01:05, Peter Rosin wrote:
> Hi!
>
> I recently upgraded from the atmel linux-3.18-at91 kernel to vanilla 4.2
> and everything seemed fine. Until I tried to write to the little eeprom
> chip. I then tried the linux-4.1-at91 kernel and that suffers too.
&g
Hi!
I recently upgraded from the atmel linux-3.18-at91 kernel to vanilla 4.2
and everything seemed fine. Until I tried to write to the little eeprom
chip. I then tried the linux-4.1-at91 kernel and that suffers too.
The symptoms are that it seems like writes get interrupted, and restarted
again
On 2015-09-27 17:50, Jonathan Cameron wrote:
> On 23/09/15 15:26, Peter Rosin wrote:
>> From: Peter Rosin <p...@axentia.se>
>>
>> Add support for Microchip digital potentiometers and rheostats
>> MCP4531, MCP4532, MCP4551, MCP4552
>> MCP4631,
From: Peter Rosin <p...@axentia.se>
Add support for Microchip digital potentiometers and rheostats
MCP4531, MCP4532, MCP4551, MCP4552
MCP4631, MCP4632, MCP4651, MCP4652
DEVICE Wipers Steps Resistor Opts (kOhm) i2c address
MCP4531 1 1295, 10, 50, 1000
From: Peter Rosin <p...@axentia.se>
This is the fifth attempt for a driver for these chips.
Thanks for review comments from Greg Kroah-Hartman, Crt Mori,
Daniel Baluta, Lars-Peter Clauson, Andreas Dannenberg, Peter
Meerwald and Jonathan Cameron. I think and hope I got it all sorted.
C
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