Switch to use ma_request_slave_channel_compat_reason() to request the DMA
channels. Only fall back to pio mode if the error code returned is not
-EPROBE_DEFER, otherwise return from the probe with the -EPROBE_DEFER.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Herbert Xu herb
Switch to use ma_request_slave_channel_compat_reason() to request the DMA
channels. Only fall back to pio mode if the error code returned is not
-EPROBE_DEFER, otherwise return from the probe with the -EPROBE_DEFER.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Ulf Hansson ulf.hans
Switch to use ma_request_slave_channel_compat_reason() to request the DMA
channels. In case of error, return the error code we received including
-EPROBE_DEFER
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/tty/serial/8250
Switch to use ma_request_slave_channel_compat_reason() to request the DMA
channel. Only fall back to polling mode if the error code returned is not
-EPROBE_DEFER, otherwise return from the probe with the -EPROBE_DEFER.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Herbert Xu herb
Switch to use ma_request_slave_channel_compat_reason() to request the DMA
channels. Only fall back to pio mode if the error code returned is not
-EPROBE_DEFER, otherwise return from the probe with the -EPROBE_DEFER.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Mark Brown broo
dmaengine provides a wrapper function to handle DT and non DT boots when
requesting DMA channel. Use that instead of checking for of_node in the
platform driver.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Mark Brown broo...@kernel.org
CC: Jarkko Nikula jarkko.nik...@bitmer.com
CC
Switch to use ma_request_slave_channel_compat_reason() to request the DMA
channels. Only fall back to pio mode if the error code returned is not
-EPROBE_DEFER, otherwise return from the probe with the -EPROBE_DEFER.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Herbert Xu herb
On 08/15/2015 05:31 AM, Vaishali Thakkar wrote:
Use resource managed function devm_snd_soc_register_component for
component registration instead of snd_soc_register_component.
Also, remove davinci_vcif_remove as it is now redundant.
Acked-by: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off
TPS77018DBVT is used to create 1.8V from avm_3v3_sw's 3.3V connected to
aic3106's DVDD.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7
The DVDD is supplied via TPS77018DBVT fixed regulator from evm_3v3
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off-by: Darren Etheridge detheri...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/dra72
The board uses tlv320aic3106 codec connected to McASP3. The master clock
for the codec and McASP3 is coming from ATL2.
McASP3 is the master on the I2S bus.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 113 +
1
The ABE related clocks should be configured via DT and not have it wired
inside of the kernel.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
Hi Tero,
the ABE PLL configuration can, and will be done for dra7xx in DT with the
assigned-clocks/rate/parent feature so no need to have
McASP3 is used by default on DRA7x based boards for audio.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 41 +++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm
,
Peter
---
Peter Ujfalusi (11):
ARM: OMAP: DRA7: hwmod: Add data for McASP3
ARM: DTS: dra7: Add McASP3 node
ARM: DTS: dra7-evm: Rename mmc2_3v3 supply to evm_3v3_sw
ARM: DTS: dra7-evm: Add fixed regulator to be used by aic3106's DVDD
ARM: DTS: dra7-evm: Enable pcf8575 (0x26 address) on i2c2
This GPIO expander is used for controlling various muxes on the board.
By default select audio functionality over VIN6 by setting the P1
(vin6_sel_s0) pin to low.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 14 ++
1 file changed, 14
The board uses tlv320aic3106 codec connected to McASP3. The master clock
for the codec and McASP3 is coming from ATL2.
McASP3 is the master on the I2S bus.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts | 114
1
Use the name for the supply as it is in the schematics since the same
supply is used for other peripherals than MMC2, like audio.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch
The DVDD is supplied via TPS77018DBVT fixed regulator from vdd_3v3
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx
The analog audio setup consists of:
McASP3 - tlv320aic3104 codec
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts | 87 +
1 file changed, 87 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch
The GPIO expander's p1 on i2c5 bus 0x26 address is used for selecting
between audio and VIN6 functionality. For VIN6 use an add on card is
needed while audio is present on the board itself.
Select the audio functionality over the VIN6 in the dts file.
Signed-off-by: Peter Ujfalusi peter.ujfal
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5d65db9ebc2b..07fa4ea5521a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch
On 08/03/2015 09:48 PM, Jarkko Nikula wrote:
It is well possible that some regression got introduced to TPA6130A2 I2C
communication over the years without nobody than you now notices. We
used to do QA back in Meego N900 days but that was pre 3.x kernels.
No major changes has been done to the
On 08/07/2015 11:00 PM, Sebastian Andrzej Siewior wrote:
-static void omap_dma_stop(struct omap_chan *c)
+static void omap_dma_drain_chan(struct omap_chan *c)
+{
+ int i;
+ uint32_t val;
+
+ /* Wait for sDMA FIFO to drain */
+ for (i = 0; ; i++) {
+ val =
On 08/11/2015 03:30 PM, Russell King - ARM Linux wrote:
On Tue, Aug 11, 2015 at 03:02:44PM +0300, Peter Ujfalusi wrote:
On 08/07/2015 11:00 PM, Sebastian Andrzej Siewior wrote:
+ /*
+* We do not allow DMA_MEM_TO_DEV transfers to be paused.
+* From the AM572x TRM, 16.1.4.18 Disabling
On 08/07/2015 11:41 AM, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used on the RX
side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
but the DMA controller
On 08/07/2015 01:36 PM, Sebastian Andrzej Siewior wrote:
On 08/07/2015 11:44 AM, Peter Ujfalusi wrote:
On 08/07/2015 11:41 AM, Sebastian Andrzej Siewior wrote:
This DMA driver is used by 8250-omap on DRA7-evm. There is one
requirement that is to pause a transfer. This is currently used
On 08/07/2015 11:00 PM, Sebastian Andrzej Siewior wrote:
The 8250-omap driver requires the DMA-engine driver to support the pause
command in order to properly turn off programmed RX transfer before the
driver stars manually reading from the FIFO.
The lacking support of the requirement has been
From: Misael Lopez Cruz misael.lo...@ti.com
In preparation for supporting multiple DMA crossbar instances,
make the idr xbar instance specific.
Signed-off-by: Misael Lopez Cruz misael.lo...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
drivers/dma/ti-dma-crossbar.c | 9
instance-specific
Peter Ujfalusi (1):
dmaengine: ti-dma-crossbar: Add support for eDMA
drivers/dma/ti-dma-crossbar.c | 34 +-
1 file changed, 29 insertions(+), 5 deletions(-)
--
2.4.5
--
To unsubscribe from this list: send the line unsubscribe linux-kernel
The crossbar for eDMA works exactly the same way as sDMA, but sDMA
requires an offset of 1, while no offset is needed for eDMA.
Based on the patch from Misael Lopez Cruz misael.lo...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
CC: Misael Lopez Cruz misael.lo...@ti.com
---
drivers
Hi Paul,
On 10/14/2015 12:23 PM, Peter Ujfalusi wrote:
> Hi Paul,
>
> This is the followup series for the hwmod changes needed to get audio working
> on DRA7xx family based boards.
> The DTS patches has been applied by Tony from the original series:
> http://www.spinics.ne
(ARM, DSP,
etc) and since ARM/Linux is the master we need to know which channels are used
by other cores. Also we need to mask out channels used for memcpy from the
events we use for HW triggers.
Regards,
Peter
---
Peter Ujfalusi (3):
dmaengine: ti-dma-crossbar: dra7: Use bitops instead of idr
Allow the crossbar driver to be used with the eDMA node with non legacy
binding.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/ti-dma-crossbar.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c
can be shared with DSP in which case the crossbar driver should also
avoid mapping xbar events to DSP used event numbers (or channels).
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
.../devicetree/bindings/dma/ti-dma-crossbar.txt| 6 +++
drivers/dma/ti-dma-cros
The use of idr was nice, but it was a bit heavy and we did not need the
features it provides. Using simple bitmap to track allocated DMA channels
is adequate here and it will be easier to add support for reserving
channels later on.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.
sed
by a client and the client is not using completion, but polling for the end of
the transfer.
Regards,
Peter
---
Peter Ujfalusi (4):
dmaengine: omap-dma: Correct status reporting for memcpy
dmaengine: omap-dma: Clean up the prep_slave_sg sg list walk code
dmaengine: omap-dma: Remove t
During mem copy both src and dst position moves at the same pace. Check the
dst position for progress reporting.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
Tested-by: Tomi Valkeinen <tomi.valkei...@ti.com>
Signed-off-by: Jyri Sarha <jsa...@ti.com>
---
drivers/dma/om
The for_each_sg() macro's last parameter is inteded to be used as counter.
We can use 'i' instead of 'j' within the loop for indexes.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/omap-dma.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff
)
dmatest: dma0chan16-copy: summary 5000 tests, 0 failures 199 iops 638 KB/s (0)
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/omap-dma.c | 59 ++
1 file changed, 2 insertions(+), 57 deletions(-)
diff --git a/drivers/dm
and
will not mark the transaction as done.
Check the channel enable bit in the CCR when the status is queried and if
the channel is no longer active, we call the omap_dma_callback() to handle
the transfer completion.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/omap-dma.c | 6 +++
the coming weeks.
Thanks,
Péter
>
> On Tuesday 26 May 2015 16:26:07 Peter Ujfalusi wrote:
>> Switch to use ma_request_slave_channel_compat_reason() to request the DMA
>> channel. Only fall back to pio mode if the error code returned is not
>> -EPROBE_DEFER, otherwise retur
rx_mask as 0) for output-only codecs to control the TDM slot(s)
> the McASP serial port uses for transmit. Before that, this scenario
> would incorrectly rely on the rx_mask for this.
>
> Signed-off-by: Andreas Dannenberg <dannenb...@ti.com>
Acked-by: Peter Ujfalusi <peter.ujf
the module's address space.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
Acked-by: Paul Walmsley <p...@pwsan.com>
Tested-by: Felipe Balbi <ba...@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 66 ++--
arch/arm/mach-omap2/omap_hwmod.
McASP3 is used by default on DRA7x based boards for audio.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
Acked-by: Paul Walmsley <p...@pwsan.com>
Tested-by: Felipe Balbi <ba...@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 56 +++
McASP node needs to list all mandatory clocks: gfclk and ahclkx
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
Tested-by: Felipe Balbi <ba...@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7
.
All in all, the McASP found in DRA7 needs all clocks to be enabled.
To satisfy this I have introduced a new flag to hwmod, which means that the
listed optional clocks need to be handled alongside with the fclk clock.
Regards,
Peter
---
Peter Ujfalusi (3):
ARM: DTS: dra7: Fix McASP3 node
.
Convert the driver to use dma_pool_* for managing the list of control
blocks for the transfer.
Fixes: f93178291712 ("dmaengine: bcm2835-dma: Fix memory leak when stopping a
running transfer")
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
Hi,
It was brought
Tony,
On 10/30/2015 06:11 PM, Paul Walmsley wrote:
> Hi Péter
>
> On Fri, 30 Oct 2015, Peter Ujfalusi wrote:
>
>> Changes since v2:
>> - DTS patch added which is needed because of the clock handling changes
>>
>> Felip Balbi reported that linux-next is
On 11/06/2015 11:53 PM, Rob Herring wrote:
> On Fri, Oct 30, 2015 at 10:00:37AM +0200, Peter Ujfalusi wrote:
>> In eDMA the events are directly mapped to a DMA channel (for example DMA
>> event 14 can only be handled by DMA channel 14). If the memcpy is enabled
Vinod,
On 10/29/2015 10:28 AM, Peter Ujfalusi wrote:
> Hi,
>
> This series depends on the eDMA work I have done, which has been now applied:
> https://lkml.org/lkml/2015/10/16/64
>
> DRA7 family of chips have both sDMA and eDMA. Currently only sDMA can be used
> becasue
can be shared with DSP in which case the crossbar driver should also
avoid mapping xbar events to DSP used event numbers (or channels).
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
.../devicetree/bindings/dma/ti-dma-crossbar.txt| 6 +++
drivers/dma/ti-dma-cros
out channels used for memcpy from the
events we use for HW triggers.
Regards,
Peter
---
Peter Ujfalusi (3):
dmaengine: ti-dma-crossbar: dra7: Use bitops instead of idr
dmaengine: ti-dma-crossbar: dra7: Support for reserving DMA event
ranges
dmaengine: ti-dma-crossbar: dra7: Support
McASP3 is used by default on DRA7x based boards for audio.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 56 +++
1 file changed, 56 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
the module's address space.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 66 ++--
arch/arm/mach-omap2/omap_hwmod.h | 3 ++
2 files changed, 39 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach
McASP node needs to list all mandatory clocks: gfclk and ahclkx
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
to hwmod, which means that the
listed optional clocks need to be handled alongside with the fclk clock.
Regards,
Peter
---
Peter Ujfalusi (3):
ARM: DTS: dra7: Fix McASP3 node regarding to clocks
ARM: OMAP2+: hwmod: Add hwmod flag for HWMOD_OPT_CLKS_NEEDED
ARM: OMAP: DRA7: hwmod: Add data for McASP3
For the record...
On 10/29/2015 10:28 AM, Peter Ujfalusi wrote:
> The use of idr was nice, but it was a bit heavy and we did not need the
> features it provides. Using simple bitmap to track allocated DMA channels
> is adequate here and it will be easier to add support for reserving
&
Allow the crossbar driver to be used with the eDMA node with non legacy
binding.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/ti-dma-crossbar.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c
The use of idr was nice, but it was a bit heavy and we did not need the
features it provides. Using simple bitmap to track allocated DMA channels
is adequate here and it will be easier to add support for reserving
channels later on.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.
or remove
callbacks provided.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
Reported-by: Olof Johansson <o...@lixom.net>
---
Hi,
while it would have been possible to add the edma3-tptc compatible to be handled
by the edma-tpcc driver (and when the device is tptc, do nothing) i
Vinod,
On 11/02/2015 05:40 PM, Vinod Koul wrote:
> On Mon, Nov 02, 2015 at 02:13:01PM +0200, Peter Ujfalusi wrote:
>> Vinod,
>>
>> On 11/02/2015 12:04 PM, Vinod Koul wrote:
>>> On Mon, Nov 02, 2015 at 01:21:19AM -0800, Olof Johansson wrote:
>>>> Hi,
of_dma_request_slave_channel should return either pointer for valid
dma_chan or ERR_PTR() error code, NULL is not expected to be returned.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
include/linux/of_dma.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/i
The driver will not probe without valid DMA channels so no need to check
if they are valid when the module is removed.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
CC: Ulf Hansson <ulf.hans...@linaro.org>
---
drivers/mmc/host/omap_hsmmc.c | 6 ++
1 file changed, 2 inse
On 11/04/2015 10:37 AM, Vinod Koul wrote:
> On Mon, Nov 02, 2015 at 05:46:05PM +0200, Peter Ujfalusi wrote:
>>> Okay I have reverted the two and applied the edma patch sent, can you please
>>> verify topic/edma_fix before I merge it and send my PULL request.
>>
>>
On 11/04/2015 10:46 AM, Arnd Bergmann wrote:
> On Wednesday 04 November 2015 09:42:35 Peter Ujfalusi wrote:
>> On 11/03/2015 04:00 PM, Arnd Bergmann wrote:
>>> During the edma rework, a build error was introduced for the
>>> case that CONFIG_OF is disabled:
>>>
On 11/03/2015 04:00 PM, Arnd Bergmann wrote:
> During the edma rework, a build error was introduced for the
> case that CONFIG_OF is disabled:
>
> drivers/built-in.o: In function `edma_tc_set_pm_state':
> :(.text+0x43bf0): undefined reference to `of_find_device_by_node'
>
> As the
, the HWMOD_INIT_NO_IDLE need to be
added.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
Vinod, Olof,
This patch somehow got lost in my working branch. It was mixed within the
patches
I will have for 4.5 while it should have been within the new eDMA3 binding
series..
Regards,
Peter
ar
On 11/02/2015 12:24 PM, Vinod Koul wrote:
> On Mon, Nov 02, 2015 at 12:11:00PM +0200, Peter Ujfalusi wrote:
>> In Linux we do not have driver for TPTCs of eDMA3 since there is no need to
>> do any configuration within TPTC for the eDMA3 to be operational. All
>> configur
t;
>
> Thanks,
>
> -Olof
>
> On Fri, Oct 16, 2015 at 12:18 AM, Peter Ujfalusi <peter.ujfal...@ti.com>
> wrote:
>> Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3 and
>> enable the DMA even crossbar with ti,am335x-edma-crossbar.
>&
Vinod,
On 11/02/2015 12:04 PM, Vinod Koul wrote:
> On Mon, Nov 02, 2015 at 01:21:19AM -0800, Olof Johansson wrote:
>> Hi,
>>
>> 1) This seems to have broken BBB in -next for me, bisected down to this
>> patch.
>>
>> For bootlog:
>>
On 11/02/2015 12:23 PM, Peter Ujfalusi wrote:
> On 11/02/2015 12:24 PM, Vinod Koul wrote:
>> On Mon, Nov 02, 2015 at 12:11:00PM +0200, Peter Ujfalusi wrote:
>>> In Linux we do not have driver for TPTCs of eDMA3 since there is no need to
>>> do any configuratio
On 10/14/2015 05:48 PM, Vinod Koul wrote:
> On Wed, Oct 14, 2015 at 04:12:21PM +0300, Peter Ujfalusi wrote:
>> The DMA event crossbar on AM33xx/AM43xx is different from the one found in
>> DRA7x family.
>> Instead of a single event crossbar it has 64 identical mux attached
On 10/14/2015 05:41 PM, Vinod Koul wrote:
> On Wed, Oct 14, 2015 at 04:12:13PM +0300, Peter Ujfalusi wrote:
>> @@ -1320,41 +1317,92 @@ static struct dma_async_tx_descriptor
>> *edma_prep_dma_memcpy(
>> struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
>>
On 10/15/2015 01:48 PM, John Ogness wrote:
> Currently drivers are limited to 19 slots for cyclic transfers.
> However, if the DMA burst size is the same as the period size,
> the period size can be changed to the full buffer size and
> intermediate interrupts activated. Since intermediate
On 10/15/2015 01:46 PM, John Ogness wrote:
> When retrieving the residue value for cyclic transfers, the DST
> field of the active PaRAM is read. However, the AM335x Technical
> Reference Manual states:
>
> 11.3.3.6 Parameter Set Updates
>
> After the TR is read from the PaRAM (and is in the
On 10/14/2015 05:31 PM, Vinod Koul wrote:
> On Wed, Oct 14, 2015 at 02:42:42PM +0300, Peter Ujfalusi wrote:
>> Hi,
>>
>> Cover letter:
>>
>> with this series the edma two driver setup will be changed to have only one
>> driver to support eDMA3. The legacy
Tony,
On 10/12/2015 11:57 PM, Tony Lindgren wrote:
> * Tony Lindgren <t...@atomide.com> [150914 09:32]:
>> * Peter Ujfalusi <peter.ujfal...@ti.com> [150914 01:54]:
>>> Hi Tony,
>>>
>>> On 08/24/2015 10:19 AM, Peter Ujfalusi wrote:
>>>
the module's address space.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 66 ++--
arch/arm/mach-omap2/omap_hwmod.h | 3 ++
2 files changed, 39 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach
in the HW w/o
any SW interaction.
All in all, the McASP found in DRA7 needs all clocks to be enabled.
To satisfy this I have introduced a new flag to hwmod, which means that the
listed optional clocks need to be handled alongside with the fclk clock.
Regards,
Peter
---
Peter Ujfalusi (2):
ARM
McASP3 is used by default on DRA7x based boards for audio.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 56 +++
1 file changed, 56 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
On 10/14/2015 01:27 PM, Vinod Koul wrote:
> On Thu, Sep 24, 2015 at 01:01:47PM +0300, Peter Ujfalusi wrote:
>> Hi,
>>
>> Cover letter:
>>
>> with this series the edma two driver setup will be changed to have only one
>> driver to support eDMA3. The legacy
On 10/14/2015 01:20 PM, Vinod Koul wrote:
> On Thu, Sep 24, 2015 at 01:02:07PM +0300, Peter Ujfalusi wrote:
>
>> +if (edesc->cyclic) {
>> +vchan_cyclic_callback(>vdesc);
>> +spin_unlock(>vchan.lock);
>> +return;
>&
On 10/14/2015 02:12 PM, Peter Ujfalusi wrote:
>>> + } else if (edma_read(ecc, EDMA_QEMR)) {
>>> + dev_dbg(ecc->dev, "QEMR %02x\n",
>>> + edma_read(ecc, EDMA_QEMR));
>
be assigned to any TC (to set priority)
- PaRAM slots can be reserved for other cores to use
- Dynamic power management for CC and TCs, if only TC0 is used all other TC
can be powered down for example
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
Documentation/devicetree/bindings/
with the old binding it was not possible for a driver
to know which channel is allowed to be used as non HW triggered channel.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
arch/arm/boot/dts/am4372.dtsi | 82 -
arch/arm/boot/dts/am437x-gp-e
line. If different
mux is selected, then the selected event is going to be routed to the given
eDMA event.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
.../devicetree/bindings/dma/ti-dma-crossbar.txt| 15 +-
drivers/dma/ti-dma-crossbar.c
Instead of nesting functions just merge them since the resulting function
is still small and readable.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/dma/ed
with the old binding it was not possible for a driver
to know which channel is allowed to be used as non HW triggered channel.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
arch/arm/boot/dts/am335x-evm.dts| 9 +---
arch/arm/boot/dts/am335x-pepper.dts | 11 +
arch/arm/bo
Query the number of qDMA channels from CCCFG register.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index eaf1f9e4bde0..ea851ab05c8e 100644
--- a/drivers/dma/
edma_assign_channel_eventq() is a wrapper around edma_map_dmach_to_queue()
We can merge the content of the later so we will have only one function
to be used for mapping channels to given eventq
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.
the remaining data.
According to tests this patch increases the throughput of memcpy from
~3MB/s to 15MB/s
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.c | 96 ++
1 file changed, 75 insertions(+), 21 del
The channel/slot reservation is not supported when booted with DT so there
is not need to allocate memory.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
maintaining this (and other patches) in my linux-next-wip branch if someone
wants to try it out w/o needing to hunt for patches:
https://github.com/omap-audio/linux-audio.git peter/linux-next-wip
Regards,
Peter
---
Peter Ujfalusi (14):
dmaengine: edma: Remove alignment constraint for memcpy
Move all code under one function to do the dma device and eDMA channel
related setup so they are not scattered around the driver.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.c | 79 +-
1 file chang
These inline functions are designed to modify parts of the PaRAM in eDMA.
Change the names accordingly.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/ed
the driver.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.c | 396 +
1 file changed, 123 insertions(+), 273 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index c0165e3d3396..a64befecf477
Since the crossbar is needed for eDMA when it is used on OMAP like
platforms (am335x/am437x and later DRA7xx), select the crossbar to be built
if ARCH_OMAP is set.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
Despite the claim by the original commit adding the memcpy
support, eDMA does not have constraint on the alignment of src, dst
or length in increment mode.
Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
---
drivers/dma/edma.c | 13 ++---
1 file changed, 6 insertions
On 10/16/2015 01:26 PM, John Ogness wrote:
> When retrieving the residue value for cyclic transfers, the
> SRC/DST fields of the active PaRAM are read. However, the AM335x
> Technical Reference Manual states:
>
> 11.3.3.6 Parameter Set Updates
>
> After the TR is read from the PaRAM (and is
y active if more than 19 slots are needed
> and the burst size matches the period size.
Acked-by: Peter Ujfalusi <peter.ujfal...@ti.com>
> Signed-off-by: John Ogness <john.ogn...@linutronix.de>
> ---
> v1-v2 changes
> . rebased for next-20151016
>
> drivers/dm
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