DT-enabled Dove will move over from ARCH_DOVE in mach-dove to MACH_DOVE in
mach-mvebu. As non-DT ARCH_DOVE will stay to rot for a while, add a new
DT-only MACH_DOVE Kconfig.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Rui, Eduardo,
Mark Brown requested to take
With all the DT support preparation done, we are able to move Dove
to MVEBU easily. Legacy non-DT mach-dove is left untouched to rot
for a while before removal.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v1-v2:
- just rename CONFIG_ARCH_DOVE
On 03/01/2014 02:38 PM, Kishon Vijay Abraham I wrote:
On Saturday 01 March 2014 02:03 PM, Sebastian Hesselbarth wrote:
DT-enabled Dove will move over from ARCH_DOVE in mach-dove to
MACH_DOVE in
mach-mvebu. As non-DT ARCH_DOVE will stay to rot for a while, add a new
DT-only MACH_DOVE Kconfig
On 03/04/2014 05:03 AM, Mark Brown wrote:
On Sat, Mar 01, 2014 at 09:33:17AM +0100, Sebastian Hesselbarth wrote:
DT-enabled Dove will move over from ARCH_DOVE in mach-dove to MACH_DOVE in
mach-mvebu. As non-DT ARCH_DOVE will stay to rot for a while, add a new
DT-only MACH_DOVE Kconfig
On 03/04/2014 10:26 AM, Andrew Lunn wrote:
I could have sworn this was discussed with this particular patchset, but
I'm unable to find the conversation in my archives. Neither during the
patch submission process, nor the (long) pull request thread.
Perhaps it was an irc conversation? Andrew,
On 03/04/2014 02:53 PM, Jason Cooper wrote:
On Tue, Mar 04, 2014 at 12:11:36PM +, Russell King - ARM Linux wrote:
On Tue, Mar 04, 2014 at 11:39:43AM +0100, Sebastian Hesselbarth wrote:
On 03/04/2014 10:26 AM, Andrew Lunn wrote:
I could have sworn this was discussed with this particular
documentation now.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Cc: Russell King li
will update the driver to make use of it.
The last patch is optional and Linus Walleij can reject it, if he is already
done for v3.15.
[1] https://lkml.org/lkml/2014/3/3/326
Sebastian Hesselbarth (3):
ARM: dove: drop pinctrl PMU reg property
devicetree: bindings: drop pinctrl PMU reg
Pinctrl will WARN on missing DT resources, which is a little bit too
noisy. Use dev_warn with FW_BUG instead.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King li...@arm.linux.org.uk
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc
. The driver will derive the registers from existing
reg properties.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc
.
Therefore, this adds code and documentation for a sysfs attribute to
allow/deny PHYs to be suspended on a per-PHY basis. Disabling that
attribute prevents PHYs from being suspended when entering halted state.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Reported-by: Andrew
On 03/10/2014 12:12 AM, David Miller wrote:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Date: Fri, 7 Mar 2014 12:34:52 +0100
commit 1211ce53077164e0d34641d0ca5fb4d4a7574498
(net: phy: resume/suspend PHYs on attach/detach)
introduced a feature to suspend PHYs when entering
On 03/10/2014 01:30 AM, David Miller wrote:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Date: Mon, 10 Mar 2014 00:25:24 +0100
There is no way to determine if a bootloader is broken or not. The
sysfs knob allows to provide a use case based decision. Of course,
we can invent some
On 03/10/2014 01:41 AM, David Miller wrote:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Date: Mon, 10 Mar 2014 01:37:32 +0100
The mechanism is manual, no automatic way to determine it.
We recognize BIOS and ACPI bugs and work around them, by looking at
version information
ethtool_wolinfo
regardless of .get_wol callback availability.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: David Miller da...@davemloft.net
Cc: Florian Fainelli f.faine...@gmail.com
Cc: net...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel
On 03/10/2014 03:40 AM, David Miller wrote:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Date: Mon, 10 Mar 2014 01:53:33 +0100
On 03/10/2014 01:41 AM, David Miller wrote:
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Date: Mon, 10 Mar 2014 01:37:32 +0100
On 03/10/2014 02:51 AM, Ben Hutchings wrote:
On Mon, 2014-03-10 at 02:01 +0100, Sebastian Hesselbarth wrote:
phy_ethtool_get_wol is a helper to get current WOL settings from
a phy device. When using this helper on a PHY without .get_wol
callback, struct ethtool_wolinfo is never set-up correctly
With phy_ethtool_get_wol now clearing struct ethtool_wolinfo, we can
simplify routines calling it.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v1-v2:
- initial
Cc: David Miller da...@davemloft.net
Cc: Florian Fainelli f.faine...@gmail.com
Cc: net
regardless of
.get_wol callback availability.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v1-v2:
- clear whole struct ethtool_wolinfo
- check for non-NULL phy_device
Cc: David Miller da...@davemloft.net
Cc: Florian Fainelli f.faine...@gmail.com
Cc: net
also added two cleanup patches for current users of
phy_ethtool_get_wol. Those two patches are also based on v3.14-rc1 but
aren't really part of the fix. They can wait for v3.15 and I'll rebase
on request.
[1] https://lkml.org/lkml/2014/3/9/169
Sebastian Hesselbarth (3):
net: phy: fix
With phy_ethtool_get_wol now clearing struct ethtool_wolinfo, we can
simplify routines calling it.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v1-v2:
- initial
Cc: David Miller da...@davemloft.net
Cc: Florian Fainelli f.faine...@gmail.com
Cc: net
On 03/11/2014 12:17 AM, Ben Hutchings wrote:
On Mon, 2014-03-10 at 10:49 +, Sebastian Hesselbarth wrote:
On 03/10/2014 02:51 AM, Ben Hutchings wrote:
On Mon, 2014-03-10 at 02:01 +0100, Sebastian Hesselbarth wrote:
phy_ethtool_get_wol is a helper to get current WOL settings from
a phy
ethtool_wolinfo
regardless of .get_wol callback availability.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Reviewed-by: Florian Fainelli f.faine...@gmail.com
---
Changelog:
v1-v2:
- clear whole struct ethtool_wolinfo
- check for non-NULL phy_device
v2-v3:
- only clear
On 01/11/2014 07:14 PM, Russell King - ARM Linux wrote:
On Thu, Jan 09, 2014 at 12:04:12PM +0100, Jean-Francois Moine wrote:
@@ -1250,6 +1311,39 @@ tda998x_encoder_init(struct i2c_client *client,
priv-vip_cntrl_2 = video;
}
+ /* install the optional HDMI connect
On 01/12/2014 07:51 PM, Jean-Francois Moine wrote:
On Sat, 11 Jan 2014 19:35:21 +0100
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote:
At least for the DT part, I'd suggest to not ask for interrupt directly
but use a proper gpios property. The can of course be converted to
priv
Feb 2014 16:59:23 +0100, Sebastian Hesselbarth wrote:
Also, in the meantime, pinctrl driver stubs for new Armada 375/28x have
been posted [3]. Before any of this patches move to a stable branch, I
plan to send an updated version comprising the required patches for the
new SoCs. As the new driver
On 02/13/14 17:59, Thomas Petazzoni wrote:
On Thu, 13 Feb 2014 17:41:02 +0100, Sebastian Hesselbarth wrote:
Thanks again for working on this! I have boot tested this successfully
on an Armada XP platform, and it seems to behave normally, the debugfs
pinctrl contents make sense.
I guess
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks for generic mpp pins that will
be used later.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Jason Cooper ja
Dove has pins that can be switched between normal and pmu functions.
Rework pmu_mpp callbacks to reuse normal mpp callbacks.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn
Passing a NULL name for pin ranges will auto-generate standard names
for each pin. With common pinctrl driver now checking NULL name correctly,
consolidate mpp pins 0-15.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Jason
The way that mvebu pinctrl is designed, requesting mpp registers
in common pinctrl driver does not allow SoC specific drivers to
access this resource.
Move resource allocation in each SoC pinctrl driver and enable
already provided mpp_{set,get} callbacks.
Signed-off-by: Sebastian Hesselbarth
With every SoC always providing its own get/set callbacks, we can now
remove the generic ones, remove the obsolete base address, and always
use the provided callbacks.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Tested-by: Andrew Lunn and...@lunn.ch
---
Cc: Linus Walleij
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks for generic mpp pins that will
be used later.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Jason Cooper ja
they have been tested on Dove, compile-tested for the others,
and Andrew was so kind to give his Tested-by for common and Kirkwood
patches.
[1] http://www.spinics.net/lists/arm-kernel/msg303496.html
[2] lkml.org/lkml/2014/1/27/562
[3] http://www.spinics.net/lists/arm-kernel/msg306409.html
Sebastian
With the introduction of a global name buffer, we can now remove
the allocation and preparation of per-control name buffers.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Tested-by: Andrew Lunn and...@lunn.ch
---
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Jason Cooper
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks for generic mpp pins that will
be used later. While at it, also make use of globally defined MPP
macros.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Linus
This adds some defines for the common mpp reg layout to mvebu pinctrl
include.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Tested-by: Andrew Lunn and...@lunn.ch
---
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn
We want to get rid of passing register addresses to common pinctrl
driver, so provide set/get callbacks for generic mpp pins that will
be used later.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Tested-by: Andrew Lunn and...@lunn.ch
---
Cc: Linus Walleij linus.wall
The only valuable information a special callback can derive from
mvebu_mpp_ctrl passed to it, is the pin id. Instead of passing
the struct, pass the pid directly.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Tested-by: Andrew Lunn and...@lunn.ch
---
Cc: Linus Walleij
. The new buffer is then used while assigning
controls to pinctrl groups later.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Tested-by: Andrew Lunn and...@lunn.ch
---
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Jason Cooper ja...@lakedaemon.net
Cc: Andrew Lunn and...@lunn.ch
Cc
We treat unnamed controls as generic mvebu mpp register controls but
we identify them by not being special controls. Flip the logic and
use the name pointer as identification instead. While at it, add some
comments explaining the not so obvious treatment.
Signed-off-by: Sebastian Hesselbarth
On 03/18/2014 03:32 PM, Antoine Ténart wrote:
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now.
Signed-off-by: Antoine Ténart
On 03/18/2014 03:32 PM, Antoine Ténart wrote:
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/arm/Marvell/README | 5 +
Applied to berlin/soc.
Documentation/devicetree/bindings/arm/marvell,berlin.txt | 1 +
Squashed into
On 03/18/2014 03:32 PM, Antoine Ténart wrote:
Adds initial support for the Marvell BG2-Q DMP. The board has 2GB of
memory, an uart activated and what's initially supported by the Marvell
Armada 1500 pro dtsi.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
On 03/20/2014 09:58 AM, Jean-Francois Moine wrote:
The I2C address (reg) is required for the TDA998x driver to be loaded
and initialized.
Signed-off-by: Jean-Francois Moine moin...@free.fr
---
This patch applies to linux-next.
---
Documentation/devicetree/bindings/drm/i2c/tda998x.txt | 2 ++
On 03/20/2014 02:01 PM, Jean-Francois Moine wrote:
On Thu, 20 Mar 2014 13:32:24 +0100
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote:
+ - reg: I2C address - must be 0x70
TDA9983b datasheet says:
Bits A0 and A1 of the I2C-bus device address are externally selected
by pins A0
On 03/20/2014 02:52 PM, Jean-Francois Moine wrote:
On Thu, 20 Mar 2014 14:32:18 +0100
Sebastian Hesselbarth sebastian.hesselba...@gmail.com wrote:
Ok, I had another round of google'ing and found this:
http://hipstercircuits.com/wp-content/uploads/2013/05/TDA19988.pdf
There, the datasheet
This adds SMP support to Marvell Berlin2 SoCs. Secondary CPUs boot into
BootROM, wait for interrupt, and read SW generic register 1 with actual
boot code address. Synchronization by holding pen is copied from
plat-versatile and mach-prima2.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba
This adds scu and general purpose registers device nodes required for
SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
address from general purpose (SW generic) register 1.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Rob Herring robh
, and BG2CD (which is UP). I expect the
Free-Electrons guys to test on BG2Q.
There is a branch based on v3.14-rc1 and latest BG2Q DTs for the
lucky ones who are able to boot unsigned images at
https://github.com/shesselba/linux-berlin.git topic/smp-bg2-bg2q
Sebastian
Sebastian Hesselbarth (2):
ARM
On 03/21/2014 12:43 PM, Alexandre Belloni wrote:
Alexandre,
Thanks for starting this! I'll start with the most obvious
things first and have a closer look on it later.
Missing commit description here.
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
On 03/21/2014 12:43 PM, Alexandre Belloni wrote:
This also moves the clocks from the clocks container node to the root.
Same comments as for patch 4/5.
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
arch/arm/boot/dts/berlin2.dtsi | 56
On 03/21/2014 12:43 PM, Alexandre Belloni wrote:
This also moves the clocks from the clocks container node to the root.
Please leave a word on the original intention of the patch here, too.
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
On 03/21/2014 12:43 PM, Alexandre Belloni wrote:
Cc: devicet...@vger.kernel.org
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
.../devicetree/bindings/clock/berlin-clock.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644
On 03/21/2014 01:17 PM, Alexandre Belloni wrote:
On 21/03/2014 at 13:11:29 +0100, Sebastian Hesselbarth wrote :
On 03/21/2014 12:43 PM, Alexandre Belloni wrote:
Alexandre,
Thanks for starting this! I'll start with the most obvious
things first and have a closer look on it later.
I
On 03/21/2014 12:43 PM, Alexandre Belloni wrote:
This drivers allows to provide DT clocks for the cpu and system PLLs found on
Marvell Berlin SoCs.
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
drivers/clk/Makefile | 1 +
drivers/clk/berlin/Makefile
On 03/21/2014 11:55 AM, Jean-Francois Moine wrote:
The tda998x driver accepts only 3 chips from the TDA998x family.
This patch changes the driver compatible strings to these chips.
Jean-Francois,
be careful with building a DT binding from a Linux driver. Although
we constantly struggle to
On 03/21/2014 02:39 PM, Rob Herring wrote:
On Tue, Mar 18, 2014 at 4:56 PM, Pantelis Antoniou
pantelis.anton...@konsulko.com wrote:
Add a runtime interface to using configfs for generic device tree overlay
usage.
A device-tree configfs entry is created in /config/device-tree/overlays
To
On 03/21/2014 04:45 PM, Alexandre Belloni wrote:
[all commentis I agree on are snipped]
:)
On 21/03/2014 at 13:49:32 +0100, Sebastian Hesselbarth wrote :
On 03/21/2014 12:43 PM, Alexandre Belloni wrote:
obj-y += pll.o
obj-$(CONFIG_MACH_BERLIN_BG2) += pll-berlin2.o
obj
On 03/21/2014 04:56 PM, Alexandre Belloni wrote:
On 21/03/2014 at 13:49:32 +0100, Sebastian Hesselbarth wrote :
On 03/21/2014 12:43 PM, Alexandre Belloni wrote:
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a367a9831717..4a2602737c27 100644
--- a/drivers/clk/Makefile
+++ b
On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
This drivers allows to provide DT clocks for the cpu and system PLLs found on
Marvell Berlin SoCs.
Alexandre,
as mentioned on IRC, I now had a closer look on it. Some minor
remarks below. Sorry, I didn't mention them earlier.
Signed-off-by:
On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
Document the device tree bindings for the PLLs found on the Marvell Berlin SoCs.
Cc: devicet...@vger.kernel.org
You forgot to add Mark Rutland's Reviewed-by. He didn't mentioned it
explicitly but his Otherwise this looks fine to me on v1, is as
On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
The Berlin BG2Q has two supported PLLs: CPU PLL and System PLL, add those to the
SoC device tree.
Note that support for the AVPLL is not yet available.
Above should not be part of the commit message, no need to resend.
I can fix it up.
On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
The Berlin BG2CD has two supported PLLs: CPU PLL and System PLL, add those to
the SoC device tree.
This also moves the remaining clocks from the clocks container node to the root.
Signed-off-by: Alexandre Belloni
On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
The Berlin BG2 has two supported PLLs: CPU PLL and System PLL, add those to the
SoC device tree.
This also moves the remaining clocks from the clocks container node to the root.
Signed-off-by: Alexandre Belloni
On 03/21/2014 08:39 PM, Alexandre Belloni wrote:
Now that we support Berlin BG2Q, select CONFIG_MACH_BERLIN_BG2Q so that we can
boot BG2Q based boards like the BG2Q DMP.
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
Applied to berlin/soc, Thanks!
---
On 03/21/2014 08:39 PM, Alexandre Belloni wrote:
Now that we start supporting the Marvell Berlin BG2Q, add a symbol allowing to
differentiate that SoC from the other SoCs of the Berlin family.
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
Applied to berlin/defconfig,
On 03/21/2014 11:22 PM, Alexandre Belloni wrote:
On 21/03/2014 at 22:22:33 +0100, Sebastian Hesselbarth wrote :
On 03/21/2014 09:08 PM, Alexandre Belloni wrote:
This drivers allows to provide DT clocks for the cpu and system PLLs found on
Marvell Berlin SoCs.
Alexandre,
as mentioned on IRC
by irq_alloc_domain_generic_chip.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Thomas Gleixner t...@linutronix.de
Cc: Russell King - ARM Linux li...@arm.linux.org.uk
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Rob Landley r...@landley.net
Cc: Arnd Bergmann
mask_cache pointer also needs to be initialized for domain generic
chips.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Thomas Gleixner t...@linutronix.de
Cc: Russell King - ARM Linux li...@arm.linux.org.uk
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring
Dove power management unit can mux some special functions to mpp0-15.
This patch adds support to set/get the current PMU function mapped
to the corresponding mpp pins. The device tree documentation is also
updated accordingly.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
that clk1 was 0 and it wasn't possible to enable it again (try also
manually with i2cset commands). Only power cycle helps.
Marek,
does the fix below also affect the behavior above, i.e. not causing
si5351 to hang?
Anyway, your fix looks very sane to me and you get my
Acked-by: Sebastian Hesselbarth
On 05/07/2013 10:14 AM, Marek Belisko wrote:
When rate is 0 powerdown clock output.
Signed-off-by: Marek Beliskomarek.beli...@streamunlimited.com
---
drivers/clk/clk-si5351.c | 32 +++-
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git
of_mdiobus_register creates a phy_device even if get_phy_device failed
to create it previously. This causes indefinite polling on non-existent
PHYs. This fix makes of_mdio_register rely on get_phy_device to
properly create the device or fail otherwise.
Signed-off-by: Sebastian Hesselbarth
@@
+/*
+ * Marvell Orion SoC timer handling.
+ *
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied
On 06/10/13 18:04, Daniel Lezcano wrote:
On 06/10/2013 11:35 AM, Sebastian Hesselbarth wrote:
This patch add a DT enabled driver for timers found on Marvell Orion SoCs
(Kirkwood, Dove, Orion5x, and Discovery Innovation). It installs a free-
running clocksource on timer0 and a clockevent source
On 06/10/13 18:44, Daniel Lezcano wrote:
On 06/10/2013 06:31 PM, Sebastian Hesselbarth wrote:
On 06/10/13 18:04, Daniel Lezcano wrote:
On 06/10/2013 11:35 AM, Sebastian Hesselbarth wrote:
This patch add a DT enabled driver for timers found on Marvell Orion
SoCs
(Kirkwood, Dove, Orion5x
instead of registering a new device.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: David Airlie airl...@linux.ie
Cc: Russell King - ARM Linux li...@arm.linux.org.uk
Cc: Darren Etheridge darren.etheri...@gmail.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: dri-de
This fixes the wrong sync generation and sync calculation. It has only
been tested for progressive modes. Sync timings for a bunch of modes
have also been verified with an oscilloscope near-end (TDA998x input)
and far-end (DVI receiver output).
Signed-off-by: Sebastian Hesselbarth
This fixes the wrong sync generation and sync calculation for progressive
and interlaced modes. Sync timings for a bunch of modes have also been verified
with an oscilloscope near-end (TDA998x input) and far-end (DVI receiver output).
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba
This fixes the wrong sync generation and sync calculation for progressive
and interlaced modes. Sync timings for a bunch of modes have also been verified
with an oscilloscope near-end (TDA998x input) and far-end (DVI receiver output).
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba
On 06/11/13 09:24, Daniel Vetter wrote:
On Mon, Jun 10, 2013 at 11:23:42PM +0200, Sebastian Hesselbarth wrote:
Current DRM slave encoder API conflicts with auto-registration of i2c client
when using DT probed clients. To allow DRM slave encoders passed by DT, this
patch adds a check
On 06/11/13 14:35, Ezequiel Garcia wrote:
On Thu, Jun 06, 2013 at 06:27:08PM +0200, Sebastian Hesselbarth wrote:
This patch set introduces DT-aware irqchip and clocksource drivers for
Marvell Orion SoCs (Kirkwood, Dove, Orion5x, MV78x00) and corresponding
patches for Dove and Kirkwood to enable
On 06/11/13 15:13, Thomas Gleixner wrote:
On Tue, 11 Jun 2013, Sebastian Hesselbarth wrote:
On 06/11/13 14:35, Ezequiel Garcia wrote:
With Thomas Gleixner's Review now only somebody has to take the irqchip
patch then all three drivers are queued for next release.
I can take it through tip
On 06/11/13 15:30, Thomas Gleixner wrote:
On Tue, 11 Jun 2013, Thomas Gleixner wrote:
On Thu, 6 Jun 2013, Sebastian Hesselbarth wrote:
This patch adds an irqchip driver for the main interrupt controller found
on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation
On 06/11/13 15:45, Thomas Gleixner wrote:
On Tue, 11 Jun 2013, Sebastian Hesselbarth wrote:
On 06/11/13 15:30, Thomas Gleixner wrote:
On Tue, 11 Jun 2013, Thomas Gleixner wrote:
On Thu, 6 Jun 2013, Sebastian Hesselbarth wrote:
This patch adds an irqchip driver for the main interrupt
On 06/11/13 16:13, Thomas Gleixner wrote:
On Tue, 11 Jun 2013, Sebastian Hesselbarth wrote:
On 06/11/13 15:45, Thomas Gleixner wrote:
But what about the bit in of that first irq in the cause register? If
it's set on entry you call generic_handle_irq() for that as well. So
if it's set you need
On 06/11/2013 05:10 PM, Francisco Jerez wrote:
Sebastian Hesselbarthsebastian.hesselba...@gmail.com writes:
- I think we could also drop the call to -set_config since presumably an
of-enabled driver grabbed any required info already from the dt.
[...]
I think this way we could still
The CPU used in Marvell Dove SoCs is a PJ4 Sheeva core. Using
CONFIG_CPU_PJ4 instead of CONFIG_CPU_V7 will enable iWMMXt
extensions on Dove.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Acked-by: Jason Cooper ja...@lakedaemon.net
Acked-by: Andrew Lunn and...@lunn.ch
This patch adds the device tree node for si5351 clock generator
and the corresponding oscillator connected to it. It also limits
i2c frequency to 100kHz as there are bus locks reported on higher
frequencies.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Russell King
With of_clk_provider stubs for CONFIG_OF not set, we can now also enable
clk-si5351 on those architectures.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Mike Turquette mturque...@linaro.org
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Andrew Morton a...@linux
clk-provider functions that
either do nothing or return appropriate values if CONFIG_OF is not set.
So, definition of these routines will always be available.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Suggested-by: Arnd Bergmann a...@arndb.de
---
Cc: Mike Turquette
by removing the dependency on CONFIG_OF.
The above approach has been suggested by Arnd Bergmann and replaces the
corresponding Kconfig patch for clk-si5351 posted earlier. It has been
compile tested with allmodconfig on x86_64 for post v3.9.
Sebastian Hesselbarth (2):
clk: add non CONFIG_OF routines
This patch adds an irqchip driver for the main interrupt controller found
on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
Corresponding device tree documentation is also added.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Note: This patch
.
Note: This patch set depends on irqchip driver for Orion SoCs patch.
Sebastian Hesselbarth (3):
ARM: dove: add DT parsing for legacy mv643xx_eth
ARM: dove: add DT parsing for legacy timer
ARM: dove: move DT boards to orion irqchip driver
arch/arm/boot/dts/dove.dtsi | 18 -
arch/arm
for mv643xx_eth.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Rob Landley r...@landley.net
Cc: Thomas Gleixner t...@linutronix.de
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann
With legacy devices mapping their irqs, we can now switch DT enabled
boards to orion irqchip driver.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Rob Landley r...@landley.net
Cc
timer.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
Cc: Grant Likely grant.lik...@linaro.org
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Rob Landley r...@landley.net
Cc: Thomas Gleixner t...@linutronix.de
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann
On 05/02/2013 08:25 PM, Sebastian Hesselbarth wrote:
This patch adds an irqchip driver for the main interrupt controller found
on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation).
Corresponding device tree documentation is also added.
Signed-off-by: Sebastian
On 05/02/13 20:45, Russell King - ARM Linux wrote:
On Thu, May 02, 2013 at 08:33:48PM +0200, Sebastian Hesselbarth wrote:
On 05/02/2013 08:25 PM, Sebastian Hesselbarth wrote:
This patch adds an irqchip driver for the main interrupt controller found
on Marvell Orion SoCs (Kirkwood, Dove
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