[PATCH 2/3] arm64: v8.3: Support for complex number instructions

ARM v8.3 adds support for new instructions to aid floating-point multiplication and addition of complex numbers. Expose the support via HWCAP and MRS emulation Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Documentation/arm64/cpu-feature-registers.txt | 2 ++ arch/arm64/i

[PATCH 0/3] arm64: Advertise ARMv8.3 features

Advertise the ARMv8.3 features for the applications via ELF HWCAPS and MRS emulation. Suzuki K Poulose (3): arm64: v8.3: Support for Javascript conversion instruction arm64: v8.3: Support for complex number instructions arm64: v8.3: Support for weaker release consistency Documentation

Re: [1/2] coresight: Disable the path only when the source is disabled

On 14/03/17 17:37, Mathieu Poirier wrote: Hi Suzuki, On 14 March 2017 at 11:31, Mathieu Poirier <mathieu.poir...@linaro.org> wrote: From: "Suzuki K. Poulose" <suzuki.poul...@arm.com> With a coresight tracing session, the components along the path from the source to s

Re: [v3 3/5] coresight: add support for debug module

On 13/03/17 16:56, Mathieu Poirier wrote: On Fri, Mar 10, 2017 at 02:29:53PM +, Suzuki K Poulose wrote: + + put_online_cpus(); + + if (!debug_count++) + atomic_notifier_chain_register(_notifier_list, + _notifier

Re: [2/2] coresight: Fix reference count for software sources

On 15/03/17 03:51, Chunyan Zhang wrote: Hi Suzuki, On 15 March 2017 at 02:06, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: On 14/03/17 17:40, Mathieu Poirier wrote: On 14 March 2017 at 11:32, Mathieu Poirier <mathieu.poir...@linaro.org> wrote: From: "Suzuki K. Poul

Re: [PATCH 13/17] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core

e. Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com> Mark. --- arch/arm64/kernel/cpu_errata.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index f6cc67e7626e..2be1d1c05303 100644 --- a/arch/arm64/kernel/

Re: [PATCH 03/17] arm64: Allow checking of a CPU-local erratum

with cpus_have_cap()'s behaviour, which includes errata already. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> This sounds sensible to me. Suzuki, any comments? Yes, this looks fine to me. Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com> Thanks, Mark. --- arch/

[PATCH] kvm: arm/arm64: Rework gpa callback handlers

reduce the number of iterations. Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm/kvm/mmu.c | 31 +-- 1 file changed, 13 insertions(+), 18

Re: [2/2] coresight: Fix reference count for software sources

On 16/03/17 12:13, Chunyan Zhang wrote: On 16 March 2017 at 00:00, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: On 15/03/17 03:51, Chunyan Zhang wrote: Btw, should we allow the user to turn on the STM from sysfs (echo 1 > $STM/enable_source) ? If enabling STM can not be al

Re: [PATCH 3/3] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

On 15/03/17 13:28, Marc Zyngier wrote: On 15/03/17 10:56, Christoffer Dall wrote: On Wed, Mar 15, 2017 at 09:39:26AM +, Marc Zyngier wrote: On 15/03/17 09:21, Christoffer Dall wrote: On Tue, Mar 14, 2017 at 02:52:34PM +, Suzuki K Poulose wrote: In kvm_free_stage2_pgd() we don't hold

Re: [PATCH v3] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

On 03/04/17 15:22, Mark Rutland wrote: Hi, On Mon, Apr 03, 2017 at 03:12:43PM +0100, Suzuki K Poulose wrote: In kvm_free_stage2_pgd() we don't hold the kvm->mmu_lock while calling unmap_stage2_range() on the entire memory range for the guest. This could cause problems with other callers (

[PATCH v3] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Mark Rutland <mark.rutl...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> [ Avoid vCPU starvation and lockup detector warnings ] Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulo

Re: [PATCH v3] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

Hi Christoffer, On 04/04/17 11:13, Christoffer Dall wrote: Hi Suzuki, On Mon, Apr 03, 2017 at 03:12:43PM +0100, Suzuki K Poulose wrote: In kvm_free_stage2_pgd() we don't hold the kvm->mmu_lock while calling unmap_stage2_range() on the entire memory range for the guest. This could ca

Re: [PATCH v6 6/8] coresight: add support for CPU debug module

On 19/04/17 15:28, Leo Yan wrote: Hi Suzuki, On Wed, Apr 19, 2017 at 02:23:04PM +0100, Suzuki K Poulose wrote: Hi Leo, This version looks good to me. I have two minor comments below. Thanks for reviewing. Will take the suggestions. Just check a bit for last comment. [...] +static int

Re: kvm/arm64: use-after-free in kvm_unmap_hva_handler/unmap_stage2_pmds

On 12/04/17 19:43, Marc Zyngier wrote: On 12/04/17 17:19, Andrey Konovalov wrote: Hi Andrey, Apparently this wasn't fixed, I've got this report again on linux-next-c4e7b35a3 (Apr 11), which includes 8b3405e34 "kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd". This looks like a different

Re: kvm/arm64: use-after-free in kvm_unmap_hva_handler/unmap_stage2_pmds

On Thu, Apr 13, 2017 at 10:17:54AM +0100, Suzuki K Poulose wrote: > On 12/04/17 19:43, Marc Zyngier wrote: > > On 12/04/17 17:19, Andrey Konovalov wrote: > > > > Hi Andrey, > > > > > Apparently this wasn't fixed, I've got this report again on > > >

Re: kvm/arm64: use-after-free in kvm_unmap_hva_handler/unmap_stage2_pmds

On 13/04/17 16:50, Suzuki K. Poulose wrote: On Thu, Apr 13, 2017 at 10:17:54AM +0100, Suzuki K Poulose wrote: On 12/04/17 19:43, Marc Zyngier wrote: On 12/04/17 17:19, Andrey Konovalov wrote: Please ignore the footer below, that was mistake from my side. -- 2.7.4 IMPORTANT NOTICE

Re: kvm/arm64: use-after-free in kvm_unmap_hva_handler/unmap_stage2_pmds

On Thu, Apr 13, 2017 at 04:50:46PM +0100, Suzuki K. Poulose wrote: > On Thu, Apr 13, 2017 at 10:17:54AM +0100, Suzuki K Poulose wrote: > > On 12/04/17 19:43, Marc Zyngier wrote: > > > On 12/04/17 17:19, Andrey Konovalov wrote: > > > > > > Hi Andrey, > > &g

Re: [PATCH v6 6/8] coresight: add support for CPU debug module

On 06/04/17 14:30, Leo Yan wrote: Coresight includes debug module and usually the module connects with CPU debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has description for related info in "Part H: External Debug". Chapter H7 "The Sample-based Profiling Extension"

Re: [v3 3/5] coresight: add support for debug module

On 03/03/17 06:00, Leo Yan wrote: Coresight includes debug module and usually the module connects with CPU debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has description for related info in "Part H: External Debug". Chapter H7 "The Sample-based Profiling Extension"

Re: [v3 2/5] coresight: refactor with function of_coresight_get_cpu

On 09/03/17 11:01, Suzuki K Poulose wrote: On 03/03/17 06:00, Leo Yan wrote: This is refactor to add function of_coresight_get_cpu(), so it's used to retrieve CPU id for coresight component. Finally can use it as a common function for multiple places. Suggested-by: Mathieu Poirier

[PATCH 0/2] coresight: Allow sharing of STM

This series fixes the coresight generic layer to handle the reference counting for the STM source properly, to allow multiple applications to share the STM. Without this series, the STM is disabled when the first user closes its connection, causing trace data losses. Suzuki K Poulose (2

[PATCH 2/2] coresight: Fix reference count for software sources

the actions when we detect that the source is enabled. This patch fixes the problem by adding the refcounting for software sources, even when they are enabled. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Reported-by: Robert Walker <robert.wal...@arm.com> Signed-off-by: Suzu

[PATCH 1/2] coresight: Disable the path only when the source is disabled

oir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 0c37356..34

Re: [v3 2/5] coresight: refactor with function of_coresight_get_cpu

: 8>-- [PATCH] coresight: of_coresight_get_cpu: Add missing of_node_put The of_coresight_get_cpu iterates over the possible CPU nodes to find a given cpu phandle. However it does not drop the reference to the node pointer returned by the of_get_cpu_node. Cc: Leo Yan <leo@linaro.org

Re: [v3 1/5] coresight: bindings for debug module

To be honest, coresight-debug sounds too generic and could be confusing with lot of the other components. To be precise, the area is for External Debug to a CPU. So "arm,coresight-cpu-debug" or even "arm,coresight-cpu-external-debug" sounds more appropriate to me. Suzuki

Re: kvm/arm64: use-after-free in kvm_unmap_hva_handler/unmap_stage2_pmds

ave caused a problem with an munmap of a memslot ? Lightly tested... commit fa75684dbf0fe845cf8403517d6e0c2c3344a544 Author: Suzuki K Poulose <suzuki.poul...@arm.com> Date: Tue Mar 14 10:26:54 2017 + kvm: arm: Fix locking for kvm_free_stage2_pgd In kvm_free_stage2_pgd()

Re: kvm/arm64: use-after-free in kvm_vm_ioctl/vmacache_update

On 13/03/17 09:58, Marc Zyngier wrote: On 10/03/17 18:37, Suzuki K Poulose wrote: On 10/03/17 15:50, Andrey Konovalov wrote: On Fri, Mar 10, 2017 at 2:38 PM, Andrey Konovalov <andreyk...@google.com> wrote: Hi, I've got the following error report while fuzzing the kernel with syz

[PATCH 3/3] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

on setup") Cc: sta...@vger.kernel.org # v3.10+ Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm/kvm/mmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ar

[PATCH 0/3] kvm: arm/arm64: Fixes for use after free problems

_sem in stage2_unmap_vm kvm: arm/arm64: Take mmap_sem in kvm_arch_prepare_memory_region Suzuki K Poulose (1): kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd arch/arm/kvm/mmu.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 2.7.4

[PATCH 1/3] kvm: arm/arm64: Take mmap_sem in stage2_unmap_vm

rnel.org # v3.19+ Cc: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm/kvm/mmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/kvm/mmu.c

[PATCH 2/3] kvm: arm/arm64: Take mmap_sem in kvm_arch_prepare_memory_region

vel <ard.biesheu...@linaro.org> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Eric Auger <eric.au...@rehat.com> Cc: sta...@vger.kernel.org # v3.18+ Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> [ Handle dirty page logging failure case ] Signed-off-by:

Re: [v3 3/5] coresight: add support for debug module

On 09/03/17 17:59, Leo Yan wrote: Hi Suziku, The problem is, it is not guaranteed that the EDPCSR_Hi, EDCIDSR & EDVIDSR are updated as a side effect of a memory mapped access (which is what we do here) to the EDPCSR_Lo. Section H.7.1.2 : Reads of EDPCSRs (in ARM DDI 0487A.k) : "The

Re: kvm/arm64: use-after-free in kvm_vm_ioctl/vmacache_update

On 10/03/17 15:50, Andrey Konovalov wrote: On Fri, Mar 10, 2017 at 2:38 PM, Andrey Konovalov wrote: Hi, I've got the following error report while fuzzing the kernel with syzkaller. On linux-next commit 56b8bad5e066c23e8fa273ef5fba50bd3da2ace8 (Mar 8). Unfortunately I

Re: kvm/arm64: use-after-free in kvm_unmap_hva_handler/unmap_stage2_pmds

On 18/04/17 10:08, Mark Rutland wrote: On Tue, Apr 18, 2017 at 09:32:31AM +0100, Mark Rutland wrote: Hi Suzuki, On Thu, Apr 13, 2017 at 04:50:46PM +0100, Suzuki K. Poulose wrote: kvm: Hold reference to the user address space The core KVM code, uses mmgrab/mmdrop to pin the mm struct

[PATCH v3 04/18] arm64: qcom-msm8916: dts: Update coresight replicator

Replace the obsolete compatible string for Coresight programmable replicator with the new one. Cc: Andy Gross <andy.gr...@linaro.org> Cc: David Brown <david.br...@linaro.org> Cc: linux-arm-...@vger.kernel.org Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by

[PATCH v3 17/18] coresight tmc: Add support for Coresight SoC 600 TMC

, ETB & ETR), unlike the previous generation. While the DEVID exposes some of the features/changes in the TMC, it doesn't explicitly advertises the new save-restore feature as described above. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.po

[PATCH v3 18/18] coresight: Add support for Coresight SoC 600 components

Add the peripheral ids for the Coresight SoC 600 TPIU, replicator and funnel. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-dynamic-replicator.c | 5 + drivers/hwtracing/coresig

[PATCH v3 14/18] coresight tmc etr: Cleanup AXICTL register handling

org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++--- drivers/hwtracing/coresight/coresight-tmc.h | 17 - 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/c

[PATCH v3 13/18] coresight tmc etr: Detect address width at runtime

m> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 26 +++--- drivers/hwtracing/coresight/coresight-tmc.h | 4 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/

[PATCH v3 08/18] coresight tmc: Expose DBA and AXICTL

Expose DBALO,DBAHI and AXICTL registers Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresi

[PATCH v3 05/18] coresight: Extend the PIDR mask to cover relevant bits in PIDR2

for a different device altogether. This patch fixes the mask and the corresponding id bits for the existing devices. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: Linus Walleij <linus.wall...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- I have not to

[PATCH v3 01/18] coresight replicator: Cleanup programmable replicator naming

rutl...@arm.com> Acked-by: Rob Herring <robh...@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V1: - Since the driver doesn't use the compatible string, change the recommended compatible string. - Rename the driver file to coresight-dynamic-

[PATCH v3 02/18] arm64: juno: dts: Use the new coresight replicator string

Use the new compatible for ATB programmable replicator in Juno. Cc: Sudeep Holla <sudeep.ho...@arm.com> Cc: Mike Leach <mike.le...@linaro.org> Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: Liviu Dudau <liviu.du...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki

[PATCH v3 00/16] coresight: Support for ARM Coresight SoC-600

out by Mathieu - Fix commit description for "coresight tmc: Handle configuration types properly" - Drop SWFIFO2 from the capability of SoC-600 TMC Suzuki K Poulose (18): coresight replicator: Cleanup programmable replicator naming arm64: juno: dts: Use the new coresight repl

[PATCH v3 16/18] coresight tmc: Support for save-restore in ETR

the STS.Full register. This can be later exploited for proper save-restore of ETR trace contexts (e.g, perf). Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 - drive

[PATCH v3 10/18] coresight tmc: Handle configuration types properly

if we encounter an unsupported configuration (ETS). Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --g

[PATCH v3 12/18] coresight tmc: Detect support for scatter gather

inaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 2 ++ drivers/hwtracing/coresight/coresight-tmc.h | 5 + 2 files changed, 7 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/h

[PATCH v3 15/18] coresigh tmc etr: Setup AXI cache encoding for read transfers

: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 ++ drivers/hwtracing/coresight/coresight-tmc.h | 9 + 2 files changed, 15 insertions(+) diff --git a/drive

[PATCH v3 11/18] coresight tmc etr: Add capabilitiy information

a bitmask of the available features which can be later checked to take appropriate actions. Cc: Mathieu Poirier <mathieu.por...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 20 +++- drivers/hwtracing/cor

[PATCH v3 09/18] coresight replicator: Expose replicator management registers

Expose the idfilter* registers of the programmable replicator. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../coresight/coresight-dynamic-replicator.c| 21 + 1 file changed, 21 inserti

[PATCH v3 06/18] coresight: Add support for reading 64bit registers

Add support for reading a lower and upper 32bits of a register as a single 64bit register. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-priv.h | 27 ++--

[PATCH v3 07/18] coresight tmc: Add helpers for accessing 64bit registers

Coresight TMC splits 64bit registers into a pair of 32bit registers (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/core

[PATCH v3 03/18] arm: qcom-msm8974: dts: Update coresight replicator

Replace the obsolete compatible string for Coresight programmable replicator with the new one. Cc: Andy Gross <andy.gr...@linaro.org> Cc: David Brown <david.br...@linaro.org> Cc: linux-arm-...@vger.kernel.org Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by

Re: [PATCH v2] KVM: arm/arm64: Handle hva aging while destroying the vm

On 16/07/17 20:56, Christoffer Dall wrote: On Fri, Jul 14, 2017 at 05:40:48PM +0100, Suzuki K Poulose wrote: On 06/07/17 10:42, Christoffer Dall wrote: On Thu, Jul 06, 2017 at 10:34:58AM +0100, Suzuki K Poulose wrote: On 06/07/17 08:45, Christoffer Dall wrote: On Thu, Jul 06, 2017 at 09:07

Re: [PATCH 3.16 121/178] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

On 16/07/17 14:56, Ben Hutchings wrote: 3.16.46-rc1 review patch. If anyone has any objections, please let me know. -- From: Suzuki K Poulose <suzuki.poul...@arm.com> commit 8b3405e345b5a098101b0c31b264c812bba045d9 upstream. In kvm_free_stage2_pgd() we don't hold t

Re: [PATCH v2] KVM: arm/arm64: Handle hva aging while destroying the vm

On 06/07/17 10:42, Christoffer Dall wrote: On Thu, Jul 06, 2017 at 10:34:58AM +0100, Suzuki K Poulose wrote: On 06/07/17 08:45, Christoffer Dall wrote: On Thu, Jul 06, 2017 at 09:07:49AM +0200, Alexander Graf wrote: On 05.07.17 10:57, Suzuki K Poulose wrote: Hi Alex, On Wed, Jul 05, 2017

Re: [PATCH v3 01/18] coresight replicator: Cleanup programmable replicator naming

On 17/07/17 18:45, Mathieu Poirier wrote: On Fri, Jul 14, 2017 at 02:04:06PM +0100, Suzuki K Poulose wrote: The Linux coresight drivers define the programmable ATB replicator as Qualcomm replicator, while this is designed by ARM. This can cause confusion to a user selecting the driver. Cleanup

Re: [PATCH v3 14/18] coresight tmc etr: Cleanup AXICTL register handling

On 17/07/17 18:06, Mathieu Poirier wrote: On Fri, Jul 14, 2017 at 02:04:19PM +0100, Suzuki K Poulose wrote: This patch cleans up how we setup the AXICTL register on TMC ETR. At the moment we don't set the CacheCtrl bits, which drives the arcache and awcache bits on AXI bus specifying

[PATCH v4 03/18] arm: qcom-msm8974: dts: Update coresight replicator

y: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c5ee

[PATCH v4 05/18] coresight: Extend the PIDR mask to cover relevant bits in PIDR2

for a different device altogether. This patch fixes the mask and the corresponding id bits for the existing devices. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: Linus Walleij <linus.wall...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../coresight

[PATCH v4 07/18] coresight tmc: Add helpers for accessing 64bit registers

Coresight TMC splits 64bit registers into a pair of 32bit registers (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/core

[PATCH v4 10/18] coresight tmc: Handle configuration types properly

if we encounter an unsupported configuration (ETS). Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --g

[PATCH v4 09/18] coresight replicator: Expose replicator management registers

Expose the idfilter* registers of the programmable replicator. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../coresight/coresight-dynamic-replicator.c| 21 + 1 file changed, 21 inserti

[PATCH v4 11/18] coresight tmc etr: Add capabilitiy information

a bitmask of the available features which can be later checked to take appropriate actions. Cc: Mathieu Poirier <mathieu.por...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 20 +++- drivers/hwtracing/cor

[PATCH v4 08/18] coresight tmc: Expose DBA and AXICTL

Expose DBALO,DBAHI and AXICTL registers Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresi

[PATCH v4 13/18] coresight tmc etr: Detect address width at runtime

m> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 26 +++--- drivers/hwtracing/coresight/coresight-tmc.h | 4 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/

[PATCH v4 06/18] coresight: Add support for reading 64bit registers

Add support for reading a lower and upper 32bits of a register as a single 64bit register. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-priv.h | 27 ++--

[PATCH v4 18/18] coresight: Add support for Coresight SoC 600 components

Add the peripheral ids for the Coresight SoC 600 TPIU, replicator and funnel. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-dynamic-replicator.c | 5 + drivers/hwtracing/coresig

[PATCH v4 12/18] coresight tmc: Detect support for scatter gather

inaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 2 ++ drivers/hwtracing/coresight/coresight-tmc.h | 5 + 2 files changed, 7 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/h

[PATCH v4 14/18] coresight tmc etr: Cleanup AXICTL register handling

org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++--- drivers/hwtracing/coresight/coresight-tmc.h | 17 - 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/c

[PATCH v4 16/18] coresight tmc: Support for save-restore in ETR

the STS.Full register. This can be later exploited for proper save-restore of ETR trace contexts (e.g, perf). Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 - drive

[PATCH v4 15/18] coresigh tmc etr: Setup AXI cache encoding for read transfers

: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 ++ drivers/hwtracing/coresight/coresight-tmc.h | 10 +- 2 files changed, 15 insertions(+), 1 deletion(-)

[PATCH v4 00/18] coresight: Support for ARM Coresight SoC-600

tmc: Handle configuration types properly" - Drop SWFIFO2 from the capability of SoC-600 TMC Suzuki K Poulose (18): coresight replicator: Cleanup programmable replicator naming arm64: juno: dts: Use the new coresight replicator string arm: qcom-msm8974: dts: Update coresight replicat

[PATCH v4 04/18] arm64: qcom-msm8916: dts: Update coresight replicator

y: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi

[PATCH v4 17/18] coresight tmc: Add support for Coresight SoC 600 TMC

, ETB & ETR), unlike the previous generation. While the DEVID exposes some of the features/changes in the TMC, it doesn't explicitly advertises the new save-restore feature as described above. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.po

[PATCH v4 02/18] arm64: juno: dts: Use the new coresight replicator string

.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index e8b7413..56f7ac2

[PATCH v4 01/18] coresight replicator: Cleanup programmable replicator naming

arm.com> Acked-by: Rob Herring <robh...@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Documentation/devicetree/bindings/arm/coresight.txt| 4 ++-- drivers/hwtracing/coresight/Kconfig| 10 +++

[PATCH v5 11/19] coresight tmc: Handle configuration types properly

if we encounter an unsupported configuration (ETS). Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --g

[PATCH v5 13/19] coresight tmc: Detect support for scatter gather

inaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 2 ++ drivers/hwtracing/coresight/coresight-tmc.h | 5 + 2 files changed, 7 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/h

[PATCH v5 16/19] coresigh tmc etr: Setup AXI cache encoding for read transfers

: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 6 ++ drivers/hwtracing/coresight/coresight-tmc.h | 10 +- 2 files changed, 15 insertions(+), 1 deletion(-)

[PATCH v5 19/19] coresight: Add support for Coresight SoC 600 components

Add the peripheral ids for the Coresight SoC 600 TPIU, replicator and funnel. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-dynamic-replicator.c | 5 + drivers/hwtracing/coresig

[PATCH v5 15/19] coresight tmc etr: Cleanup AXICTL register handling

org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++--- drivers/hwtracing/coresight/coresight-tmc.h | 17 - 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/c

[PATCH v5 14/19] coresight tmc etr: Detect address width at runtime

m> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 26 +++--- drivers/hwtracing/coresight/coresight-tmc.h | 4 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/

[PATCH v5 05/19] coresight: Extend the PIDR mask to cover relevant bits in PIDR2

for a different device altogether. This patch fixes the mask and the corresponding id bits for the existing devices. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: Linus Walleij <linus.wall...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../coresight

[PATCH v5 03/19] arm: qcom-msm8974: dts: Update coresight replicator

y: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c5ee

[PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit registers

Coresight TMC splits 64bit registers into a pair of 32bit registers (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/core

[PATCH v5 06/19] coresight: Add support for reading 64bit registers

Add support for reading a lower and upper 32bits of a register as a single 64bit register. Also add simplified macros for direct register accesses. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresig

[PATCH v5 10/19] coresight replicator: Expose replicator management registers

Expose the idfilter* registers of the programmable replicator. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../coresight/coresight-dynamic-replicator.c | 23 ++ 1 file changed, 23 inserti

[PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC

, ETB & ETR), unlike the previous generation. While the DEVID exposes some of the features/changes in the TMC, it doesn't explicitly advertises the new save-restore feature as described above. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.po

[PATCH v5 17/19] coresight tmc: Support for save-restore in ETR

the STS.Full register. This can be later exploited for proper save-restore of ETR trace contexts (e.g, perf). Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 - drive

[PATCH v5 12/19] coresight tmc etr: Add capabilitiy information

a bitmask of the available features which can be later checked to take appropriate actions. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 20 +++- drivers/hwtracing/cor

[PATCH v5 04/19] arm64: qcom-msm8916: dts: Update coresight replicator

y: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi

[PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600

wed-by tags for the DTS changes. Suzuki K Poulose (19): coresight replicator: Cleanup programmable replicator naming arm64: juno: dts: Use the new coresight replicator string arm: qcom-msm8974: dts: Update coresight replicator arm64: qcom-msm8916: dts: Update coresight replicator coresight: Ext

[PATCH v5 09/19] coresight tmc: Expose DBA and AXICTL

Expose DBALO,DBAHI and AXICTL registers Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresi

[PATCH v5 01/19] coresight replicator: Cleanup programmable replicator naming

arm.com> Acked-by: Rob Herring <robh...@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../devicetree/bindings/arm/coresight.txt | 4 +- drivers/hwtracing/coresight/Kconfig| 10 +- drivers/hwtracing/coresight/Makefile

[PATCH v5 07/19] coresight: Use the new helper for defining registers

Use the new helpers for exposing coresight component registers, choosing the 64bit variants for appropriate registers. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-etb10

[PATCH v5 02/19] arm64: juno: dts: Use the new coresight replicator string

.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index e8b7413..56f7ac2

Re: [PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit registers

On 24/07/17 18:11, Mathieu Poirier wrote: On 20 July 2017 at 04:17, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: Coresight TMC splits 64bit registers into a pair of 32bit registers (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers. Cc: Mathieu Poirier <mat

Re: [PATCH v2 2/6] of: Add helper for mapping device node to logical CPU number

On 24/07/17 17:42, Sudeep Holla wrote: On 24/07/17 11:29, Suzuki K Poulose wrote: Add a helper to map a device node to a logical CPU number to avoid duplication. Currently this is open coded in different places (e.g gic-v3, coresight). The helper tries to map device node to a "pos

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