Re: [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600

On 24/07/17 18:15, Mathieu Poirier wrote: On 20 July 2017 at 04:17, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: This series adds support for ARM Coresight SoC-600 IP, which implements Coresight V3 architecture. It also does some clean up of the replicator driver namings used in the

Re: [PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC

On 24/07/17 18:12, Mathieu Poirier wrote: On 20 July 2017 at 04:17, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: The coresight SoC 600 supports ETR save-restore which allows us to restore a trace session by retaining the RRP/RWP/STS.Full values when the TMC leaves the Disabled

Re: [PATCH v8 1/3] perf: cavium: Support memory controller PMU counters

On 25/07/17 16:04, Jan Glauber wrote: Add support for the PMU counters on Cavium SOC memory controllers. This patch also adds generic functions to allow supporting more devices with PMU counters. Properties of the LMC PMU counters: - not stoppable - fixed purpose - read-only - one PCI device

Re: [PATCH v2 6/6] perf: ARM DynamIQ Shared Unit PMU support

Hi Jonathan, On 24/07/17 15:50, Jonathan Cameron wrote: On Mon, 24 Jul 2017 11:29:21 +0100 Suzuki K Poulose <suzuki.poul...@arm.com> wrote: Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU). The DSU integrates one or more cores with an L3 memory system, control

Re: [PATCH v2 2/6] of: Add helper for mapping device node to logical CPU number

Hi Marc, On 24/07/17 14:14, Marc Zyngier wrote: On 24/07/17 11:29, Suzuki K Poulose wrote: Add a helper to map a device node to a logical CPU number to avoid duplication. Currently this is open coded in different places (e.g gic-v3, coresight). The helper tries to map device node

Re: [PATCH v5 03/19] arm: qcom-msm8974: dts: Update coresight replicator

On 20/07/17 11:17, Suzuki K Poulose wrote: Replace the obsolete compatible string for Coresight programmable replicator with the new one. Cc: Andy Gross <andy.gr...@linaro.org> Cc: David Brown <david.br...@linaro.org> Cc: linux-arm-...@vger.kernel.org Cc: Mathieu Poirier &

[PATCH v3 6/6] perf: ARM DynamIQ Shared Unit PMU support

drivers. The driver only supports ARM64 at the moment. It can be extended to support ARM32 by providing register accessors like we do in arch/arm64/include/arm_dsu_pmu.h. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose

[PATCH v3 2/6] of: Add helper for mapping device node to logical CPU number

arc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/of/base.c | 26 ++ include/linux/of_device.h | 7 +++ 2 files changed, 33 insertions(+) diff --git a/drivers/of/base.c b/drivers/of/base.c index 686628d..0b01

[PATCH v3 4/6] irqchip: gic-v3: Use of_device_node_get_cpu helper

Use the new generic helper of_device_node_get_cpu() instead of using our own version to map a device node to logical CPU number. Acked-by: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/irqchip/irq-g

[PATCH v3 3/6] coresight: of: Use of_device_node_get_cpu helper

Reuse the new generic helper, of_device_node_get_cpu() to map a given CPU phandle to a logical CPU number. Cc: Leo Yan <leo@linaro.org> Acked-by: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/h

Re: [PATCH v3 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU

On 27/07/17 16:52, Rob Herring wrote: +DT list On Thu, Jul 27, 2017 at 10:10 AM, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: This patch documents the devicetree bindings for ARM DSU PMU. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com>

[PATCH v3 1/6] perf: Export perf_event_update_userpage

Export perf_event_update_userpage() so that PMU driver using them, can be built as modules. Cc: Peter Zilstra <pet...@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/cor

[PATCH v3 0/6] perf: Support for ARM DynamIQ Shared Unit PMU

. - Add MODULE_DEVICE_TABLE entry - Use hlist_entry_safe for converting cpuhp_node to dsu_pmu. - Added Reviews and Acks. Changes since V1: - Use the new of_device_node_get_cpu() helper for Coresight - Rebased to 4.13-rc2 Suzuki K Poulose (6): perf: Export perf_event_update_userpage of: Add

[PATCH v3 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU

This patch documents the devicetree bindings for ARM DSU PMU. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Rob Herring <r...@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../devicetree/bindings/arm/arm

Re: [PATCH v3 2/6] of: Add helper for mapping device node to logical CPU number

On 27/07/17 16:48, Rob Herring wrote: Please use get_maintainers and cc the right people/lists. Sorry about that, will fix it. +Frank, DT list On Thu, Jul 27, 2017 at 10:10 AM, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: Add a helper to map a device node to a logical CPU

Re: [PATCH v8 1/3] perf: cavium: Support memory controller PMU counters

On 26/07/17 12:19, Jan Glauber wrote: On Tue, Jul 25, 2017 at 04:39:18PM +0100, Suzuki K Poulose wrote: On 25/07/17 16:04, Jan Glauber wrote: Add support for the PMU counters on Cavium SOC memory controllers. This patch also adds generic functions to allow supporting more devices with PMU

Re: [PATCH v8 1/3] perf: cavium: Support memory controller PMU counters

+To: Boris Hi Boris, On 26/07/17 14:10, Jan Glauber wrote: On Wed, Jul 26, 2017 at 01:47:35PM +0100, Suzuki K Poulose wrote: On 26/07/17 12:19, Jan Glauber wrote: On Tue, Jul 25, 2017 at 04:39:18PM +0100, Suzuki K Poulose wrote: On 25/07/17 16:04, Jan Glauber wrote: Add support for the PMU

Re: [PATCH v8 1/3] perf: cavium: Support memory controller PMU counters

On 26/07/17 16:13, Jan Glauber wrote: On Wed, Jul 26, 2017 at 04:55:22PM +0200, Borislav Petkov wrote: On Wed, Jul 26, 2017 at 03:35:25PM +0100, Suzuki K Poulose wrote: So the Cavium EDACs, which appear as PCI devices have a PMU attached to it. Cavium EDACs? So let me set something straight

[PATCH v2 0/6] perf: Support for ARM DynamIQ Shared Unit PMU

. Series applies on v4.13-rc2 and is also available at: git://linux-arm.org/linux-skp.git 4.13/dsu-v2 Changes since V1: - Use the new of_device_node_get_cpu() helper for Coresight - Rebased to 4.13-rc2 Suzuki K Poulose (6): perf: Export perf_event_update_userpage of: Add helper for mapping

[PATCH v2 6/6] perf: ARM DynamIQ Shared Unit PMU support

drivers. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/arm_dsu_pmu.h | 124 + drivers/perf/Kconfig | 9 + drivers/perf/Makefile

[PATCH v2 2/6] of: Add helper for mapping device node to logical CPU number

er to make sure that the CPU is online. The helper uses of_get_cpu_node() which uses arch specific backends to match the phyiscal ids. Cc: Rob Herring <robh...@kernel.org> Cc: Mark Rutland <mark.rutl...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- dr

[PATCH v2 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU

This patch documents the devicetree bindings for ARM DSU PMU. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Rob Herring <r...@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../devicetree/bindings/arm/arm

[PATCH v2 3/6] coresight: of: Use of_device_node_get_cpu helper

Reuse the new generic helper, of_device_node_get_cpu() to map a given CPU phandle to a logical CPU number. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: Leo Yan <leo@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresi

[PATCH v2 4/6] irqchip: gic-v3: Use of_device_node_get_cpu helper

Use the new generic helper of_device_node_get_cpu() instead of using our own version to map a device node to logical CPU number. Cc: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/irqchip/irq-g

[PATCH v2 1/6] perf: Export perf_event_update_userpage

Export perf_event_update_userpage() so that PMU driver using them, can be built as modules. Cc: Peter Zilstra <pet...@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/cor

Re: [PATCH 01/11] arm64: docs: describe ELF hwcaps

it is easy to get confused with the former. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Dave Martin <dave.mar...@arm.com> Cc: Suzuki K Poulose <suzuki.poul...@arm.com> Cc: Will Deacon <will.dea...@arm.com>

Re: [PATCH 04/11] arm64/cpufeature: add ARMv8.3 id_aa64isar1 bits

, the features are hidden from userspace. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/cpufeature.c | 6 +- 1 file cha

Re: [PATCH v2 02/12] arm64: dts: juno: Use the new coresight replicator string

On 28/06/17 19:00, Mathieu Poirier wrote: On 26 June 2017 at 09:22, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: Use the new compatible for ATB programmable replicator in Juno. Cc: Sudeep Holla <sudeep.ho...@arm.com> Cc: Mike Leach <mike.le...@linaro.org> Cc: Mathieu Poi

[PATCH 3/3] irq: gic-v3: Honor forced affinity setting

Honor the 'force' flag for set_affinity, by selecting a CPU from the given mask (which may not be reported "online" by the cpu_online_mask). Some drivers, like ARM PMU, rely on it. Cc: Marc Zyngier <marc.zyng...@arm.com> Reported-by: Mark Rutland <mark.rutl...@arm.com> S

[PATCH 2/3] irqchip: gic-v2: Report failures in gic_irq_domain_alloc

mit 9a1091ef0017c ("irqchip: gic: Support hierarchy irq domain.") Cc: Yingjoe Chen <yingjoe.c...@mediatek.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/irqchip/irq-gic.c | 7 +-- 1 file changed, 5 inse

[PATCH 0/3] irqchip: Miscellaneous fixes for GIC/GICv3

This series contains some fixes for GIC/GIC-v3 to behave as expected by the generic management layer. Suzuki K Poulose (3): irqchip: gic-v3: Report failures in gic_irq_domain_alloc irqchip: gic-v2: Report failures in gic_irq_domain_alloc irq: gic-v3: Honor forced affinity setting drivers

[PATCH 1/3] irqchip: gic-v3: Report failures in gic_irq_domain_alloc

mit 443acc4f37f6 ("irqchip: GICv3: Convert to domain hierarchy") Cc: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/irqchip/irq-gic-v3.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drive

Re: [PATCH v2] KVM: arm/arm64: Handle hva aging while destroying the vm

all <cd...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: sta...@vger.kernel.org Fixes: commit 293f29363 ("kvm-arm: Unmap shadow pagetables properly") Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- virt/kvm/arm/mmu.c | 4 1 file changed, 4 in

Re: [PATCH] bus: arm-cci: constify attribute_group structures.

On 06/07/17 05:53, Arvind Yadav wrote: Hi, On Wednesday 05 July 2017 09:33 PM, Suzuki K Poulose wrote: On 03/07/17 08:46, Arvind Yadav wrote: attribute_groups are not supposed to change at runtime. All functions working with attribute_groups provided by work with const attribute_group. So

Re: [PATCH v2] KVM: arm/arm64: Handle hva aging while destroying the vm

On 06/07/17 08:45, Christoffer Dall wrote: On Thu, Jul 06, 2017 at 09:07:49AM +0200, Alexander Graf wrote: On 05.07.17 10:57, Suzuki K Poulose wrote: Hi Alex, On Wed, Jul 05, 2017 at 08:20:31AM +0200, Alexander Graf wrote: The kvm_age_hva callback may be called all the way concurrently

Re: [PATCH v2 09/12] coresight tmc: Add capability information

On 26/06/17 16:22, Suzuki K Poulose wrote: This patch adds description of the capabilities of a given TMC. This will help us to handle different versions of the TMC in the same driver by checking the capabilities. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K P

Re: [PATCH] bus: arm-cci: constify attribute_group structures.

On 03/07/17 08:46, Arvind Yadav wrote: attribute_groups are not supposed to change at runtime. All functions working with attribute_groups provided by work with const attribute_group. So mark the non-const structs as const. Signed-off-by: Arvind Yadav ---

Re: [PATCH v2 03/12] coresight: Extend the PIDR mask to cover relevant bits in PIDR2

On 28/06/17 18:35, Mathieu Poirier wrote: On 26 June 2017 at 09:22, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: As per coresight standards, PIDR2 register has the following format : [2-0] - JEP106_bits6to4 [3]- JEDEC, designer ID is specified by JEDEC. However some of the d

Re: [PATCH 1/2] kvm: Fix mmu_notifier release race

On 25/04/17 19:49, Radim Krčmář wrote: 2017-04-24 11:10+0100, Suzuki K Poulose: The KVM uses mmu_notifier (wherever available) to keep track of the changes to the mm of the guest. The guest shadow page tables are released when the VM exits via mmu_notifier->ops.release(). There is a rare cha

Re: [patch V2 00/24] cpu/hotplug: Convert get_online_cpus() to a percpu_rwsem

On 26/04/17 09:59, Mark Rutland wrote: On Tue, Apr 25, 2017 at 07:28:38PM +0200, Sebastian Siewior wrote: On 2017-04-25 17:10:37 [+0100], Mark Rutland wrote: When we bring the secondary CPU online, we detect an erratum that wasn't present on the boot CPU, and try to enable a static branch we

Re: [PATCH] arm64: cpufeature: use static_branch_enable_cpuslocked() (was: Re: [patch V2 00/24] cpu/hotplug: Convert get_online_cpus() to a percpu_rwsem)

h_enable_cpuslocked(), and updates all the callers of update_cpu_capabilities() consistent with the change. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Reported-by: Catalin Marinas <catalin.mari...@arm.com> Suggested-by: Sebastian Andrzej Siewior <bige...@linutronix.de> Suggested

Re: [PATCH] arm64: cpufeature: use static_branch_enable_cpuslocked()

On 27/04/17 17:35, Suzuki K Poulose wrote: rom f3b0809224e4915197d3ae4a38ebe7f210e74abf Mon Sep 17 00:00:00 2001 From: Mark Rutland <mark.rutl...@arm.com> Date: Thu, 27 Apr 2017 16:48:06 +0100 Subject: [PATCH] arm64: cpufeature: use static_branch_enable_cpuslocked() Build break

Re: [PATCH v3] kvm: arm/arm64: Fix locking for kvm_free_stage2_pgd

On Sat, Apr 22, 2017 at 02:28:44AM +0200, Alexander Graf wrote: > > > On 04.04.17 12:35, Suzuki K Poulose wrote: > > Hi Christoffer, > > > > On 04/04/17 11:13, Christoffer Dall wrote: > > > Hi Suzuki, > > > > > > On Mon, Ap

[PATCH 2/2] kvm: arm/arm64: Fix race in resetting stage2 PGD

...@arm.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm/kvm/mmu.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index 582a972..9c4026d 1

[PATCH 0/2] kvm: Fixes for race conditions

c40-1a76d1399...@suse.de Suzuki K Poulose (2): kvm: Fix mmu_notifier release race kvm: arm/arm64: Fix race in resetting stage2 PGD arch/arm/kvm/mmu.c | 14 +++- include/linux/kvm_host.h | 1 + virt/kvm/kvm_main.c | 59 ++-- 3 fi

[PATCH 1/2] kvm: Fix mmu_notifier release race

rm.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Radim Krčmář <rkrc...@redhat.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: andreyk...@google.com Cc: Marc Zyngier <marc.zyng...@arm.com> Tested-by: Mark Rut

Re: [PATCH 1/2] kvm: Fix mmu_notifier release race

On 26/04/17 17:03, Suzuki K Poulose wrote: On 25/04/17 19:49, Radim Krčmář wrote: 2017-04-24 11:10+0100, Suzuki K Poulose: The KVM uses mmu_notifier (wherever available) to keep track of the changes to the mm of the guest. The guest shadow page tables are released when the VM exits via

Re: [RFC] minimum gcc version for kernel: raise to gcc-4.3 or 4.6?

On 16/04/17 20:52, Kees Cook wrote: Was there a conclusion to this discussion? I didn't see anything definitive in the thread... Notes below... On Fri, Dec 16, 2016 at 3:14 AM, Arnd Bergmann wrote: [Fixed linux-arm-kernel mailing list address, sorry for the duplicate, I'm not

[PATCH v5 0/6] perf: Support for ARM DynamIQ Shared Unit

. - Add MODULE_DEVICE_TABLE entry - Use hlist_entry_safe for converting cpuhp_node to dsu_pmu. - Added Reviews and Acks. Changes since V1: - Use the new of_device_node_get_cpu() helper for Coresight - Rebased to 4.13-rc2 Suzuki K Poulose (6): perf: Export perf_event_update_userpage of: Add

[PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

drivers. The driver only supports ARM64 at the moment. It can be extended to support ARM32 by providing register accessors like we do in arch/arm64/include/arm_dsu_pmu.h. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose

[PATCH v5 4/6] irqchip: gic-v3: Use of_cpu_node_to_id helper

Use the new generic helper of_cpu_node_to_id() instead of using our own version to map a device node to logical CPU number. Acked-by: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V3: - Reflect the change in the

[PATCH v5 2/6] of: Add helper for mapping device node to logical CPU number

rm.com> Reviewed-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Rob Herring <r...@kernel.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V3: - Renamed the helper to of_cpu_node_to_id(), suggested by Rob - Return -ENODEV on failur

[PATCH v5 3/6] coresight: of: Use of_cpu_node_to_id helper

Reuse the new generic helper, of_cpu_node_to_id() to map a given CPU phandle to a logical CPU number. Cc: Leo Yan <leo@linaro.org> Acked-by: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V4:

[PATCH v5 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU

This patch documents the devicetree bindings for ARM DSU PMU. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Rob Herring <r...@kernel.org> Cc: devicet...@vger.kernel.org Cc: frowand.l...@gmail.com Signed-off-by: Suzuki K Poulose <s

Re: [PATCH v4 6/6] perf: ARM DynamIQ Shared Unit PMU support

/commits/Suzuki-K-Poulose/perf-Support-for-ARM-DynamIQ-Shared-Unit-PMU/20170808-124822 config: arm64-allmodconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin

[PATCH v5 1/6] perf: Export perf_event_update_userpage

Export perf_event_update_userpage() so that PMU driver using them, can be built as modules. Cc: Peter Zilstra <pet...@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/cor

Re: [PATCH v4 3/6] coresight: of: Use of_cpu_node_to_id helper

/commits/Suzuki-K-Poulose/perf-Support-for-ARM-DynamIQ-Shared-Unit-PMU/20170808-124822 config: arm-allmodconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705 reproduce: wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin

Re: [PATCH v8 1/3] perf: cavium: Support memory controller PMU counters

On 27/07/17 10:08, Jan Glauber wrote: On Thu, Jul 27, 2017 at 07:11:57AM +0200, Borislav Petkov wrote: On Wed, Jul 26, 2017 at 02:02:42PM -0700, David Daney wrote: Also, if a given configuration disables CONFIG_EDAC there is some hackery needed to get the perf portion of the driver included.

[PATCH v4 6/6] perf: ARM DynamIQ Shared Unit PMU support

drivers. The driver only supports ARM64 at the moment. It can be extended to support ARM32 by providing register accessors like we do in arch/arm64/include/arm_dsu_pmu.h. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose

[PATCH v4 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU

This patch documents the devicetree bindings for ARM DSU PMU. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Rob Herring <r...@kernel.org> Cc: devicet...@vger.kernel.org Cc: frowand.l...@gmail.com Signed-off-by: Suzuki K Poulose <s

[PATCH v4 4/6] irqchip: gic-v3: Use of_cpu_node_to_id helper

Use the new generic helper of_cpu_node_to_id() instead of using our own version to map a device node to logical CPU number. Acked-by: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V3: - Reflect the change in the

[PATCH v4 2/6] of: Add helper for mapping device node to logical CPU number

Cc: Sudeep Holla <sudeep.ho...@arm.com> Reviewed-by: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V3: - Renamed the helper to of_cpu_node_to_id(), suggested by Rob - Return -ENODEV on failur

[PATCH v4 1/6] perf: Export perf_event_update_userpage

Export perf_event_update_userpage() so that PMU driver using them, can be built as modules. Cc: Peter Zilstra <pet...@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- kernel/events/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/events/cor

[PATCH v4 3/6] coresight: of: Use of_cpu_node_to_id helper

Reuse the new generic helper, of_cpu_node_to_id() to map a given CPU phandle to a logical CPU number. Cc: Leo Yan <leo@linaro.org> Acked-by: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V3: - Re

[PATCH v4 0/6] perf: Support for ARM DynamIQ Shared Unit PMU

since V1: - Use the new of_device_node_get_cpu() helper for Coresight - Rebased to 4.13-rc2 Suzuki K Poulose (6): perf: Export perf_event_update_userpage of: Add helper for mapping device node to logical CPU number coresight: of: Use of_cpu_node_to_id helper irqchip: gic-v3: Use

Re: [PATCH v6 6/6] perf: ARM DynamIQ Shared Unit PMU support

On 22/08/17 12:17, Jonathan Cameron wrote: On Mon, 21 Aug 2017 18:55:09 +0100 Suzuki K Poulose <suzuki.poul...@arm.com> wrote: Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU). The DSU integrates one or more cores with an L3 memory system, control logic, and ex

Re: [PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

Hi Mark, On 16/08/17 15:10, Mark Rutland wrote: On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote: +/* + * struct dsu_pmu - DSU PMU descriptor + * + * @pmu_lock : Protects accesses to DSU PMU register from multiple + * CPUs. + * @hw_events

Re: [PATCH v5 6/6] perf: ARM DynamIQ Shared Unit PMU support

On 17/08/17 16:57, Mark Rutland wrote: On Thu, Aug 17, 2017 at 03:52:24PM +0100, Suzuki K Poulose wrote: On 16/08/17 15:10, Mark Rutland wrote: On Tue, Aug 08, 2017 at 12:37:26PM +0100, Suzuki K Poulose wrote: +static struct attribute *dsu_pmu_event_attrs[] = { + DSU_EVENT_ATTR(cycles

[PATCH 1/2] kvm: arm/arm64: Fix race in resetting stage2 PGD

Reviewed-by: Christoffer Dall <cd...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm/kvm/mmu.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c index 313ee64..909a1a7 100644 -

[PATCH 2/2] kvm: arm/arm64: Fix use after free of stage2 page table

t; Cc: Radim Krčmář <rkrc...@redhat.com> Cc: andreyk...@google.com Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/ar

Re: [PATCH 1/2] kvm: Fix mmu_notifier release race

On 28/04/17 18:20, Suzuki K Poulose wrote: On 26/04/17 17:03, Suzuki K Poulose wrote: On 25/04/17 19:49, Radim Krčmář wrote: 2017-04-24 11:10+0100, Suzuki K Poulose: The KVM uses mmu_notifier (wherever available) to keep track of the changes to the mm of the guest. The guest shadow page

[PATCHv2 0/2] kvm: arm/arm64: Fixes for race conditions

be reproduced. - Added reviewed-by from Christoffer - Added new patch to fix another race condition Suzuki K Poulose (2): kvm: arm/arm64: Fix race in resetting stage2 PGD kvm: arm/arm64: Fix use after free of stage2 page table arch/arm/kvm/mmu.c | 33 - 1

Re: [PATCHv3] arm64/cpufeature: don't use mutex in bringup path

oul...@arm.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: Will Deacon <will.dea...@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com>

Re: [PATCH 2/2] kvm: arm/arm64: Fix use after free of stage2 page table

On 15/05/17 14:36, Suzuki K Poulose wrote: On 15/05/17 11:00, Christoffer Dall wrote: Hi Suzuki, On Wed, May 03, 2017 at 03:17:52PM +0100, Suzuki K Poulose wrote: We yield the kvm->mmu_lock occassionaly while performing an operation (e.g, unmap or permission changes) on a large area of sta

Re: [PATCH 2/2] kvm: arm/arm64: Fix use after free of stage2 page table

On 15/05/17 11:00, Christoffer Dall wrote: Hi Suzuki, On Wed, May 03, 2017 at 03:17:52PM +0100, Suzuki K Poulose wrote: We yield the kvm->mmu_lock occassionaly while performing an operation (e.g, unmap or permission changes) on a large area of stage2 mappings. However this could possibly ca

Re: [PATCHv2] arm64/cpufeature: don't use mutex in bringup path

On 11/05/17 16:01, Mark Rutland wrote: Currently, cpus_set_cap() calls static_branch_enable_cpuslocked(), which must take the jump_label mutex. We call cpus_set_cap() in the secondary bringup path, from the idle thread where interrupts are disabled. Taking a mutex in this path "is a NONO"

Re: [PATCHv2] arm64/cpufeature: don't use mutex in bringup path

On 11/05/17 16:37, Mark Rutland wrote: On Thu, May 11, 2017 at 04:15:38PM +0100, Suzuki K Poulose wrote: On 11/05/17 16:01, Mark Rutland wrote: +static inline bool cpus_have_const_cap(int num) +{ + if (static_branch_likely(_const_caps_ready)) + return __cpus_have_const_cap

Re: [PATCH v9 7/9] coresight: add support for CPU debug module

e parameter or sysfs to constrain all or partial idle states to ensure the CPU power domain is enabled and access coresight CPU debug component safely. Signed-off-by: Leo Yan <leo@linaro.org> With comments from Mathieu addressed, Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com>

Re: [PATCH 2/2] kvm: arm/arm64: Fix use after free of stage2 page table

On 15/05/17 18:43, Christoffer Dall wrote: On Mon, May 15, 2017 at 02:36:58PM +0100, Suzuki K Poulose wrote: On 15/05/17 11:00, Christoffer Dall wrote: Hi Suzuki, So I don't think this change is wrong, but I wonder if it's sufficient. For example, I can see that this function is called from

Re: [PATCH] arm64: cpufeature: check translation granule size based on kernel config

On 18/05/17 11:21, Leo Yan wrote: In the big.LITTLE system with two clusters, one is CA53 cluster and another is CA73 cluster. CA53 doesn't support 16KB memory translation granule size (4.3.21 AArch64 Memory Model Feature Register 0, EL1; ARM DDI 0500F), but CA73 supports this feature (4.3.27

[PATCH v3 0/2] kvm: arm/arm64: Fixes for race conditions

ace condition Suzuki K Poulose (2): kvm: arm/arm64: Force reading uncached stage2 PGD kvm: arm/arm64: Fix use after free of stage2 page table virt/kvm/arm/mmu.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) -- 2.7.4

[PATCH v3 2/2] kvm: arm/arm64: Fix use after free of stage2 page table

t; Cc: Radim Krčmář <rkrc...@redhat.com> Cc: andreyk...@google.com Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Paolo Bonzini <pbonz...@redhat.com> Acked-by: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- vi

Re: [PATCH v3 0/2] kvm: arm/arm64: Fixes for race conditions

On 16/05/17 10:53, Christoffer Dall wrote: On Tue, May 16, 2017 at 10:34:53AM +0100, Suzuki K Poulose wrote: The patches fixes race conditions in stage2 pgd accesses. Patch 1 is a fix up for the patch which has already been pushed to kvmarm/master. Patch 2 fixes a case where stage2 PGD could

[PATCH v3 1/2] kvm: arm/arm64: Force reading uncached stage2 PGD

Make sure we don't use a cached value of the KVM stage2 PGD while resetting the PGD. Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Christoffer Dall <cd...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- virt/kvm/arm/mmu.c | 2 +- 1 file changed, 1 insert

[PATCH 03/12] coresight: Extend the PIDR mask to cover relevant bits in PIDR2

for a different device altogether. This patch fixes the mask and the corresponding id bits for the existing devices. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: Linus Walleij <linus.wall...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- I have not to

[PATCH 00/12] coresight: Support for ARM Coresight SoC-600

Patch 12 adds the support for other components in SoC 600. Tested on Juno (with Coresight SoC 400) and an FPGA based system for SoC 600. Suzuki K Poulose (12): coresight replicator: Cleanup programmable replicator naming arm64: dts: juno: Use the new coresight replicator string coresight

[PATCH 02/12] arm64: dts: juno: Use the new coresight replicator string

Use the new compatible for ATB programmable replicator in Juno. Cc: Sudeep Holla <sudeep.ho...@arm.com> Cc: Mike Leach <mike.le...@linaro.org> Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: Liviu Dudau <liviu.du...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki

[PATCH 01/12] coresight replicator: Cleanup programmable replicator naming

com => coresight-dynamic-replicator Cc: Pratik Patel <prat...@codeaurora.org> Cc: Ivan T. Ivanov <ivan.iva...@linaro.org> Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: devicet...@vger.kernel.org Cc: Rob Herring <robh...@kernel.org> Cc: Mark Rutland <mark.rutl...

[PATCH 04/12] coresight: Add support for reading 64bit registers

Add support for reading a lower and upper 32bits of a register as a single 64bit register. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-priv.h | 27 ++--

[PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers

Coresight TMC splits 64bit registers into a pair of 32bit registers (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/core

[PATCH 07/12] coresight replicator: Expose replicator management registers

Expose the idfilter* registers of the programmable replicator. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../hwtracing/coresight/coresight-replicator-qcom.c | 21 + 1 file changed, 21 inserti

[PATCH 12/12] coresight: Add support for Coresight SoC 600 components

Add the peripheral ids for the Coresight SoC 600 TPIU, replicator and funnel. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-funnel.c | 5 + drivers/hwtracing/coresig

[PATCH 11/12] coresight tmc: Add support for Coresight SoC 600 TMC

rier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 20 drivers/hwtracing/coresight/coresight-tmc.h | 8 2 files changed, 28 insertions(+) diff --git a/drivers/hwt

[PATCH 08/12] coresight tmc: Handle configuration types properly

Coresight SoC 600 defines a new configuration for TMC, Embedded Trace Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. Make sure the driver handles the new type properly. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com>

[PATCH 09/12] coresight tmc: Add capability information

This patch adds description of the capabilities of a given TMC. This will help us to handle different versions of the TMC in the same driver by checking the capabilities. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com>

[PATCH 06/12] coresight tmc: Expose DBA and AXICTL

Expose DBALO,DBAHI and AXICTL registers Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresi

[PATCH 10/12] coresight tmc: Support for save-restore in ETR

the STS.Full register. This can be later exploited for proper save-restore of ETR trace contexts (e.g, perf). Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 - drive

[PATCH v2 02/12] arm64: dts: juno: Use the new coresight replicator string

Use the new compatible for ATB programmable replicator in Juno. Cc: Sudeep Holla <sudeep.ho...@arm.com> Cc: Mike Leach <mike.le...@linaro.org> Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Cc: Liviu Dudau <liviu.du...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki

[PATCH v2 07/12] coresight replicator: Expose replicator management registers

Expose the idfilter* registers of the programmable replicator. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- .../coresight/coresight-dynamic-replicator.c| 21 + 1 file changed, 21 inserti

[PATCH v2 06/12] coresight tmc: Expose DBA and AXICTL

Expose DBALO,DBAHI and AXICTL registers Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-tmc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresi

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