[PATCH] arm64: Fix incorrect per-cpu usage for boot CPU

;sta...@vger.kernel.org> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/smp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kernel/s

Re: [PATCH V2 5/6] coresight: adding sink parameter to function coresight_build_path()

On 20/07/16 21:38, Mathieu Poirier wrote: Up to now function coresight_build_path() was counting on a sink to have been selected (from sysFS) prior to being called. This patch adds a string argument so that a sink matching the argument can be selected. static int

[PATCH] [4.7] arm64: Honor nosmp kernel command line option

;) Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: James Morse <james.mo...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/smp.c | 7 +++ 1 file ch

Re: [RFCv2 4/4] perf: util: support sysfs supported_cpumask file

On 15/07/16 11:08, Mark Rutland wrote: For system PMUs, the perf tools have long expected a cpumask file under sysfs, describing the single CPU which they support events being opened/handled on. Prior patches in this series have reworked this support to support multiple CPUs in a mask, as is

Re: [PATCH 01/10] coresight: etm-perf: pass struct perf_event to source::enable/disable()

On 18/07/16 20:51, Mathieu Poirier wrote: With this commit [1] address range filter information is now found in the struct hw_perf_event::addr_filters. As such pass the event itself to the coresight_source::enable/disable() functions so that both event attribute and filter can be accessible for

Re: [PATCH 03/10] coresight: etm-perf: configuring filters from perf core

On 18/07/16 20:51, Mathieu Poirier wrote: This patch implements the required API needed to access and retrieve range and start/stop filters from the perf core. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 146

[PATCH] coresight: Use local coresight_desc instances

a needless dynamic allocation and wasting the memory(which will only be free'd when the device is destroyed). Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtracing/coresight/coresight-etb10.c | 20 ++--

Re: [PATCH v6] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs

On 28/06/16 16:33, Catalin Marinas wrote: On Tue, Jun 21, 2016 at 12:12:36PM +0100, Suzuki K. Poulose wrote: +#define CPUINFO_ATTR_RO(_name) \ + static ssize_t show_##_name(struct device *dev

[PATCH 0/8] arm64: Work around for mismatched cache line size

K Poulose (8): arm64: Set the safe value for L1 icache policy arm64: Use consistent naming for errata handling arm64: Rearrange CPU errata workaround checks arm64/insn: Add helpers for pc relative address offsets arm64: alternative: Add support for patching adrp instructions arm64

[PATCH 4/8] arm64/insn: Add helpers for pc relative data processing instructions

.@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/insn.h | 5 + arch/arm64/kernel/insn.c | 23 +++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/i

[PATCH 1/8] arm64: Set the safe value for L1 icache policy

arinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/kernel/cpufeature.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git

[PATCH 3/8] arm64: Rearrange CPU errata workaround checks

ave initialised the system wide CPU feature values. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.co

[PATCH 4/8] arm64/insn: Add helpers for pc relative address offsets

.@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/insn.h | 5 + arch/arm64/kernel/insn.c | 23 +++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/i

[PATCH 5/8] arm64: alternative: Add support for patching adrp instructions

dea...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/alternative.c | 13 + 1 file changed, 13 in

[PATCH 2/8] arm64: Use consistent naming for errata handling

ect the same. 2) verify_local_cpu_errata() => verify_local_cpu_errata_workarounds() Use errata_workarounds instead of _errata. Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 4 ++-- arch/arm64/kernel/cpu_errata.c | 4 ++-- arch/

[PATCH 7/8] arm64: Refactor sysinstr exception handling

it a bit more reader friendly. Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arc

[PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

than the system wide), when the system wide feature may not be accessible. Provide another helper which will fetch cache line size on the current CPU. Cc: James Morse <james.mo...@arm.com> Cc: Geoff Levand <ge...@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm

[PATCH 8/8] arm64: Work around systems with mismatched cache line sizes

...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/assembler.h | 25 +++-- arch/arm64/include/asm/cpufeature.h | 4 +++- arch/arm64/include/asm/esr.h| 8 a

[PATCH 0/8] arm64: Work around for mismatched cache line size

K Poulose (8): arm64: Set the safe value for L1 icache policy arm64: Use consistent naming for errata handling arm64: Rearrange CPU errata workaround checks arm64/insn: Add helpers for pc relative address offsets arm64: alternative: Add support for patching adrp instructions arm64

[PATCH v9] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs

lug notifiers, kobject changes ] Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V8: - Handle sysfs group addition/removal gracefully. Changes since V7: - Remove unnecessary clean up cpuinfo_regs_init Changes since V6: - Introduce regs/identification hierarc

Re: [PATCH V4 6/6] coresight: etm-perf: incorporating sink definition from cmd line

On 04/08/16 17:53, Mathieu Poirier wrote: Now that PMU specific configuration is available as part of the event, lookup the sink identified by users from the perf command line and build a path from source to sink. With this functionality it is no longer required to select a sink in a separate

[PATCH v7] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs

lug notifiers, kobject changes ] Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V6: - Introduce regs/identification hierarchy(using kobject for the added level) - Use the register names as in ARM ARM (i.e, midr => midr_el1) Changes since V5: - Add hotplug notif

Re: [PATCH 4/7] bus: arm-cci: add missing of_node_put after calling of_parse_phandle

On 01/07/16 10:41, Peter Chen wrote: of_node_put needs to be called when the device node which is got from of_parse_phandle has finished using. Cc: Will Deacon <will.dea...@arm.com> Cc: Suzuki K Poulose <suzuki.poul...@arm.com> Signed-off-by: Peter Chen <peter.c...@nxp.com>

Re: [PATCH v7] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs

On 01/07/16 14:01, Catalin Marinas wrote: On Thu, Jun 30, 2016 at 06:36:44PM +0100, Suzuki K. Poulose wrote: From: Steve Capper <steve.cap...@linaro.org> It can be useful for JIT software to be aware of MIDR_EL1 and REVIDR_EL1 to ascertain the presence of any core errata that could affec

[PATCH v8] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs

lug notifiers, kobject changes ] Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V7: - Remove unnecessary clean up cpuinfo_regs_init Changes since V6: - Introduce regs/identification hierarchy(using kobject for the added level) - Use the register names as in ARM

Re: [PATCH] coresight: STM: Balance enable/disable

Poirier <mathieu.poir...@linaro.org> Reviewed-by: Chunyan Zhang <zhang.chun...@linaro.org> Reported-by: Robert Walker <robert.wal...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Greg, Without this patch, the coresight STM IP can only be used for one tr

[PATCH] coresight: STM: Balance enable/disable

re...@linuxfoundation.org> Cc: sta...@vger.kernel.org # 4.7+ Acked-by: Mathieu Poirier <mathieu.poir...@linaro.org> Reviewed-by: Chunyan Zhang <zhang.chun...@linaro.org> Reported-by: Robert Walker <robert.wal...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Gre

Re: [PATCH 4/8] arm64: insn: Add helpers for adrp offsets

On 18/08/16 15:47, Marc Zyngier wrote: Hi Suzuki, On 18/08/16 14:10, Suzuki K Poulose wrote: Adds helpers for decoding/encoding the PC relative addresses for adrp. This will be used for handling dynamic patching of 'adrp' instructions in alternative code patching. Cc: Mark Rutland <mark.r

Re: [PATCH] usb: gadget: configs: plug memory leak

On 28/02/17 10:55, John Keeping wrote: When binding a gadget to a device, "name" is stored in gi->udc_name, but this does not happen when unregistering and the string is leaked. Signed-off-by: John Keeping --- drivers/usb/gadget/configfs.c | 1 + 1 file changed, 1

Re: [PATCH 2/2] arm64: Use static keys for CPU features

On 02/09/16 16:52, Catalin Marinas wrote: On Fri, Aug 26, 2016 at 10:22:13AM +0100, Suzuki K. Poulose wrote: On 25/08/16 18:26, Catalin Marinas wrote: Just a heads up. I have a patch [1] which moves the "check_local_cpu_errata()" around to smp_prepare_boot_cpu(). This patch sh

[PATCH v3 5/9] arm64: insn: Add helpers for adrp offsets

mari...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/insn.h | 11 ++- arch/arm64/kernel/insn.c | 13 + 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/a

[PATCH v3 3/9] arm64: Rearrange CPU errata workaround checks

ave initialised the system wide CPU feature values. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.co

[PATCH v3 2/9] arm64: Use consistent naming for errata handling

ect the same. 2) verify_local_cpu_errata() => verify_local_cpu_errata_workarounds() Use errata_workarounds instead of _errata. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuk

[PATCH v3 1/9] arm64: Set the safe value for L1 icache policy

arinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/kernel/cpufeature.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git

[PATCH v3 6/9] arm64: alternative: Add support for patching adrp instructions

dea...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/alternative.c | 15 +++ 1 file changed

[PATCH v3 7/9] arm64: Introduce raw_{d,i}cache_line_size

Geoff Levand <ge...@infradead.org> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/assembler.h | 24 +++

[PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/assembler.h | 25 +++-- arch/arm64/include/asm/cpufeature.h |

[PATCH v3 8/9] arm64: Refactor sysinstr exception handling

it a bit more reader friendly. Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arc

[PATCH v3 0/9] arm64: Work around for mismatched cache line size

field defintions. - Added a patch to disallow silent patching of unhandled pc relative instructions in alternative code patching. [1] http://marc.info/?l=linux-arm-kernel=147263959504998=2 Suzuki K Poulose (9): arm64: Set the safe value for L1 icache policy arm64: Use consistent naming

[PATCH v3 4/9] arm64: alternative: Disallow patching instructions using literals

<marc.zyng...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Suggested-by: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> ---

Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

On 05/09/16 11:10, Ard Biesheuvel wrote: On 5 September 2016 at 10:58, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: +/* + * read_ctr - read CTR_EL0. If the system has mismatched + * cache line sizes, provide the system wide safe value. + */ + .macro read_ctr, reg +alternative_

Re: [PATCH V7 5/5] perf tools: adding sink configuration for cs_etm PMU

On 31/08/16 15:14, Mathieu Poirier wrote: On 31 August 2016 at 03:37, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: On 30/08/16 17:19, Mathieu Poirier wrote: Using the PMU::set_drv_config() callback to enable the CoreSight sink that will be used for the trace session.

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

On 26/08/16 18:00, Catalin Marinas wrote: On Fri, Aug 26, 2016 at 05:16:27PM +0100, Will Deacon wrote: On Fri, Aug 26, 2016 at 02:08:01PM +0100, Suzuki K Poulose wrote: On 26/08/16 14:04, Suzuki K Poulose wrote: It might be worth looking to see if we can pass the ctr as an extra parameter

Re: [PATCH V7 5/5] perf tools: adding sink configuration for cs_etm PMU

On 30/08/16 17:19, Mathieu Poirier wrote: Using the PMU::set_drv_config() callback to enable the CoreSight sink that will be used for the trace session. +int cs_etm_set_drv_config(struct perf_evsel_config_term *term) +{ + int ret; + char enable_sink[ENABLE_SINK_MAX]; + +

Re: [PATCH v3] Added perf functionality to mmdc driver

On 17/08/16 20:42, Zhengyu Shen wrote: MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64 and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6 QuadPlus devices, but this driver only

Re: [PATCH v3] Added perf functionality to mmdc driver

On 17/08/16 20:42, Zhengyu Shen wrote: MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64 and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6 QuadPlus devices, but this driver only

[PATCH v4 6/9] arm64: alternative: Add support for patching adrp instructions

dea...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/alternative.c | 15 +++ 1 file changed

[PATCH v4 7/9] arm64: Introduce raw_{d,i}cache_line_size

Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Acked-by: James Morse <james.mo...@arm.com> Reviewed-by: Geoff Levand <ge...@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/assembler.h | 24 +++

[PATCH v4 0/9] arm64: Work around for mismatched cache line size

-kernel=147263959504998=2 Suzuki K Poulose (9): arm64: Set the safe value for L1 icache policy arm64: Use consistent naming for errata handling arm64: Rearrange CPU errata workaround checks arm64: alternative: Disallow patching instructions using literals arm64: insn: Add helpers for adrp

[PATCH v4 4/9] arm64: alternative: Disallow patching instructions using literals

<marc.zyng...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Suggested-by: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> ---

[PATCH v4 1/9] arm64: Set the safe value for L1 icache policy

arinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/kernel/cpufeature.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git

[PATCH v4 5/9] arm64: insn: Add helpers for adrp offsets

mari...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/insn.h | 11 ++- arch/arm64/kernel/insn.c | 13 + 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/a

[PATCH v4 3/9] arm64: Rearrange CPU errata workaround checks

ave initialised the system wide CPU feature values. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.co

[PATCH v4 2/9] arm64: Use consistent naming for errata handling

ect the same. 2) verify_local_cpu_errata() => verify_local_cpu_errata_workarounds() Use errata_workarounds instead of _errata. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Acked-by: Andre Przywara <andre.przyw...@arm.com> Signed-off-by: Suzuk

[PATCH v4 8/9] arm64: Refactor sysinstr exception handling

it a bit more reader friendly. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Acked-by: Andre Przywara <andre.przyw...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arc

[PATCH v4 9/9] arm64: Work around systems with mismatched cache line sizes

...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/assembler.h | 24 ++-- arch/arm64/include/asm/cpufeature.h | 3 ++- arch/arm64/include/asm/esr.h| 8 a

Re: [PATCH] arm-cci: add cci_enable_port_for_self() declaration in arm-cci.h

On 12/09/16 11:33, Baoyou Xie wrote: We get 1 warning when building kernel with W=1: drivers/bus/arm-cci.c:2027:25: warning: no previous prototype for 'cci_enable_port_for_self' [-Wmissing-prototypes] In fact, this function is used in a few files, but should be declared in a header file. So

[PATCH] coresight: tmc: Cleanup operation mode handling

mathieu's coresight/next tree [1] https://git.linaro.org/kernel/coresight.git next Reported-by: Venkatesh Vivekanandan <venkatesh.vivekanan...@broadcom.com> Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtrac

Re: [PATCH] coresight: tmc: fix for trace collection bug in sysFS mode

On 14/09/16 12:30, Venkatesh Vivekanandan wrote: On Wed, Sep 14, 2016 at 3:26 PM, Suzuki K Poulose <suzuki.poul...@arm.com <mailto:suzuki.poul...@arm.com>> wrote: On 13/09/16 16:41, Mathieu Poirier wrote: On 13 September 2016 at 06:20, Venkatesh

Re: [PATCH] coresight: tmc: fix for trace collection bug in sysFS mode

On 13/09/16 16:41, Mathieu Poirier wrote: On 13 September 2016 at 06:20, Venkatesh Vivekanandan wrote: tmc_etb_dump_hw is never called in sysFS mode to collect trace from hardware, because drvdata->mode is set to CS_MODE_DISABLED at tmc_disable_etf/etr_sink

Re: [PATCH] coresight: tmc: Cleanup operation mode handling

On 19/09/16 17:59, Suzuki K Poulose wrote: On 16/09/16 18:07, Mathieu Poirier wrote: On 14 September 2016 at 07:53, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: Cheers Suzuki IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be priv

Re: [PATCH] coresight: tmc: Cleanup operation mode handling

On 16/09/16 18:07, Mathieu Poirier wrote: On 14 September 2016 at 07:53, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: The mode of operation of the TMC tracked in drvdata->mode is defined as a local_t type. This is always checked and modified under the drvdata->spinlock and he

[RESEND] [PATCH 0/8] arm64: Work around for mismatched cache line size

K Poulose (8): arm64: Set the safe value for L1 icache policy arm64: Use consistent naming for errata handling arm64: Rearrange CPU errata workaround checks arm64: insn: Add helpers for adrp offsets arm64: alternative: Add support for patching adrp instructions arm64: Introduce raw_{d,i

[PATCH 5/8] arm64: alternative: Add support for patching adrp instructions

dea...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/kernel/alternative.c | 13 + 1 file changed, 13 in

[PATCH 8/8] arm64: Work around systems with mismatched cache line sizes

...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/assembler.h | 25 +++-- arch/arm64/include/asm/cpufeature.h | 4 +++- arch/arm64/include/asm/esr.h| 8 a

[PATCH 7/8] arm64: Refactor sysinstr exception handling

it a bit more reader friendly. Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arc

[PATCH 1/8] arm64: Set the safe value for L1 icache policy

arinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/kernel/cpufeature.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git

[PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

than the system wide), when the system wide feature may not be accessible. Provide another helper which will fetch cache line size on the current CPU. Cc: James Morse <james.mo...@arm.com> Cc: Geoff Levand <ge...@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm

[PATCH 3/8] arm64: Rearrange CPU errata workaround checks

ave initialised the system wide CPU feature values. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.co

[PATCH 2/8] arm64: Use consistent naming for errata handling

ect the same. 2) verify_local_cpu_errata() => verify_local_cpu_errata_workarounds() Use errata_workarounds instead of _errata. Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 4 ++-- arch/arm64/kernel/cpu_errata.c | 4 ++-- arch/

[PATCH 4/8] arm64: insn: Add helpers for adrp offsets

mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/insn.h | 4 arch/arm64/kernel/insn.c | 13 + 2 files changed, 17 insertions(+) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

On 26/08/16 14:04, Suzuki K Poulose wrote: On 26/08/16 12:03, Ard Biesheuvel wrote: Hello Suzuki, For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0 via read_system_reg), we keep track of the pointer to table entry for CTR_EL0 in the CPU feature infrastructure

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

On 26/08/16 12:03, Ard Biesheuvel wrote: Hello Suzuki, For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0 via read_system_reg), we keep track of the pointer to table entry for CTR_EL0 in the CPU feature infrastructure. IIUC it is the runtime sorting of the

Re: [PATCH 2/2] arm64: Use static keys for CPU features

, otherwise the compiler generates the bitmap test. Because of the early call to static_branch_enable() via check_local_cpu_errata() -> update_cpu_capabilities(), the jump labels are initialised in cpuinfo_store_boot_cpu(). Cc: Will Deacon <will.dea...@arm.com> Cc: Suzuki K. Poulose <

[PATCH v2 7/9] arm64: Introduce raw_{d,i}cache_line_size

Geoff Levand <ge...@infradead.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/assembler.h | 24 arch/arm64/kernel/hibernate-asm.S | 2 +- arch/arm64/kernel/relocate_kernel.S | 2 +- 3 files changed, 22 insertio

[PATCH v2 8/9] arm64: Refactor sysinstr exception handling

it a bit more reader friendly. Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes sin

[PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/assembler.h | 25 +++-- arch/arm64/include/asm/cpufeature.h | 4 +++- arch/arm64/include/asm/esr.h| 8 a

[PATCH v2 5/9] arm64: insn: Add helpers for adrp offsets

mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V1: - Replace adr_adrp with seperate handlers for adr and adrp (Marc Zyngier) --- arch/arm64/include/asm/insn.h | 11 ++- arch/arm64/kernel/insn.c | 13 + 2 files chan

[PATCH v2 6/9] arm64: alternative: Add support for patching adrp instructions

dea...@arm.com> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- Changes since V1: - Add align_down macro. Couldn't find the best place to

[PATCH v2 2/9] arm64: Use consistent naming for errata handling

ect the same. 2) verify_local_cpu_errata() => verify_local_cpu_errata_workarounds() Use errata_workarounds instead of _errata. Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 4 ++-- arch/arm64/kernel/cpu_errata.c | 4 ++-- arch/

[PATCH v2 1/9] arm64: Set the safe value for L1 icache policy

arinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/kernel/cpufeature.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git

[PATCH v2 4/9] arm64: alternative: Disallow patching instructions using literals

<marc.zyng...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Suggested-by: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> ---

[PATCH v2 3/9] arm64: Rearrange CPU errata workaround checks

ave initialised the system wide CPU feature values. Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Andre Przywara <andre.przyw...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.co

[PATCH v2 0/9] arm64: Work around for mismatched cache line size

. Suzuki K Poulose (9): arm64: Set the safe value for L1 icache policy arm64: Use consistent naming for errata handling arm64: Rearrange CPU errata workaround checks arm64: alternative: Disallow patching instructions using literals arm64: insn: Add helpers for adrp offsets arm64

Re: [PATCH 5/8] arm64: alternative: Add support for patching adrp instructions

On 22/08/16 12:45, Ard Biesheuvel wrote: On 18 August 2016 at 15:10, Suzuki K Poulose <suzuki.poul...@arm.com> wrote: adrp uses PC-relative address offset to a page (of 4K size) of a symbol. If it appears in an alternative code patched in, we should adjust the offset to reflect the a

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

On 22/08/16 11:00, Will Deacon wrote: On Thu, Aug 18, 2016 at 02:10:30PM +0100, Suzuki K Poulose wrote: On systems with mismatched i/d cache min line sizes, we need to use the smallest size possible across all CPUs. This will be done by fetching the system wide safe value from CPU feature

Re: [PATCH 5/8] arm64: alternative: Add support for patching adrp instructions

On 22/08/16 12:19, Will Deacon wrote: On Thu, Aug 18, 2016 at 02:10:29PM +0100, Suzuki K Poulose wrote: adrp uses PC-relative address offset to a page (of 4K size) of a symbol. If it appears in an alternative code patched in, we should adjust the offset to reflect the address where

Re: [PATCH 7/8] arm64: Refactor sysinstr exception handling

On 22/08/16 13:53, Will Deacon wrote: On Thu, Aug 18, 2016 at 02:10:31PM +0100, Suzuki K Poulose wrote: Right now we trap some of the user space data cache operations based on a few Errata (ARM 819472, 826319, 827319 and 824069). We need to trap userspace access to CTR_EL0, if we detect

Re: [PATCH 8/8] arm64: Work around systems with mismatched cache line sizes

On 22/08/16 14:02, Will Deacon wrote: On Thu, Aug 18, 2016 at 02:10:32PM +0100, Suzuki K Poulose wrote: Systems with differing CPU i-cache/d-cache line sizes can cause problems with the cache management by software when the execution is migrated from one to another. Usually, the application

[PATCH 1/3] coresight: tmc: Cleanup operation mode handling

mathieu's coresight/next tree [1] https://git.linaro.org/kernel/coresight.git next Reported-by: Venkatesh Vivekanandan <venkatesh.vivekanan...@broadcom.com> Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drivers/hwtrac

[PATCH 3/3] coresight: tmc: Remove duplicate memset

The tmc_etr_enable_hw() fills the buffer with 0's before enabling the hardware. So, we don't need an explicit memset() in tmc_enable_etr_sink_sysfs() before calling the tmc_etr_enable_hw(). This patch removes the explicit memset from tmc_enable_etr_sink_sysfs. Signed-off-by: Suzuki K Poulose

[PATCH 2/3] coresight: tmc: Get rid of mode parameter for helper routines

Get rid of the superfluous mode parameter and the check for the mode in tmc_etX_enable_sink_{perf/sysfs}. While at it, also remove the unnecessary WARN_ON() checks. Cc: Mathieu Poirier <mathieu.poir...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- drive

Re: [PATCH] coresight: tmc: implementing TMC-ETR AUX space API

On 19/09/16 22:14, Mathieu Poirier wrote: This patch implements the AUX area interfaces required to use the TMC-ETR (configured to work in scatter-gather mode) from the Perf sub-system. Some of this work was inspired from the original implementation done by Pratik Patel at CodeAurora. Hi

Re: [PATCH 3/3] arm64/fpsimd: Use ID_AA64PFR0_EL1_.* macros

On 03/09/15 19:12, Alexander Kuleshov wrote: The 26d75e67c commit (arm64/cpufeature.h: Add macros for a cpu features testing) provides set of macros for the testing processor's FP and advanced SIMD features. Let's use these macros instead of direct calculation. Signed-off-by: Alexander

Re: [PATCH 2/3] arm64/setup: Use ID_AA64ISAR0_EL1_.* macros

On 03/09/15 19:12, Alexander Kuleshov wrote: The 26d75e67c commit (arm64/cpufeature.h: Add macros for a cpu features testing) provides set of macros for the testing processor's crypto features. Let's use these macros instead of direct calculation. Signed-off-by: Alexander Kuleshov

[PATCH v3 2/2] arm64: Support systems without FP/ASIMD

m.com> Cc: Christoffer Dall <christoffer.d...@linaro.org> Cc: Marc Zyngier <marc.zyng...@arm.com> Cc: Ard Biesheuvel <ard.biesheu...@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpucaps.h| 3 ++- arch/arm64/include/asm

[PATCH v3 1/2] arm64: Add hypervisor safe helper for checking constant capabilities

c: Catalin Marinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com> --- arch/arm64/include/asm/cpufeature.h | 19 --- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/process.c |

[PATCH v3 0/2] arm64: Support systems without FP/ASIMD

users with constant caps should use the new API to make use of static_keys. - Removed a dedicated static_key used in irqchip-gic-v3.c for Cavium errata with the new API. Applies on v4.9-rc4 + [1] (which is pushed for rc5) [1] http://marc.info/?l=linux-arm-kernel=147819889813214=2 Suzuki K

Re: [PATCH V4 01/10] acpi: apei: read ack upon ghes record consumption

On 21/10/16 18:30, Tyler Baicar wrote: A RAS (Reliability, Availability, Serviceability) controller may be a separate processor running in parallel with OS execution, and may generate error records for consumption by the OS. If the RAS controller produces multiple error records, then they may be

Re: [PATCH] coresight: reset "enable_sink" flag when need be

mechanism to ensure that the "enabled" sink is the one perf really enabled for us. But there is nothing much we could do and should rely on the user to do it right for us. So, with the changes to description : Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com>

<    4   5   6   7   8   9   10   11   12   13   >