This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- ad
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- None
Changes
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- sort the list of_dwc3_simple_match (Doug)
drivers/us
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
usb: dwc3
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- rebase on top of balbi t
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- rebase on top of balbi t
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
C
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- sort the list of_dwc3_simple_match
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v4:
- rebase
Dear Sergei,
On 05/27/2016 07:54 PM, Sergei Shtylyov wrote:
Hello.
On 5/27/2016 2:31 PM, William Wu wrote:
This patch documents the device tree documentation required for
Documents the documentation? :-)
Ah, my commit log seems a little weird. I'll corrcet it next patch.
Thanks
Dear Heiko,
On 06/20/2016 10:44 PM, Heiko Stübner wrote:
Hi William,
Am Freitag, 17. Juni 2016, 17:18:59 schrieb William Wu:
On 06/17/2016 07:15 AM, Heiko Stübner wrote:
Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
This patch adds the devicetree documentation required
Dear Heiko,
On 06/17/2016 07:15 AM, Heiko Stübner wrote:
Hi William,
Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate
Dear Heiko,
On 06/25/2016 03:50 AM, Heiko Stuebner wrote:
Hi William,
Am Dienstag, 21. Juni 2016, 17:11:44 schrieb William Wu:
On 06/20/2016 10:44 PM, Heiko Stübner wrote:
Am Freitag, 17. Juni 2016, 17:18:59 schrieb William Wu:
On 06/17/2016 07:15 AM, Heiko Stübner wrote:
Am Donnerstag, 2
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- None
Documentation/devi
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- sort the list of_dwc3_simple_match (Doug)
drivers/usb/dwc3/dwc3-of-simple.c |
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- None
Documentation/devi
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
usb: dwc3
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- add a
be reset to
default 0 after the core reset. Dump GUCTL1 reg from
debugfs is more convenient for us.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- add commit log
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff
Dear Felipe,
On 05/13/2016 05:37 PM, Felipe Balbi wrote:
Hi,
William Wu <william...@rock-chips.com> writes:
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simpl
This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- add ro
On 05/13/2016 06:05 PM, William Wu wrote:
GUCTL1 reg has some useful functions which can be
written by user. For rockchip platform, we set
GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK (bit26, applicable
for the core is programmed to operate in 2.0 device
only) to 1 in bootrom, and after start the kernel
be reset to
default 0 after the core reset. Dump GUCTL1 reg from
debugfs is more convenient for us.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v2:
- add commit log
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff
request correctly.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/gadget/composite.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index d67de0d..eb64848 100644
Dear Felipe & Doug,
Thanks for your proposal. It's a good idea to sort the list.
I'll fix it next patch version.
On 05/10/2016 03:14 PM, Felipe Balbi wrote:
Hi,
Doug Anderson <diand...@google.com> writes:
William,
On Mon, May 9, 2016 at 4:46 AM, William Wu <wi
, even if they aren't as fortunate as me to have been CC'd on your
patch directly.
Actually, I don't know the linux-rockc...@lists.infradead.org before.
I'll add the list in CC next patch version.
Thanks~
On Mon, May 09, 2016 at 07:46:14PM +0800, William Wu wrote:
Signed-off-by: William Wu <willia
Dear Felipe,
On 05/10/2016 04:11 PM, Felipe Balbi wrote:
Hi William,
William Wu <william...@rock-chips.com> writes:
Dear Felipe & Doug,
Thanks for your proposal. It's a good idea to sort the list.
I'll fix it next patch version.
cool, thanks.
ps: top-posting
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c
b/drivers/usb/dwc3/dwc3-of-simple.c
index 9743353..1f3665b 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Documentation/devicetree/bindings/usb/dw
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Documentation/devicetree/bindings/usb/dw
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (4):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy interface
to the corresponding value according to the usb2
phy interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
drivers/usb/dwc3/core.c| 13 +
drivers/usb/dwc3/core.h
Signed-off-by: William Wu <william...@rock-chips.com>
---
drivers/usb/dwc3/core.h| 1 +
drivers/usb/dwc3/debugfs.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e15e307..f268869 100644
--- a/drivers/usb/dwc3/core.h
+++ b/d
On 05/09/2016 08:10 PM, Felipe Balbi wrote:
William Wu <william...@rock-chips.com> writes:
Thanks Felipe Balbi and Greg KH. I'm really sorry that I forgot to
add changelog.
Signed-off-by: William Wu <william...@rock-chips.com>
no changelog = no commit, sorry. Why do you
On 05/09/2016 08:18 PM, Felipe Balbi wrote:
Hi,
William Wu <william...@rock-chips.com> writes:
Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
this needs a quirk_ prefix...
Yes, maybe a quirk is more proper. As you mentioned,
the PHYIf can be configured
Hi Felipe,
On 05/24/2016 05:32 PM, Felipe Balbi wrote:
Hi,
William Wu <william...@rock-chips.com> writes:
This patch documents the device tree documentation required for
Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys.
It could operate in device mode (SS, HS, FS) an
Hi Felipe & Rob,
On 05/25/2016 04:04 PM, Felipe Balbi wrote:
Hi,
William Wu <william...@rock-chips.com> writes:
Hi Felipe,
On 05/24/2016 05:32 PM, Felipe Balbi wrote:
Hi,
William Wu <william...@rock-chips.com> writes:
This patch documents the device tree documentation requi
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v8:
- configure utmi interface via phy_type property in DT (Heiko, Rob Herring)
- add Acked-by (Rob Herring)
- m
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- change comp
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v9:
- None
Changes in v8:
- configure utmi interface via phy_type property in DT (Heiko, Rob Herring)
- add A
, but not use the
generic of glue layer which merely enable some clocks
and populate its children.
William Wu (5):
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi interface configurable
usb: dwc3: add dis_del_phy_power_chg_quirk
usb: dwc3: rockchip: add devicetree bindings
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v10:
- None
Changes in v9:
- None
Changes in v8:
- configure utmi interface via phy_type property in DT (Heiko,
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
than use the
generic of glue layer which merely enable some clocks
and populate its children.
William Wu (5):
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi interface configurable
usb: dwc3: add dis_del_phy_power_chg_quirk
usb: dwc3: rockchip: add devicetree bindings
. And it need to reconfigure USB PHY interface of DWC3
core after deassert DWC3 controller reset.
The current driver supports Host only and Peripheral Only well, for
now, we will add support for OTG after we have it all stabilized.
Signed-off-by: William Wu <william...@rock-chips.com>
---
drive
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
. And it need to reconfigure USB PHY interface of DWC3
core after deassert DWC3 controller reset.
The current driver supports Host only and Peripheral Only well, for
now, we will add support for OTG after we have it all stabilized.
Signed-off-by: William Wu <william...@rock-chips.com>
---
C
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: make usb2 phy utmi
), the
default PHYIF configuration value is fault, so we need to
reconfigure it by software.
And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to the
UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v7:
- None
Changes in v6:
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- change compatible from "ro
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v7:
- None
Changes in v6:
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
Dear Heiko,
On 06/29/2016 12:41 AM, Heiko Stuebner wrote:
Hi William,
Am Dienstag, 28. Juni 2016, 11:18:04 schrieb William Wu:
So about the usb3 controller clk management, I think it should contain
the following clk:
1. aclk_usb3otg1
2. aclk_usb3otg0
3. aclk_usb3_grf
correct
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
C
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v6:
- use '-' instead of '_'
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v6:
- None
Changes in v5:
- change compatible from "rockchip,dwc3" to "
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v6:
- use '-' instead of '_'
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v6:
- use '-' i
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- change compatible from "rockchip,dwc3" to "rockchip,rk3399-dwc3&qu
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- None
Changes in v4:
-
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
---
C
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- None
Changes in v4:
-
configuration value is fault, so we need to
reconfigure it by software.
And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v5:
- None
Changes
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add
Dear Heiko,
On 06/30/2016 08:15 PM, Heiko Stuebner wrote:
Hi William,
Am Donnerstag, 30. Juni 2016, 19:16:40 schrieb William Wu:
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could
Dear Rob,
On 07/01/2016 10:38 AM, Rob Herring wrote:
On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote:
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3
Dear Rob,
On 07/01/2016 10:32 AM, Rob Herring wrote:
On Thu, Jun 30, 2016 at 07:12:53PM +0800, William Wu wrote:
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input
and we don't need to add xhci node separately, but just add dwc3
node like this:
usbdrd3_0: usb@fe80 {
compatible = "rockchip,rk3399-dwc3";
..
ranges;
status = "disabled";
usbdrd_dwc3_0: dwc3@fe80 {
compatible = "snps,dwc3";
reg = <0x0 0x
Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.
Signed-off-by: William Wu <william...@rock-chips.com>
---
Changes in v11:
- add compatible in dwc3-of-simple.c, and remove dwc3-rockchip.c (balbi)
Changes
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v11:
- None
Changes in v10:
- None
Changes in v9:
- None
Changes in v8:
- configure utmi interface via phy_t
) and Peripheral
Only configurations.
The current driver supports Host only and Peripheral Only,
for now, and we can add support for DRD after dwc3 driver
adds generic handling of DRD.
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip rk3399
usb: dwc3: add dis_u2_freeclk_exists_quirk
This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).
Signed-off-by: William Wu <william...@rock-chips.com>
Acked-b
From: William wu <william...@rock-chips.com>
The commit 4ac53087d6d4 ("usb: xhci: plat: Create both
HCDs before adding them") move add hcd to the end of
probe, this cause hcc_params uninitiated, because xHCI
driver sets hcc_params in xhci_gen_setup() called from
usb_add_hcd().
T
-off-by: William Wu <w...@rock-chips.com>
---
drivers/phy/phy-rockchip-inno-usb2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/phy-rockchip-inno-usb2.c
b/drivers/phy/phy-rockchip-inno-usb2.c
index ecfd7d1..8f2d2b6 100644
--- a/drivers/phy/phy-rockchip-inn
extcon notifier to
send USB charger types to power driver.
- Support PHY suspend for power management.
- Support OTG Host only mode.
Signed-off-by: William Wu <w...@rock-chips.com>
---
Changes in v3:
- split the clock fix into a separate patch
Changes in v2:
- remove wakelock
drivers/p
This series add support for rk3399 USB2 PHY0 and PHY1 OTG port.
rk3399 has two USB2 PHYs, and each USB2 PHY is comprised of one
Host port and one OTG port. We have supported Host port before,
and try to support OTG port now.
Test on rk3399-evb board.
William Wu (2):
phy: rockchip-inno-usb2
Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can
be used for USB2.0 part of USB3.0 OTG controller.
Signed-off-by: William Wu <w...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 21 +
1 file c
This series try to correct the 480MHz output clock of USB2 PHY
clk_ops callback and fix the delay time. It aims to make the
480MHz clock gate more sensible and stable.
Tested on rk3366/rk3399 EVB board.
William Wu (2):
phy: rockchip-inno-usb2: correct clk_ops callback
phy: rockchip-inno-usb2
.
And the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct
clk_ops callback") used prepare callbacks instead of enable
callbacks to support gate a clk if the operation may sleep. So
we can switch from delay to sleep functions.
Signed-off-by: William Wu <w...@rock-chips.com>
---
Chan
pt latency is not sensible.
The 480MHz output clock should be handled in prepare callbacks
which support gate a clk if the operation may sleep.
Signed-off-by: William Wu <w...@rock-chips.com>
---
Changes in v3:
- None
Changes in v2:
- None
drivers/phy/phy-rockchip-inno-usb2.c | 12 ++--
1
uot;waiting".
Signed-off-by: William Wu <w...@rock-chips.com>
Reviewed-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v4:
- add Reviewed-by and fix a spelling error
Changes in v3:
- None
Changes in v2:
- None
drivers/phy/phy-rockchip-inno-usb2.c | 4 ++--
1 file chan
pt latency is not sensible.
The 480MHz output clock should be handled in prepare callbacks
which support gate a clk if the operation may sleep.
Signed-off-by: William Wu <w...@rock-chips.com>
Reviewed-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v4:
- add Reviewed-by
Changes in v3:
This series try to correct the 480MHz output clock of USB2 PHY
clk_ops callback and fix the delay time. It aims to make the
480MHz clock gate more sensible and stable.
Tested on rk3366/rk3399 EVB board.
William Wu (2):
phy: rockchip-inno-usb2: correct clk_ops callback
phy: rockchip-inno-usb2
This series try to correct the 480MHz output clock of USB2 PHY
clk_ops callback and fix the delay time. It aims to make the
480MHz clock more sensible and stable.
Tested on rk3366/rk3399 EVB board.
William Wu (2):
phy: rockchip-inno-usb2: correct clk_ops callback
phy: rockchip-inno-usb2
.
And the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct
clk_ops callback") used prepare callbacks instead of enable
callbacks to support gate a clk if the operation may sleep. So
we can switch from delay to sleep functions.
Signed-off-by: William Wu <w...@rock-chips.com>
---
Chan
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