generic KVM code that dispatches to kvm_set_spte_gfn(), as
> well as all the architecture specific implementations.
>
> Signed-off-by: Paolo Bonzini
For KVM RISC-V:
Acked-by: Anup Patel
Regards,
Anup
> ---
> arch/arm64/kvm/mmu.c | 34 -
>
On Tue, Mar 5, 2024 at 1:54 AM Björn Töpel wrote:
>
> Conor Dooley writes:
>
> > On Thu, Feb 29, 2024 at 01:10:56PM +0100, Alexandre Ghiti wrote:
> >> For now, we use stop_machine() to patch the text and when we use IPIs for
> >> remote icache flushes (which is emitted in patch_text_nosync()),
rnel.
>
> Fixes: e9efb21fe352 ("riscv: Prepare ptdump for vm layout dynamic addresses")
> Signed-off-by: Alexandre Ghiti
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/mm/ptdump.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions
pping")
> Signed-off-by: Alexandre Ghiti
Quite a few #ifdef but I don't see any better way at the moment. Maybe we can
clean this later. Otherwise looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/include/asm/page.h| 9 +
> arch/riscv/include/asm/pg
y: Alexandre Ghiti
Maybe you should add "Fixes:" tag in commit tag ?
Otherwise it looks good.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/kernel/setup.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/kernel/
;)
Cc: sta...@vger.kernel.org
Signed-off-by: Anup Patel
---
arch/riscv/kernel/smp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index ea028d9e0d24..d44567490d91 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -
On Mon, Apr 12, 2021 at 9:47 PM Jisheng Zhang wrote:
>
> From: Jisheng Zhang
>
> They are not needed after booting, so mark them as __init to move them
> to the __init section.
>
> Signed-off-by: Jisheng Zhang
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
On Mon, Apr 12, 2021 at 9:46 PM Jisheng Zhang wrote:
>
> From: Jisheng Zhang
>
> patch1 removes the non-necessary setup_zero_page()
> patch2 is a trivial improvement patch to move some functions to .init
> section
>
> Then following patches improve self-protection by:
>
> Marking some variables
On Mon, Apr 12, 2021 at 9:47 PM Jisheng Zhang wrote:
>
> From: Jisheng Zhang
>
> The empty_zero_page sits at .bss..page_aligned section, so will be
> cleared to zero during clearing bss, we don't need to clear it again.
>
> Signed-off-by: Jisheng Zhang
Looks good to m
ermissions instead.
>
> Signed-off-by: Jisheng Zhang
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/kernel/module.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/module.c b/arch/ris
On Wed, Mar 31, 2021 at 10:02 PM Jisheng Zhang
wrote:
>
> From: Jisheng Zhang
>
> Allocate PAGE_KERNEL_READ_EXEC(read only, executable) page for kprobes
> insn page. This is to prepare for STRICT_MODULE_RWX.
>
> Signed-off-by: Jisheng Zhang
Looks good to me.
Reviewed-by:
On Wed, Mar 31, 2021 at 10:05 PM Jisheng Zhang
wrote:
>
> From: Jisheng Zhang
>
> Now we can set ARCH_HAS_STRICT_MODULE_RWX for MMU riscv platforms, this
> is good from security perspective.
>
> Signed-off-by: Jisheng Zhang
Looks good to me.
Reviewed-by: Anup
sheng Zhang
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/include/asm/smp.h | 4 ++--
> arch/riscv/kernel/sbi.c | 2 +-
> arch/riscv/kernel/smp.c | 4 ++--
> 3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/ris
ed-off-by: Jisheng Zhang
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/include/asm/syscall.h | 2 +-
> arch/riscv/kernel/syscall_table.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/syscall.h
&g
On Wed, Mar 31, 2021 at 10:01 PM Jisheng Zhang
wrote:
>
> From: Jisheng Zhang
>
> All of these are never modified after init, so they can be
> __ro_after_init.
>
> Signed-off-by: Jisheng Zhang
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> a
c7492..3b7b6e4d025e 100644
> --- a/arch/riscv/mm/ptdump.c
> +++ b/arch/riscv/mm/ptdump.c
> @@ -331,7 +331,7 @@ static int ptdump_show(struct seq_file *m, void *v)
>
> DEFINE_SHOW_ATTRIBUTE(ptdump);
>
> -static int ptdump_init(void)
> +static int __init ptdump_init(void)
> {
> unsigned int i, j;
>
> --
> 2.31.0
>
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Apart from above, looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
to
the guest VCPU whenever the guest VCPU hrtimer event expires.
This patch adds guest VCPU timer implementation along with ONE_REG
interface to access VCPU timer state from user space.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Acked
This patch extends asm/csr.h by adding RISC-V hypervisor extension
related defines.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/csr.h | 89
1 file changed, 89
reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to
userspace tool.
CC: Jonathan Corbet
CC: linux-...@vger.kernel.org
Signed-off-by: Anup Patel
---
Documentation/virt/kvm/api.rst | 193 +++--
1 file changed, 184 insertions(+), 9 deletions(-)
diff --git
which are forwarded to user space because these calls cannot be
implemented in kernel space. In future, when we implement SBI v0.2 for
Guest, we will forward SBI v0.2 experimental and vendor extension calls
to user space.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
and kvm_riscv_vcpu_has_interrupt() function.
The KVM_REQ_VCPU_RESET request will be used by SBI emulation (added
later) to power-up a VCPU in power-off state. The user-space can use
the GET_MPSTATE/SET_MPSTATE ioctls to get/set power state of a VCPU.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed
From: Atish Patra
Add a KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctl interface for floating
point registers such as F0-F31 and FCSR. This support is added for
both 'F' and 'D' extensions.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/kvm/vcpu_exit.c | 76 ++
1 file changed, 76 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c
index dc66be032ad7..1873b8c35101
support]
Signed-off-by: Yifei Jiang
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/asm/kvm_host.h | 12 +
arch/riscv/include/asm/pgtable-bits.h | 1 +
arch/riscv/kvm/Kconfig| 1 +
arch/riscv/kvm/main.c
performance.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 5 +
arch/riscv/kernel/asm-offsets.c | 72 +
arch/riscv/kvm/vcpu.c | 91
This patch implements MMU notifiers for KVM RISC-V so that Guest
physical address space is in-sync with Host physical address space.
This will allow swapping, page migration, etc to work transparently
with KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Add myself as maintainer for KVM RISC-V and Atish as designated reviewer.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git
of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
---
arch/riscv/include/uapi/asm/kvm.h | 53 ++-
arch/riscv/kvm/vcpu.c
() and kvm_arch_vcpu_put() functions
respectively.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 10 +-
arch/riscv/kernel/asm-offsets.c | 78
arch/riscv/kvm/Makefile | 2
-by: Yifei Jiang
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 22 ++
arch/riscv/kernel/asm-offsets.c | 6 +
arch/riscv/kvm/Kconfig| 1 +
arch/riscv/kvm/Makefile | 1
This patch implements VCPU create, init and destroy functions
required by generic KVM module. We don't have much dynamic
resources in struct kvm_vcpu_arch so these functions are quite
simple for KVM RISC-V.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed
Stage2 VMID for each Guest VCPU whenever
VMID changes using VCPU request KVM_REQ_UPDATE_HGATP
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/include/asm/kvm_host.h | 24 ++
arch/riscv/kvm/Makefile | 3
kvm_arch_vcpu_ioctl_run() which is semi-complete and
extended by subsequent patches.
3. Stubs for required arch specific stage2 MMU functions.
Signed-off-by: Anup Patel
Acked-by: Paolo Bonzini
Reviewed-by: Paolo Bonzini
Reviewed-by: Alexander Graf
---
arch/riscv/Kconfig | 1 +
arch
rate patch for FP ONE_REG interface
- Added separate patch for updating MAINTAINERS file
Anup Patel (13):
RISC-V: Add hypervisor extension related CSR defines
RISC-V: Add initial skeletal KVM support
RISC-V: KVM: Implement VCPU create, init and destroy functions
RISC-V: KVM: Implemen
On Wed, Mar 31, 2021 at 2:52 PM Paolo Bonzini wrote:
>
> On 30/03/21 07:48, Anup Patel wrote:
> >
> > It seems Andrew does not want to freeze H-extension until we have
> > virtualization
> > aware interrupt controller (such as RISC-V AIA specification)
On Tue, Mar 30, 2021 at 7:56 AM Guo Ren wrote:
>
> On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
> >
> > On Mon, Mar 29, 2021 at 2:52 PM Guo Ren wrote:
> > >
> > > On Mon, Mar 29, 2021 at 7:31 PM Peter Zijlstra
> > > wrote:
> > > >
> > > > On Mon, Mar 29, 2021 at 01:16:53PM +0200,
On Sat, Jan 23, 2021 at 9:10 AM Palmer Dabbelt wrote:
>
> On Fri, 15 Jan 2021 04:18:29 PST (-0800), Anup Patel wrote:
> > This series adds initial KVM RISC-V support. Currently, we are able to boot
> > Linux on RV64/RV32 Guest with multiple VCPUs.
>
> Thanks. IIUC th
> -Original Message-
> From: Guo Ren
> Sent: 30 March 2021 08:44
> To: Peter Zijlstra
> Cc: linux-riscv ; Linux Kernel Mailing List
> ; linux-c...@vger.kernel.org; linux-arch
> ; Guo Ren ; Will
> Deacon ; Ingo Molnar ; Waiman
> Long ; Arnd Bergmann ; Anup
>
> -Original Message-
> From: Peter Zijlstra
> Sent: 29 March 2021 16:57
> To: Guo Ren
> Cc: linux-riscv ; Linux Kernel Mailing List
> ; linux-c...@vger.kernel.org; linux-arch
> ; Guo Ren ; Will
> Deacon ; Ingo Molnar ; Waiman
> Long ; Arnd Bergmann ;
On Wed, Mar 24, 2021 at 8:33 PM Changbin Du wrote:
>
> In the setup_arch() of riscv, function early_init_dt_verify() has
> been done by parse_dtb(). So no need to call it again. Just directly
> invoke unflatten_device_tree().
>
> Signed-off-by: Changbin Du
> ---
> arch/riscv/kernel/setup.c | 5
On Wed, Mar 24, 2021 at 6:08 PM Peter Zijlstra wrote:
>
> On Wed, Mar 24, 2021 at 05:58:58PM +0530, Anup Patel wrote:
> > On Wed, Mar 24, 2021 at 3:45 PM wrote:
> > >
> > > From: Guo Ren
> > >
> > > This patch introduces a ticket lock impl
con
> Cc: Peter Zijlstra
> Cc: Palmer Dabbelt
> Cc: Anup Patel
> Cc: Arnd Bergmann
> ---
> arch/riscv/Kconfig | 1 +
> arch/riscv/include/asm/Kbuild | 1 +
> arch/riscv/include/asm/spinlock.h | 158
> ---
The RISC-V CPU idle states will be described in under the
/cpus/idle-states DT node in the same way as ARM CPU idle
states.
This patch adds common bindings documentation for both ARM
and RISC-V idle states.
Signed-off-by: Anup Patel
---
.../bindings/{arm => cpu}/idle-states.yaml|
We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test
SBI HSM Supend on QEMU.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig.socs | 3 +++
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
3 files changed, 5 insertions(+)
diff --git
-off-by: Anup Patel
---
MAINTAINERS | 8 +
drivers/cpuidle/Kconfig | 5 +
drivers/cpuidle/Kconfig.riscv | 15 +
drivers/cpuidle/Makefile | 4 +
drivers/cpuidle/cpuidle-sbi.c | 502 ++
5 files changed, 534 insertions(+)
create mode
We add defines related to SBI HSM suspend call and also
update HSM states naming as-per latest SBI specification.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/sbi.h| 27 ++-
arch/riscv/kernel/cpu_ops_sbi.c | 2 +-
2 files changed, 23 insertions(+), 6
The generic power domain related code in PSCI domain driver is largely
independent of PSCI and can be shared with RISC-V SBI domain driver
hence we factor-out this code into dt_idle_genpd.c and dt_idle_genpd.h.
Signed-off-by: Anup Patel
---
drivers/cpuidle/Kconfig | 4
erty in
devicetree/bindings/riscv/cpus.yaml
- Added documentation for "riscv,sbi-suspend-param" DT property in
devicetree/bindings/riscv/idle-states.yaml
Anup Patel (8):
RISC-V: Enable CPU_IDLE drivers
RISC-V: Rename relocate() and make it global
RISC-V: Add arch functions for
/exit.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/suspend.h | 35 +
arch/riscv/kernel/Makefile| 2 +
arch/riscv/kernel/asm-offsets.c | 3 +
arch/riscv/kernel/suspend.c | 86 ++
arch/riscv/kernel/suspend_entry.S | 116
-retentive suspend
so we make it global symbol.
Signed-off-by: Anup Patel
---
arch/riscv/kernel/head.S | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index f5a9bad86e58..9d10f89e8ab7 100644
--- a/arch/riscv/kernel/head.S
+++ b
We force select CPU_PM and provide asm/cpuidle.h so that we can
use CPU IDLE drivers for Linux RISC-V kernel.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 7 +++
arch/riscv/configs/defconfig | 7 +++
arch/riscv/configs/rv32_defconfig | 4 ++--
arch/riscv
On Tue, Mar 16, 2021 at 9:24 PM Rob Herring wrote:
>
> On Sun, Mar 7, 2021 at 8:18 PM Anup Patel wrote:
> >
> > On Sat, Mar 6, 2021 at 4:52 AM Rob Herring wrote:
> > >
> > > On Sun, Feb 21, 2021 at 03:07:57PM +0530, Anup Patel wrote:
> > > > Th
On Wed, Mar 17, 2021 at 10:38 AM Palmer Dabbelt wrote:
>
> On Mon, 15 Mar 2021 04:04:59 PDT (-0700), Anup Patel wrote:
> > The sbi_init() already prints SBI version before detecting
> > various SBI extensions so we don't need to print SBI version
> > for all
by opensbi/bbl, this still causes performance degradation.
>
> Signed-off-by: Zihao Yu
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/kernel/entry.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/ri
On Wed, Mar 17, 2021 at 10:23 AM Palmer Dabbelt
wrote:
>
> On Thu, 11 Mar 2021 08:47:09 PST (-0800), Anup Patel wrote:
> > This series primarily does two things:
> > 1. Allows RISC-V IPI provider to specificy whether IPI operations are
> >suitable for remote TLB flush
We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test
SBI HSM Supend on QEMU.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig.socs | 3 +++
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
3 files changed, 5 insertions(+)
diff --git
The RISC-V CPU idle states will be described in DT under the
/cpus/idle-states DT node. This patch adds the bindings documentation
for riscv-idle-states DT nodes and idle state DT nodes under it.
Signed-off-by: Anup Patel
---
.../devicetree/bindings/riscv/cpus.yaml | 6 +
.../bindings
-off-by: Anup Patel
---
MAINTAINERS | 8 +
drivers/cpuidle/Kconfig | 5 +
drivers/cpuidle/Kconfig.riscv | 15 +
drivers/cpuidle/Makefile | 4 +
drivers/cpuidle/cpuidle-sbi.c | 502 ++
5 files changed, 534 insertions(+)
create mode
The generic power domain related code in PSCI domain driver is largely
independent of PSCI and can be shared with RISC-V SBI domain driver
hence we factor-out this code into dt_idle_genpd.c and dt_idle_genpd.h.
Signed-off-by: Anup Patel
---
drivers/cpuidle/Kconfig | 4
We add defines related to SBI HSM suspend call and also
update HSM states naming as-per latest SBI specification.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/sbi.h| 27 ++-
arch/riscv/kernel/cpu_ops_sbi.c | 2 +-
2 files changed, 23 insertions(+), 6
/exit.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/suspend.h | 35 +
arch/riscv/kernel/Makefile| 2 +
arch/riscv/kernel/asm-offsets.c | 3 +
arch/riscv/kernel/suspend.c | 86 ++
arch/riscv/kernel/suspend_entry.S | 116
-retentive suspend
so we make it global symbol.
Signed-off-by: Anup Patel
---
arch/riscv/kernel/head.S | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index f5a9bad86e58..9d10f89e8ab7 100644
--- a/arch/riscv/kernel/head.S
+++ b
We force select CPU_PM and provide asm/cpuidle.h so that we can
use CPU IDLE drivers for Linux RISC-V kernel.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 7 +++
arch/riscv/configs/defconfig | 7 +++
arch/riscv/configs/rv32_defconfig | 4 ++--
arch/riscv
s
- Added documentation for "cpu-idle-states" DT property in
devicetree/bindings/riscv/cpus.yaml
- Added documentation for "riscv,sbi-suspend-param" DT property in
devicetree/bindings/riscv/idle-states.yaml
Anup Patel (8):
RISC-V: Enable CPU_IDLE drivers
RISC-V: Rename
On Tue, Mar 16, 2021 at 1:59 PM Andrew Waterman
wrote:
>
> On Tue, Mar 16, 2021 at 12:32 AM Anup Patel wrote:
> >
> > On Tue, Mar 16, 2021 at 12:27 PM Jiuyang Liu wrote:
> > >
> > > > As per my understanding, we don't need to explicitly invalidat
pte_t *ptep, pte_t pteval)
> {
>
> if (!pte_present(pteval))
> goto cache_sync_done;
>
> if (pte_present(*ptep) && (pte_pfn(*ptep) == pte_pfn(pteval)))
> goto cache_sync_done;
>
> __update_cache(addr, pteval);
> c
+Alex
On Tue, Mar 16, 2021 at 9:20 AM Jiuyang Liu wrote:
>
> This patch inserts SFENCE.VMA after modifying PTE based on RISC-V
> specification.
>
> arch/riscv/include/asm/pgtable.h:
> 1. implement pte_user, pte_global and pte_leaf to check correspond
> attribute of a pte_t.
Adding pte_user(),
-sbi-doc.
This patch extends Linux RISC-V SBI implementation to detect
and use SBI SRST extension.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/include/asm/sbi.h | 24
arch/riscv/kernel/sbi.c | 35 +++
2 files
The sbi_init() already prints SBI version before detecting
various SBI extensions so we don't need to print SBI version
for all detected SBI extensions.
Signed-off-by: Anup Patel
---
arch/riscv/kernel/sbi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv
extension available in the latest
SBI v0.3-draft specification
Changes since v1:
- Updated patch as-per latest SBI SRST extension draft spec where
we have only one SBI call with "reset_type" parameter
Anup Patel (2):
RISC-V: Don't print SBI version for all detected extensions
R
the extended riscv_set_ipi_ops()
will be useful to AIA IMSIC driver as well.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/smp.h | 13 +++--
arch/riscv/kernel/sbi.c | 2 +-
arch/riscv/kernel/smp.c | 10 +-
arch/riscv/mm/cacheflush.c| 2 +-
drivers
adds handle_IPI_noregs() for nested irqchip drivers.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/smp.h | 6 ++
arch/riscv/kernel/smp.c | 20 ++--
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm
allows S-mode software to directly inject IPIs without any
assistance from M-mode runtime firmware.
This patch extends remote TLB flush functions to use IPIs whenever
underlying IPI operations are suitable for remote FENCEs.
Signed-off-by: Anup Patel
---
arch/riscv/mm/tlbflush.c | 62
)
This series also a preparatory series for upcoming RISC-V advanced
interrupt architecture (AIA) support.
These patches can be found in riscv_ipi_imp_v1 branch at
https://github.com/avpatel/linux
Anup Patel (3):
RISC-V: IPI provider should specify if we can use IPI for remote FENCE
RISC-V: Use IPIs
On Wed, Mar 10, 2021 at 8:31 AM Palmer Dabbelt wrote:
>
> On Mon, 01 Mar 2021 03:58:33 PST (-0800), Anup Patel wrote:
> > The SBI SRST extension provides a standard way to poweroff and
> > reboot the system irrespective to whether Linux RISC-V S-mode
> > is running nati
On Mon, Mar 8, 2021 at 1:19 PM Atish Patra wrote:
>
> On Sat, Mar 6, 2021 at 4:12 AM Anup Patel wrote:
> >
> > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt
> > wrote:
> > >
> > > The constants in enum sbi_ext_rfence_fid should match th
On Sat, Mar 6, 2021 at 4:52 AM Rob Herring wrote:
>
> On Sun, Feb 21, 2021 at 03:07:57PM +0530, Anup Patel wrote:
> > The RISC-V CPU idle states will be described in DT under the
> > /cpus/riscv-idle-states DT node. This patch adds the bindings
> > documentation for ri
C3 state. But many other architectures(powerpc, mips,
> arm, hexagon, openrisc, sh) have supported the infrastructure to
> deal with Power Management issues.
>
> Signed-off-by: Guo Ren
> Cc: Arnd Bergmann
> Cc: Thomas Gleixner
> Cc: Daniel Lezcano
> Cc: Anup Patel
> Cc: At
ese calls are only used by
KVM RISC-V which is not merged yet. Further for KVM RISC-V, the HFENCE
instruction is emulated as flush everything on FPGA, QEMU, and Spike so
we did not notice any issue with KVM RISC-V too.
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/ris
-sbi-doc.
This patch extends Linux RISC-V SBI implementation to detect
and use SBI SRST extension.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
Changes since v4:
- We should compare both major and minor number to ensure that
SBI spec version is 0.3 (or above) for detecting SRST
On Fri, Feb 26, 2021 at 6:46 PM Alex Ghiti wrote:
>
> Hi Anup,
>
> Le 2/21/21 à 4:37 AM, Anup Patel a écrit :
> > We force select CPU_PM and provide asm/cpuidle.h so that we can
> > use CPU IDLE drivers for Linux RISC-V kernel.
> >
> > Signed-off-by: Anup Pat
On Mon, Mar 1, 2021 at 5:29 PM Anup Patel wrote:
>
> The SBI SRST extension provides a standard way to poweroff and
> reboot the system irrespective to whether Linux RISC-V S-mode
> is running natively (HS-mode) or inside Guest/VM (VS-mode).
>
> The SBI SRST extension is avail
-sbi-doc.
This patch extends Linux RISC-V SBI implementation to detect
and use SBI SRST extension.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/sbi.h | 16 ++
arch/riscv/kernel/sbi.c | 41 +---
2 files changed, 54 insertions(+), 3 deletions
Hi Alex,
On Fri, Feb 26, 2021 at 6:46 PM Alex Ghiti wrote:
>
> Hi Anup,
>
> Le 2/21/21 à 4:37 AM, Anup Patel a écrit :
> > We force select CPU_PM and provide asm/cpuidle.h so that we can
> > use CPU IDLE drivers for Linux RISC-V kernel.
> >
> > Signed-off-by:
Hi Palmer,
On Fri, Feb 19, 2021 at 12:45 PM Palmer Dabbelt
wrote:
>
> On Mon, 08 Feb 2021 21:46:20 PST (-0800), Anup Patel wrote:
> > The CPU hotplug support has been tested on QEMU, Spike, and SiFive
> > Unleashed so let's enable it by default in RV32 and RV64 defconfigs.
We enable RISC-V SBI CPU Idle driver for QEMU virt machine to test
SBI HSM Supend on QEMU.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig.socs | 3 +++
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
3 files changed, 5 insertions(+)
diff --git
The generic power domain related code in PSCI domain driver is largely
independent of PSCI and can be shared with RISC-V SBI domain driver
hence we factor-out this code into dt_idle_genpd.c and dt_idle_genpd.h.
Signed-off-by: Anup Patel
---
drivers/cpuidle/Kconfig | 4
The RISC-V CPU idle states will be described in DT under the
/cpus/riscv-idle-states DT node. This patch adds the bindings
documentation for riscv-idle-states DT nodes and idle state DT
nodes under it.
Signed-off-by: Anup Patel
---
.../bindings/riscv/idle-states.yaml | 250
We add defines related to SBI HSM suspend call and also
update HSM states naming as-per latest SBI specification.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/sbi.h| 27 ++-
arch/riscv/kernel/cpu_ops_sbi.c | 2 +-
2 files changed, 23 insertions(+), 6
/exit.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/suspend.h | 35 +
arch/riscv/kernel/Makefile| 2 +
arch/riscv/kernel/asm-offsets.c | 3 +
arch/riscv/kernel/suspend.c | 86 ++
arch/riscv/kernel/suspend_entry.S | 116
-off-by: Anup Patel
---
MAINTAINERS | 8 +
drivers/cpuidle/Kconfig | 5 +
drivers/cpuidle/Kconfig.riscv | 15 +
drivers/cpuidle/Makefile | 4 +
drivers/cpuidle/cpuidle-sbi.c | 503 ++
5 files changed, 535 insertions(+)
create mode
-retentive suspend
so we make it global symbol.
Signed-off-by: Anup Patel
---
arch/riscv/kernel/head.S | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 16e9941900c4..a8aca43929d8 100644
--- a/arch/riscv/kernel/head.S
+++ b
We force select CPU_PM and provide asm/cpuidle.h so that we can
use CPU IDLE drivers for Linux RISC-V kernel.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig| 7 +++
arch/riscv/configs/defconfig | 7 +++
arch/riscv/configs/rv32_defconfig | 4 ++--
arch/riscv
Sandeep Tripathy for providing early feeback on SBI HSM
support in all above projects (RISC-V SBI specification, OpenSBI, and
Linux RISC-V).
Anup Patel (8):
RISC-V: Enable CPU_IDLE drivers
RISC-V: Rename relocate() and make it global
RISC-V: Add arch functions for non-retentive suspend entry/exit
The CPU hotplug support has been tested on QEMU, Spike, and SiFive
Unleashed so let's enable it by default in RV32 and RV64 defconfigs.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git
we don't see any change in performance. On real HW
having all ASID bits implemented, the performance gains will be much
more due improved sharing of TLB among different processes.
Signed-off-by: Anup Patel
Reviewed-by: Palmer Dabbelt
---
Changes since v4:
- Rebased on Linux-5.11-rc6
- Used
On Wed, Feb 3, 2021 at 7:58 AM Palmer Dabbelt wrote:
>
> On Thu, 21 Jan 2021 05:50:16 PST (-0800), Anup Patel wrote:
> > Currently, we do local TLB flush on every MM switch. This is very harsh on
> > performance because we are forcing page table walks after every MM switch.
we don't see any change in performance. On real
HW having all ASID bits implemented, the performance gains will be
much more due improved sharing of TLB among different processes.
Signed-off-by: Anup Patel
---
Changes since v3:
- Rebased on Linux-5.11-rc4. The previous v3 patch (almost 2 years back
t;
> @Palmer: ping :)
>
> > Signed-off-by: Vitaly Wool
>
> While at it, since this is just a respin/concatenation:
> @Damien: are you okay with re-adding 'Tested-By:' ?
> @Anup: are you okay with adding 'Reviewed-by:' since you have reviewed
> both v1 patches that were c
Hi,
On Tue, Jan 19, 2021 at 1:40 PM Geert Uytterhoeven wrote:
>
> Let the LiteX SoC Controller register a restart handler, which resets
> the LiteX SoC by writing 1 to CSR_CTRL_RESET_ADDR.
>
> Signed-off-by: Geert Uytterhoeven
We have SBI System Reset Extension (SRST) in upcoming
SBI v0.3
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