Re: [PATCH 2/4] iommu/mediatek: Add iotlb_sync_range() support

On Fri, 2020-10-23 at 13:57 +0800, chao hao wrote: > On Wed, 2020-10-21 at 17:55 +0100, Robin Murphy wrote: > > On 2020-10-19 12:30, Chao Hao wrote: > > > MTK_IOMMU driver writes one page entry and does tlb flush at a time > > > currently. More optimal would be to agg

Re: [PATCH 2/4] iommu/mediatek: Add iotlb_sync_range() support

On Wed, 2020-10-21 at 17:55 +0100, Robin Murphy wrote: > On 2020-10-19 12:30, Chao Hao wrote: > > MTK_IOMMU driver writes one page entry and does tlb flush at a time > > currently. More optimal would be to aggregate the writes and flush > > BUS buffer in the end. >

[PATCH 1/4] iommu: Introduce iotlb_sync_range callback

, iotlb_sync() and tlb_flush_walk/leaf() can be skipped. So iotlb_sync_range() will enhance performance by reducing the time of tlb sync. Signed-off-by: Chao Hao --- drivers/iommu/dma-iommu.c | 9 + drivers/iommu/iommu.c | 7 +++ include/linux/iommu.h | 2 ++ 3 files changed, 18

[PATCH 4/4] iommu/mediatek: Adjust iotlb_sync_range

As is title, the patch only adjusts the architecture of iotlb_sync_range(). No functional change. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c

[PATCH 2/4] iommu/mediatek: Add iotlb_sync_range() support

% performance or more(depending on size of every page size) in comparison to flushing after each page entry update. So we prefer to use iotlb_sync_range() to replace iotlb_sync(), tlb_add_range() and tlb_flush_walk/leaf() for MTK platforms. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c

[PATCH 3/4] iommu/mediatek: Remove unnecessary tlb sync

As is "[PATCH 2/4]" described, we will use iotlb_sync_range() to replace iotlb_sync(), tlb_add_range() and tlb_flush_walk/leaf() to enhance performance. So we will remove the implementation of iotlb_sync(), tlb_add_range() and tlb_flush_walk/leaf(). Signed-off-by: Chao Hao --- dri

[PATCH 0/4] MTK_IOMMU: Optimize mapping / unmapping performance

iotlb_sync(), tlb_add_range() and tlb_flush_walk/leaf(). So this patchset will replace iotlb_sync(), tlb_add_range() and tlb_flush_walk/leaf() with iotlb_sync_range() callback. Chao Hao (4): iommu: Introduce iotlb_sync_range callback iommu/mediatek: Add iotlb_sync_range() support iommu

Re: [PATCH 11/21] iommu/mediatek: Add power-domain operation

On Sat, 2020-07-11 at 14:48 +0800, Yong Wu wrote: > In the previous SoC, the M4U HW is in the EMI power domain which is > always on. the latest M4U is in the display power domain which may be > turned on/off, thus we have to add pm_runtime interface for it. > > we should enable its power before

Re: [PATCH v6 03/10] iommu/mediatek: Use a u32 flags to describe different HW features

Hi Matthias and Yingjoe, Thanks for your comments! On Mon, 2020-07-06 at 17:17 +0200, Matthias Brugger wrote: > > On 04/07/2020 03:16, Yingjoe Chen wrote: > > On Fri, 2020-07-03 at 12:41 +0800, Chao Hao wrote: > >> Given the fact that we are adding more and more

[PATCH v6 08/10] iommu/mediatek: Extend protect pa alignment value

Starting with mt6779, iommu needs to extend to 256 bytes from 128 bytes which can send the max number of data for memory protection pa alignment. So we can use a separate patch to modify it. Signed-off-by: Chao Hao Reviewed-by: Matthias Brugger --- drivers/iommu/mtk_iommu.c | 2 +- 1 file

[PATCH v6 04/10] iommu/mediatek: Setting MISC_CTRL register

. The feature is controlled by OUT_ORDER_WR_EN platform data flag. Cc: Matthias Brugger Suggested-by: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c

[PATCH v6 05/10] iommu/mediatek: Move inv_sel_reg into the plat_data

For mt6779, MMU_INV_SEL register's offset is changed from 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to use it. In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it before mt6779. Cc: Yong Wu Signed-off-by: Chao Hao Reviewed-by: Matthias Brugger --- drivers/iommu

[PATCH v6 06/10] iommu/mediatek: Add sub_comm id in translation fault

extend larb_remap[] to larb_remap[8][4] for this. larb_remap[x][y]: x means common-id above, y means subcommon_id above. We can also distinguish if the M4U HW has sub_common by HAS_SUB_COMM macro. Cc: Matthias Brugger Signed-off-by: Chao Hao Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.

[PATCH v6 10/10] iommu/mediatek: Add mt6779 basic support

1. Start from mt6779, INVLDT_SEL move to offset=0x2c, so we add REG_MMU_INV_SEL_GEN2 definition and mt6779 uses it. 2. Add mt6779_data to support mm_iommu HW init. Cc: Yong Wu Signed-off-by: Chao Hao Reviewed-by: Matthias Brugger --- drivers/iommu/mtk_iommu.c | 9 + drivers/iommu

[PATCH v6 00/10] MT6779 IOMMU SUPPORT

tek/2020-January/026131.html v1: http://lists.infradead.org/pipermail/linux-mediatek/2019-November/024567.html Chao Hao (10): dt-bindings: mediatek: Add bindings for MT6779 iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL iommu/mediatek: Use a u32 flags to describ

[PATCH v6 02/10] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL

the register name, no functional change. Signed-off-by: Chao Hao Reviewed-by: Yong Wu Reviewed-by: Matthias Brugger --- drivers/iommu/mtk_iommu.c | 14 +++--- drivers/iommu/mtk_iommu.h | 5 - 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c

[PATCH v6 03/10] iommu/mediatek: Use a u32 flags to describe different HW features

Given the fact that we are adding more and more plat_data bool values, it would make sense to use a u32 flags register and add the appropriate macro definitions to set and check for a flag present. No functional change. Cc: Yong Wu Suggested-by: Matthias Brugger Signed-off-by: Chao Hao

[PATCH v6 01/10] dt-bindings: mediatek: Add bindings for MT6779

) || ||| || -- || | | | Multimedia engine CCU VPU MDLA EMDA All the connections are hardware fixed, software can not adjust it. Signed-off-by: Chao Hao Reviewed-by: Rob

[PATCH v6 09/10] iommu/mediatek: Modify MMU_CTRL register setting

the bit will be cleared and IOMMU performance will drop. Cc: Matthias Brugger Cc: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index e71003037ffa

[PATCH v6 07/10] iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition

-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 11 +++ drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 0d96dcd8612b..5c8e141668fc 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu

Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register

On Wed, 2020-07-01 at 16:58 +0200, Matthias Brugger wrote: > > On 30/06/2020 12:53, chao hao wrote: > > On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: > >> > >> On 29/06/2020 09:13, Chao Hao wrote: > >>> Add F_MMU_IN_ORDER_WR_EN

Re: [PATCH v5 03/10] iommu/mediatek: Modify the usage of mtk_iommu_plat_data structure

On Tue, 2020-06-30 at 18:56 +0800, Yong Wu wrote: > Hi Chao, > > This is also ok for me. Only two format nitpick. > > On Mon, 2020-06-29 at 15:13 +0800, Chao Hao wrote: > > Given the fact that we are adding more and more plat_data bool values, > > it would make sense

Re: [PATCH v5 06/10] iommu/mediatek: Add sub_comm id in translation fault

On Tue, 2020-06-30 at 18:55 +0800, Yong Wu wrote: > On Mon, 2020-06-29 at 15:13 +0800, Chao Hao wrote: > > The max larb number that a iommu HW support is 8(larb0~larb7 in the below > > diagram). > > If the larb's number is over 8, we use a sub_common for merging > >

Re: [PATCH v5 09/10] iommu/mediatek: Modify MMU_CTRL register setting

On Mon, 2020-06-29 at 12:28 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > MT8173 is different from other SoCs for MMU_CTRL register. > > For mt8173, its bit9 is in_order_write_en and doesn't use its > > default 1'b1.> For other SoCs, bit[1

Re: [PATCH v5 07/10] iommu/mediatek: Add REG_MMU_WR_LEN register definition

On Mon, 2020-06-29 at 12:16 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > Some platforms(ex: mt6779) need to improve performance by setting > > REG_MMU_WR_LEN register. And we can use WR_THROT_EN macro to control > > whether we

Re: [PATCH v5 04/10] iommu/mediatek: Setting MISC_CTRL register

On Mon, 2020-06-29 at 11:28 +0200, Matthias Brugger wrote: > > On 29/06/2020 09:13, Chao Hao wrote: > > Add F_MMU_IN_ORDER_WR_EN and F_MMU_STANDARD_AXI_MODE_BIT definition > > in MISC_CTRL register. > > F_MMU_STANDARD_AXI_MODE_BIT: > > If we set F_MMU_STANDA

Re: [PATCH v4 3/7] iommu/mediatek: Set MISC_CTRL register

On Sat, 2020-06-20 at 10:03 +0800, Yong Wu wrote: > Hi Chao, > > On Thu, 2020-06-18 at 19:49 +0800, chao hao wrote: > > On Wed, 2020-06-17 at 11:34 +0200, Matthias Brugger wrote: > > [snip] > > > > > > > > > #define REG_MMU_MISC_

Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779

On Sun, 2020-06-21 at 13:01 +0200, Matthias Brugger wrote: > > On 19/06/2020 12:56, chao hao wrote: > > On Wed, 2020-06-17 at 11:22 +0200, Matthias Brugger wrote: > >> > >> On 17/06/2020 05:00, Chao Hao wrote: > >>> Some platforms(ex: mt6779) ha

Re: [PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779

On Wed, 2020-06-17 at 11:22 +0200, Matthias Brugger wrote: > > On 17/06/2020 05:00, Chao Hao wrote: > > Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN > > to improve performance. > > This patch add this register definition. > > Please be mo

Re: [PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support

On Thu, 2020-06-18 at 18:00 +0200, Matthias Brugger wrote: > > On 18/06/2020 13:54, chao hao wrote: > > On Wed, 2020-06-17 at 11:33 +0200, Matthias Brugger wrote: > >> > >> On 17/06/2020 05:00, Chao Hao wrote: > >>> 1. Start from mt6779,

Re: [PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support

On Wed, 2020-06-17 at 11:33 +0200, Matthias Brugger wrote: > > On 17/06/2020 05:00, Chao Hao wrote: > > 1. Start from mt6779, INVLDT_SEL move to offset=0x2c, so we add > >REG_MMU_INV_SEL_GEN2 definition and mt6779 uses it. > > 2. Change PROTECT_PA_ALIGN from 128

Re: [PATCH v4 3/7] iommu/mediatek: Set MISC_CTRL register

On Wed, 2020-06-17 at 11:34 +0200, Matthias Brugger wrote: > > On 17/06/2020 05:00, Chao Hao wrote: > > Add F_MMU_IN_ORDER_WR_EN definition in MISC_CTRL. > > In order to improve performance, we always disable STANDARD_AXI_MODE > > and IN_ORDER_WR_EN in MISC_CTRL.

Re: [PATCH v4 5/7] iommu/mediatek: Add sub_comm id in translation fault

On Wed, 2020-06-17 at 19:11 +0800, Yong Wu wrote: > Hi Matthias, > > Thanks very much for your review. > > On Wed, 2020-06-17 at 11:17 +0200, Matthias Brugger wrote: > > > > On 17/06/2020 05:00, Chao Hao wrote: > > > The max larb number that a iommu HW s

[PATCH v4 3/7] iommu/mediatek: Set MISC_CTRL register

We need to disable in_order_write to improve performance Cc: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 11 +++ drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index

[PATCH v4 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data

For mt6779, MMU_INV_SEL register's offset is changed from 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to use it. In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it before mt6779. Change since v3: 1. Fix coding style Cc: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu

[PATCH v4 00/07] MT6779 IOMMU SUPPORT

8 register. 5. Split "iommu/mediatek: Add mt6779 IOMMU basic support(patch v1)" to several patches(patch v2). http://lists.infradead.org/pipermail/linux-mediatek/2020-January/026131.html v1: http://lists.infradead.org/pipermail/linux-mediatek/2019-November/024567.html Chao Ha

[PATCH v4 5/7] iommu/mediatek: Add sub_comm id in translation fault

extern larb_remap[] to larb_remap[8][4] for this. larb_remap[x][y]: x mean common-id above, y means subcommon_id above. We can also distinguish if the M4U HW has sub_common by has_sub_comm property. Signed-off-by: Chao Hao Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 20 +--- d

[PATCH v4 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779

Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN to improve performance. This patch add this register definition. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 10 ++ drivers/iommu/mtk_iommu.h | 2 ++ 2 files changed, 12 insertions(+) diff --git

[PATCH v4 7/7] iommu/mediatek: Add mt6779 basic support

. 4. Add mt6779_data to support mm_iommu HW init. Change since v3: 1. When setting MMU_CTRL_REG, we don't need to include mt8173. Cc: Yong Wu Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 20 ++-- drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 19 insertions(+), 2

[PATCH v4 2/7] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL

the register name, no functional change. Signed-off-by: Chao Hao Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 14 +++--- drivers/iommu/mtk_iommu.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index

[PATCH v4 1/7] dt-bindings: mediatek: Add bindings for MT6779

, ex: M4U_LARB12_ID, M4U_LARB13_ID, CCU, VPU, MDLA, EDMA Change since v1: 1. Delete M4U_PORT_UNKNOWN define because of not use it. 2. Correct coding format: ex: /*larb3-VENC*/ --> /* larb3-VENC */ Signed-off-by: Chao Hao Reviewed-by: Rob Herring --- .../bindings/iommu/mediatek,iommu.

Re: [PATCH v3 3/7] iommu/mediatek: Disable STANDARD_AXI_MODE in MISC_CTRL

On Mon, 2020-05-25 at 14:14 +0800, Yong Wu wrote: > On Sat, 2020-05-09 at 16:36 +0800, Chao Hao wrote: > > In order to improve performance, we always disable STANDARD_AXI_MODE in > > MISC_CTRL. > > > > Signed-off-by: Chao Hao > > --- > > drivers/iommu/mtk_

[PATCH v3 3/7] iommu/mediatek: Disable STANDARD_AXI_MODE in MISC_CTRL

In order to improve performance, we always disable STANDARD_AXI_MODE in MISC_CTRL. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 8 +++- drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu

[PATCH v3 00/07] MT6779 IOMMU SUPPORT

.org/pipermail/linux-mediatek/2020-January/026131.html v1: http://lists.infradead.org/pipermail/linux-mediatek/2019-November/024567.html Chao Hao (7): dt-bindings: mediatek: Add bindings for MT6779 iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL iom

[PATCH v3 7/7] iommu/mediatek: Add mt6779 basic support

. 4. Add mt6779_data to support mm_iommu HW init. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 18 +++--- drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index dc9ae944e712

[PATCH v3 6/7] iommu/mediatek: Add REG_MMU_WR_LEN definition preparing for mt6779

Some platforms(ex: mt6779) have a new register called by REG_MMU_WR_LEN to improve performance. This patch add this register definition. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 10 ++ drivers/iommu/mtk_iommu.h | 2 ++ 2 files changed, 12 insertions(+) diff --git

[PATCH v3 4/7] iommu/mediatek: Move inv_sel_reg into the plat_data

For mt6779, MMU_INVLDT_SEL register's offset is changed from 0x38 to 0x2c, so we can put inv_sel_reg in the plat_data to use it. In addition, we renamed it to REG_MMU_INV_SEL_GEN1 and use it before mt6779. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 9 ++--- drivers/iommu

[PATCH v3 5/7] iommu/mediatek: Add sub_comm id in translation fault

extern larb_remap[] to larb_remap[8][4] for this. larb_remap[x][y]: x mean common-id above, y means subcommon_id above. We can also distinguish if the M4U HW has sub_common by has_sub_comm property. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 20 +--- drivers/iommu/mtk_iommu.

[PATCH v3 2/7] iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL

the register name, no functional change. Signed-off-by: Chao Hao --- drivers/iommu/mtk_iommu.c | 14 +++--- drivers/iommu/mtk_iommu.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 5f4d6df59cf6

[PATCH v3 1/7] dt-bindings: mediatek: Add bindings for MT6779

, ex: M4U_LARB12_ID, M4U_LARB13_ID, CCU, VPU, MDLA, EDMA Change since v1: 1. Delete M4U_PORT_UNKNOWN define because of not use it. 2. Correct coding format: ex: /*larb3-VENC*/ --> /* larb3-VENC */ Signed-off-by: Chao Hao Reviewed-by: Rob Herring --- .../bindings/iommu/mediatek,iommu.