L-2.0-only
> /*
> - * Hisilicon SoC reset code
> + * HiSilicon SoC reset code
>*
> - * Copyright (c) 2014 Hisilicon Ltd.
> + * Copyright (c) 2014 HiSilicon Ltd.
>* Copyright (c) 2014 Linaro Ltd.
>*
>* Author: Haojian Zhuang
>
Acked-by: Haojian Zhuang
2012-2013 Hisilicon Ltd.
> + * Copyright (c) 2012-2013 HiSilicon Ltd.
> * Copyright (c) 2012-2013 Linaro Ltd.
>*
>* Author: Haojian Zhuang
> diff --git a/arch/arm/mach-hisi/hotplug.c b/arch/arm/mach-hisi/hotplug.c
> index 5c5f255..c517941 100644
> --- a/arch/
/am33xx-l4.dtsi | 2 +-
> drivers/pinctrl/pinctrl-single.c | 11 +--
> include/dt-bindings/pinctrl/omap.h | 2 +-
> 3 files changed, 11 insertions(+), 4 deletions(-)
>
> --
> 2.25.1
>
Acked-by: Haojian Zhuang
nconfs, sizeof(struct pcs_conf_vals),
> @@ -1056,9 +1056,12 @@ static int pcs_parse_one_pinctrl_entry(struct
> pcs_device *pcs,
>
> if (PCS_HAS_PINCONF && function) {
> res = pcs_parse_pinconf(pcs, np, function, map);
> - if (res)
> + if (res == 0)
> + *num_maps = 2;
> + else if (res == -ENOTSUPP)
> + *num_maps = 1;
> + else
> goto free_pingroups;
> - *num_maps = 2;
> } else {
> *num_maps = 1;
> }
> --
> 2.25.1
Tested-by: Haojian Zhuang
On Tue, 2015-08-25 at 16:37 +0100, Leif Lindholm wrote:
> On Tue, Aug 25, 2015 at 04:51:22PM +0200, Ard Biesheuvel wrote:
> > >>Arm kernel should either fetch memory information from
> > >>efi or DT.
> > >
> > > Absolutely.
> > >
> > >>Currently arm kernel fetch both efi memory
On Wed, 2015-08-26 at 00:00 +0800, Leo Yan wrote:
> On Tue, Aug 25, 2015 at 09:43:14PM +0800, Haojian Zhuang wrote:
> > On Tue, 2015-08-25 at 11:42 +0100, Mark Rutland wrote:
> > > > > Are you then going to hack GRUB, release a special HiKey version of
> > >
On Tue, 2015-08-25 at 11:42 +0100, Mark Rutland wrote:
> > > Are you then going to hack GRUB, release a special HiKey version of
> > > GRUB, not support any other versions, and still can your firmware
> > > UEFI?
> >
> > I don't need to hack GRUB at all.
>
> Then it is working for you by pure
On Tue, 2015-08-25 at 10:46 +0100, Leif Lindholm wrote:
> On Tue, Aug 25, 2015 at 04:13:47PM +0800, Haojian Zhuang wrote:
> > On Mon, 2015-08-24 at 12:49 +0100, Leif Lindholm wrote:
> > > On Mon, Aug 24, 2015 at 06:19:56PM +0800, Haojian Zhuang wrote:
> > > > >
On Mon, 2015-08-24 at 12:49 +0100, Leif Lindholm wrote:
> On Mon, Aug 24, 2015 at 06:19:56PM +0800, Haojian Zhuang wrote:
> > > If your EFI memory map describes the memory as mappable, it is wrong.
> >
> > When kernel is working, kernel will create its own page table base
On Mon, 2015-08-24 at 13:48 +0100, Mark Rutland wrote:
> > > > > I don't see why you need reserved-memory here, given you're not
> > > > > referring to
> > > > > these regions by phandle anyway.
> > > >
> > > > - Now we have enabled EFI_STUB, so the memory node will be removed in
> > > >
On Tue, 2015-08-25 at 16:37 +0100, Leif Lindholm wrote:
On Tue, Aug 25, 2015 at 04:51:22PM +0200, Ard Biesheuvel wrote:
Arm kernel should either fetch memory information from
efi or DT.
Absolutely.
Currently arm kernel fetch both efi memory information and
On Mon, 2015-08-24 at 12:49 +0100, Leif Lindholm wrote:
On Mon, Aug 24, 2015 at 06:19:56PM +0800, Haojian Zhuang wrote:
If your EFI memory map describes the memory as mappable, it is wrong.
When kernel is working, kernel will create its own page table based on
UEFI memory map. Since
On Mon, 2015-08-24 at 13:48 +0100, Mark Rutland wrote:
I don't see why you need reserved-memory here, given you're not
referring to
these regions by phandle anyway.
- Now we have enabled EFI_STUB, so the memory node will be removed in
kernel:
efi_entry()
On Tue, 2015-08-25 at 10:46 +0100, Leif Lindholm wrote:
On Tue, Aug 25, 2015 at 04:13:47PM +0800, Haojian Zhuang wrote:
On Mon, 2015-08-24 at 12:49 +0100, Leif Lindholm wrote:
On Mon, Aug 24, 2015 at 06:19:56PM +0800, Haojian Zhuang wrote:
If your EFI memory map describes the memory
On Tue, 2015-08-25 at 11:42 +0100, Mark Rutland wrote:
Are you then going to hack GRUB, release a special HiKey version of
GRUB, not support any other versions, and still can your firmware
UEFI?
I don't need to hack GRUB at all.
Then it is working for you by pure chance alone.
On Wed, 2015-08-26 at 00:00 +0800, Leo Yan wrote:
On Tue, Aug 25, 2015 at 09:43:14PM +0800, Haojian Zhuang wrote:
On Tue, 2015-08-25 at 11:42 +0100, Mark Rutland wrote:
Are you then going to hack GRUB, release a special HiKey version of
GRUB, not support any other versions, and still
On Mon, 2015-08-24 at 10:51 +0100, Mark Rutland wrote:
> On Mon, Aug 24, 2015 at 10:18:45AM +0100, Leo Yan wrote:
> > Hi Mark,
> >
> > On Fri, Aug 21, 2015 at 07:40:59PM +0100, Mark Rutland wrote:
> > > On Wed, Aug 19, 2015 at 10:37:35AM +0100, Leo Yan wrote:
> > > > On Hi6220, below memory
On Mon, 2015-08-24 at 10:51 +0100, Mark Rutland wrote:
On Mon, Aug 24, 2015 at 10:18:45AM +0100, Leo Yan wrote:
Hi Mark,
On Fri, Aug 21, 2015 at 07:40:59PM +0100, Mark Rutland wrote:
On Wed, Aug 19, 2015 at 10:37:35AM +0100, Leo Yan wrote:
On Hi6220, below memory regions in DDR have
atch set:
> https://github.com/96boards/documentation/wiki/UEFI
>
> Changes v4:
> * Rebase to kernel 4.1-rc1
> * Delete "arm,cortex-a15-gic" from the gic node in dts
>
Acked-by: Haojian Zhuang
--
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onfig and defconfig
> arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
> clk: hi6220: Document devicetree bindings for hi6220 clock
> clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
> arm64: dts: Add dts files for Hisilicon Hi6220 SoC
>
://github.com/96boards/documentation/wiki/UEFI
Changes v4:
* Rebase to kernel 4.1-rc1
* Delete arm,cortex-a15-gic from the gic node in dts
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
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: Document devicetree bindings for hi6220 clock
clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
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On Tue, Feb 3, 2015 at 9:21 PM, Linus Walleij wrote:
> On Wed, Jan 28, 2015 at 3:30 AM, Chao Xie wrote:
>
>> From: Chao Xie
>>
>> For some old PXA series, they used PXA GPIO driver.
>> The IP of GPIO changes since PXA988 which is Marvell MMP
>> series.
>> It will use new way to control the GPIO
On Tue, Feb 3, 2015 at 9:21 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, Jan 28, 2015 at 3:30 AM, Chao Xie chao@marvell.com wrote:
From: Chao Xie chao@marvell.com
For some old PXA series, they used PXA GPIO driver.
The IP of GPIO changes since PXA988 which is Marvell MMP
It will be refined as each CPU probes its ID.
> */
> for (i = 0; i < NR_HIP04_CPU_IF; i++)
> - hip04_cpu_map[i] = 0xff;
> + hip04_cpu_map[i] = 0x;
>
> /*
> * Find out how many interrupts are support
)
* It will be refined as each CPU probes its ID.
*/
for (i = 0; i NR_HIP04_CPU_IF; i++)
- hip04_cpu_map[i] = 0xff;
+ hip04_cpu_map[i] = 0x;
/*
* Find out how many interrupts are supported.
--
1.8.3.4
Acked-by: Haojian Zhuang haojian.zhu
On Fri, Nov 28, 2014 at 9:30 PM, Robert Jarzmik wrote:
> Thomas Gleixner writes:
>
>> So what is the relationship between installing that chained handler
>> and that gpio-pxa probe stuff?
> The relation is in gpio-pxa probe, look at the extract of pxa_gpio_probe() :
> pxa_gpio_probe()
>
On Fri, Nov 28, 2014 at 9:30 PM, Robert Jarzmik robert.jarz...@free.fr wrote:
Thomas Gleixner t...@linutronix.de writes:
So what is the relationship between installing that chained handler
and that gpio-pxa probe stuff?
The relation is in gpio-pxa probe, look at the extract of
On Tue, Nov 4, 2014 at 8:46 PM, Zhou Wang wrote:
> This patchset adds the support for NAND controller of hisilicon hip04 Soc.
> The NAND controller IP was developed by hisilicon and needs a new driver to
> support it. This patchset is based on v3.18-rc1. I have tested that NAND flash
> controller
On Tue, Nov 4, 2014 at 8:46 PM, Zhou Wang wangzhou@gmail.com wrote:
This patchset adds the support for NAND controller of hisilicon hip04 Soc.
The NAND controller IP was developed by hisilicon and needs a new driver to
support it. This patchset is based on v3.18-rc1. I have tested that NAND
On 13 November 2014 08:35, Mike Turquette wrote:
> Quoting Haojian Zhuang (2014-11-04 00:15:55)
>> On Fri, Oct 31, 2014 at 10:13 AM, Chao Xie wrote:
>> > From: Chao Xie
>> >
>> > The patch set focuses at support device tree for clock.
>> >
>> &
On 13 November 2014 08:35, Mike Turquette mturque...@linaro.org wrote:
Quoting Haojian Zhuang (2014-11-04 00:15:55)
On Fri, Oct 31, 2014 at 10:13 AM, Chao Xie chao@marvell.com wrote:
From: Chao Xie chao@marvell.com
The patch set focuses at support device tree for clock
quot;
>
> /* clock parent list */
> -static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
Acked-by: Haojian Zhuang
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*/
-static const char *timer0_mux_p[] __initdata = { osc32k, timerclk01, };
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
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|1 +
> drivers/mtd/nand/hisi504_nand.c| 846
>
> 4 files changed, 892 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt
> create mode 100644 drivers/mtd/nand/hisi504_nand
insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt
create mode 100644 drivers/mtd/nand/hisi504_nand.c
--
1.7.9.5
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
--
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create mode 100644 drivers/clk/mmp/clk-of-mmp2.c
> create mode 100644 drivers/clk/mmp/clk-of-pxa168.c
> create mode 100644 drivers/clk/mmp/clk-of-pxa910.c
> create mode 100644 drivers/clk/mmp/clk.c
> create mode 100644 drivers/clk/mmp/reset.c
> create mode 100644 drivers/clk/mm
mode 100644 include/dt-bindings/clock/marvell,mmp2.h
create mode 100644 include/dt-bindings/clock/marvell,pxa168.h
create mode 100644 include/dt-bindings/clock/marvell,pxa910.h
--
1.8.3.2
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
Mike,
Please merge all mach-mmp patches with clock
> 2 files changed, 76 insertions(+)
>
Acked-by: Haojian Zhuang
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insertions(+)
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
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Please read the FAQ at http://www.tux.org
On Thu, Oct 23, 2014 at 10:04 PM, Zhou Wang wrote:
> Signed-off-by: Zhou Wang
> ---
> drivers/mtd/nand/Kconfig|5 +
> drivers/mtd/nand/Makefile |1 +
> drivers/mtd/nand/hisi504_nand.c | 836
> +++
> 3 files changed, 842 insertions(+)
>
On Thu, Oct 23, 2014 at 10:04 PM, Zhou Wang wangzhou@gmail.com wrote:
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig|5 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/hisi504_nand.c | 836
+++
On 5 September 2014 07:07, Paul Bolle wrote:
> On Thu, 2014-06-19 at 17:00 +0800, Haojian Zhuang wrote:
>> On 19 June 2014 16:50, Paul Bolle wrote:
>> > 0) Commit d3e6573c48f4 ("clk: hip04: add clock driver") was included in
>> > v3.15. That clock driver is b
On 5 September 2014 07:07, Paul Bolle pebo...@tiscali.nl wrote:
On Thu, 2014-06-19 at 17:00 +0800, Haojian Zhuang wrote:
On 19 June 2014 16:50, Paul Bolle pebo...@tiscali.nl wrote:
0) Commit d3e6573c48f4 (clk: hip04: add clock driver) was included in
v3.15. That clock driver is built only
On 26 August 2014 12:38, Chao Xie wrote:
> From: Chao Xie
>
> The patch set focuses at support device tree for clock.
>
> The first part of the patches
> clk: mmp: add prefix "mmp" for structures defined for clk-frac
> clk: mmp: add spin lock for clk-frac
> clk: mmp: add init callback for
On 26 August 2014 12:38, Chao Xie chao@marvell.com wrote:
From: Chao Xie chao@marvell.com
The patch set focuses at support device tree for clock.
The first part of the patches
clk: mmp: add prefix mmp for structures defined for clk-frac
clk: mmp: add spin lock for clk-frac
as extension. If it needs to extend
a bitmap, it still check whether the allocation exceeding the total
size, not current bitmap size. So change the condition from
mapping->bits to PAGE_SIZE.
Signed-off-by: Haojian Zhuang
---
arch/arm/mm/dma-mapping.c | 8
1 file changed, 4 insertions(+)
bitmaps were introduced as extension. If it needs to extend
a bitmap, it still check whether the allocation exceeding the total
size, not current bitmap size. So change the condition from
mapping-bits to PAGE_SIZE.
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
arch/arm/mm/dma
d(CONFIG_SPI_PXA2XX_MASTER)
> +#if IS_ENABLED(CONFIG_SPI_PXA2XX)
> static struct pxa2xx_spi_master corgi_spi_info = {
> .num_chipselect = 3,
> };
> --
> 1.9.0
>
Acked-by: Haojian Zhuang
--
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6 @@ static struct map_desc common_io_desc[] __initdata = {
>
> void __init pxa_map_io(void)
> {
> + debug_ll_io_init();
> iotable_init(ARRAY_AND_SIZE(common_io_desc));
> }
> --
> 1.9.0.rc3.12.gbc97e2d
>
Acked-by: Haojian Zhuang
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@ (see Errata 38 ...hangs when entering self-refresh mode)
>
> @ force address lines low by reading at physical address 0
> ldr r3, [r2]
> --
> 1.9.0.rc3.12.gbc97e2d
>
Acked-by: Haojian Zhuang
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Wei Xu
> +L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
> +W: www.hisilicon.com
> +S: Supported
> +T: git git://github.com/hisilicon/linux-hisi.git
> +F: arch/arm/mach-hisi/
> +
> ARM/HP JORNADA 7XX MACHINE SUPPORT
> M: K
W: www.jlime.com
--
1.8.1.2
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Best Regards
Haojian
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entering self-refresh mode)
@ force address lines low by reading at physical address 0
ldr r3, [r2]
--
1.9.0.rc3.12.gbc97e2d
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
--
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@@ static struct map_desc common_io_desc[] __initdata = {
void __init pxa_map_io(void)
{
+ debug_ll_io_init();
iotable_init(ARRAY_AND_SIZE(common_io_desc));
}
--
1.9.0.rc3.12.gbc97e2d
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
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(CONFIG_SPI_PXA2XX)
static struct pxa2xx_spi_master corgi_spi_info = {
.num_chipselect = 3,
};
--
1.9.0
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
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More
iff --git a/arch/arm/mach-pxa/time.c b/drivers/clocksource/pxa_timer.c
> similarity index 100%
> rename from arch/arm/mach-pxa/time.c
> rename to drivers/clocksource/pxa_timer.c
> --
> 2.0.0.rc2
>
Acked-by: Haojian Zhuang
Acked for all these three patches.
Regards
Haojian
--
To un
/mach-pxa/time.c
rename to drivers/clocksource/pxa_timer.c
--
2.0.0.rc2
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
Acked for all these three patches.
Regards
Haojian
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On 19 June 2014 16:50, Paul Bolle wrote:
> 0) Commit d3e6573c48f4 ("clk: hip04: add clock driver") was included in
> v3.15. That clock driver is built only if CONFIG_ARCH_HIP04 is set.
>
> And commit 5efaf09021a5 ("clk: hisi: add clk-hix5hd2.c") was included in
> v3.16-rc1. And that driver is
On 19 June 2014 16:50, Paul Bolle pebo...@tiscali.nl wrote:
0) Commit d3e6573c48f4 (clk: hip04: add clock driver) was included in
v3.15. That clock driver is built only if CONFIG_ARCH_HIP04 is set.
And commit 5efaf09021a5 (clk: hisi: add clk-hix5hd2.c) was included in
v3.16-rc1. And that
y: Jean Delvare
> Cc: Chris Ball
> Cc: Ulf Hansson
> Cc: Eric Miao
> Cc: Haojian Zhuang
> ---
> Changes since v1:
> * Rebased on kernel 3.16-rc1
>
> drivers/mmc/host/Kconfig |2 ++
> 1 file changed, 2 insertions(+)
>
> --- linux-3.16-rc1.orig/
gpiolib irqchip helpers
> and rid some code. Just saying.
>
> Yours,
> Linus Walleij
Acked-by: Haojian Zhuang
Yes, it's worth to rid some irqchip code.
Regards
Haojian
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to the gpiolib irqchip helpers
and rid some code. Just saying.
Yours,
Linus Walleij
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
Yes, it's worth to rid some irqchip code.
Regards
Haojian
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-by: Jean Delvare jdelv...@suse.de
Cc: Chris Ball ch...@printf.net
Cc: Ulf Hansson ulf.hans...@linaro.org
Cc: Eric Miao eric.y.m...@gmail.com
Cc: Haojian Zhuang haojian.zhu...@gmail.com
---
Changes since v1:
* Rebased on kernel 3.16-rc1
drivers/mmc/host/Kconfig |2 ++
1 file changed, 2
gt; #ifdef CONFIG_OF
> -static struct of_device_id sa1100_rtc_dt_ids[] = {
> +static const struct of_device_id sa1100_rtc_dt_ids[] = {
> { .compatible = "mrvl,sa1100-rtc", },
> { .compatible = "mrvl,mmp-rtc", },
> {}
> --
> 1.7
struct of_device_id sa1100_rtc_dt_ids[] = {
+static const struct of_device_id sa1100_rtc_dt_ids[] = {
{ .compatible = mrvl,sa1100-rtc, },
{ .compatible = mrvl,mmp-rtc, },
{}
--
1.7.10.4
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Regards
Haojian
On 24 April 2014 02:52, Rob Herring wrote:
> On Mon, Apr 21, 2014 at 8:35 PM, Haojian Zhuang
> wrote:
>> If gpio base number isn't specified, the gpio base will be find from
>> the end of gpio number. In order to keep with schematics, use alias
>> to get the
On 23 April 2014 21:21, Linus Walleij wrote:
> On Tue, Apr 22, 2014 at 3:35 AM, Haojian Zhuang
> wrote:
>
>> If gpio base number isn't specified, the gpio base will be find from
>> the end of gpio number. In order to keep with schematics, use alias
>> to get the ID of
On 23 April 2014 21:21, Linus Walleij linus.wall...@linaro.org wrote:
On Tue, Apr 22, 2014 at 3:35 AM, Haojian Zhuang
haojian.zhu...@linaro.org wrote:
If gpio base number isn't specified, the gpio base will be find from
the end of gpio number. In order to keep with schematics, use alias
On 24 April 2014 02:52, Rob Herring robherri...@gmail.com wrote:
On Mon, Apr 21, 2014 at 8:35 PM, Haojian Zhuang
haojian.zhu...@linaro.org wrote:
If gpio base number isn't specified, the gpio base will be find from
the end of gpio number. In order to keep with schematics, use alias
to get
Use gpio alias to identify the index of gpio chip. Then we can keep the
same gpio number as schematics. Otherwise, gpio number is countered from
bottom to top.
Signed-off-by: Haojian Zhuang
---
arch/arm/boot/dts/hi3620.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff
If gpio base number isn't specified, the gpio base will be find from
the end of gpio number. In order to keep with schematics, use alias
to get the ID of gpio chip.
Signed-off-by: Haojian Zhuang
---
.../devicetree/bindings/gpio/gpio-pl061.txt| 31 ++
drivers/gpio
Use gpio alias to identify the index of gpio chip. Then we can keep the
same gpio number as schematics. Otherwise, gpio number is countered from
bottom to top.
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
arch/arm/boot/dts/hi3620.dtsi | 22 ++
1 file changed
If gpio base number isn't specified, the gpio base will be find from
the end of gpio number. In order to keep with schematics, use alias
to get the ID of gpio chip.
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
.../devicetree/bindings/gpio/gpio-pl061.txt| 31
On 6 April 2014 18:28, Paul Bolle wrote:
> On Fri, 2014-04-04 at 10:47 -0700, Mike Turquette wrote:
>> Haojian Zhuang (3):
>> [...]
>> clk: hip04: add clock driver
>
> This clock driver is only built if CONFIG_ARCH_HIP04 is set. But I
> couldn't find a
On 6 April 2014 18:28, Paul Bolle pebo...@tiscali.nl wrote:
On Fri, 2014-04-04 at 10:47 -0700, Mike Turquette wrote:
Haojian Zhuang (3):
[...]
clk: hip04: add clock driver
This clock driver is only built if CONFIG_ARCH_HIP04 is set. But I
couldn't find a Kconfig symbol
platform_device_register(_device_u2o);
> #endif
>
> -#ifdef CONFIG_USB_EHCI_MV_U2O
> +#if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
> pxa168_device_u2oehci.dev.platform_data = _usb_pdata;
> platform_device_register(_device_u2oehci);
> #endif
>
> -#ifdef CONFIG_
();
#endif
}
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
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On Thu, Feb 27, 2014 at 9:37 AM, Chao Xie wrote:
> On Mon, Feb 24, 2014 at 7:31 PM, Thomas Gleixner wrote:
>> On Mon, 24 Feb 2014, Haojian Zhuang wrote:
>>
>>> On Mon, Feb 24, 2014 at 2:07 PM, Chao Xie wrote:
>>> > On Mon, Feb 24, 2014 at 7:17 AM, Uwe Kleine-
On Thu, Feb 27, 2014 at 9:37 AM, Chao Xie xiechao.m...@gmail.com wrote:
On Mon, Feb 24, 2014 at 7:31 PM, Thomas Gleixner t...@linutronix.de wrote:
On Mon, 24 Feb 2014, Haojian Zhuang wrote:
On Mon, Feb 24, 2014 at 2:07 PM, Chao Xie xiechao.m...@gmail.com wrote:
On Mon, Feb 24, 2014 at 7:17
pm8607.c
> +++ b/drivers/regulator/88pm8607.c
> @@ -2,7 +2,7 @@
> * Regulators driver for Marvell 88PM8607
> *
> * Copyright (C) 2009 Marvell International Ltd.
> - * Haojian Zhuang
> + * Haojian Zhuang
> *
> * This program is free software; you can r
/regulator/88pm8607.c
@@ -2,7 +2,7 @@
* Regulators driver for Marvell 88PM8607
*
* Copyright (C) 2009 Marvell International Ltd.
- * Haojian Zhuang haojian.zhu...@marvell.com
+ * Haojian Zhuang haojian.zhu...@marvell.com
*
* This program is free software; you can redistribute
On Mon, Feb 24, 2014 at 2:07 PM, Chao Xie wrote:
> On Mon, Feb 24, 2014 at 7:17 AM, Uwe Kleine-König
> wrote:
>> Hi Thomas,
>>
>> On Sun, Feb 23, 2014 at 09:40:13PM -, Thomas Gleixner wrote:
>>> The pm-mmp2 and pm-pxa910 power management related irq_set_wake
>>> callbacks fiddle pointlessly
On Mon, Feb 24, 2014 at 2:07 PM, Chao Xie xiechao.m...@gmail.com wrote:
On Mon, Feb 24, 2014 at 7:17 AM, Uwe Kleine-König
u.kleine-koe...@pengutronix.de wrote:
Hi Thomas,
On Sun, Feb 23, 2014 at 09:40:13PM -, Thomas Gleixner wrote:
The pm-mmp2 and pm-pxa910 power management related
On Fri, Dec 6, 2013 at 6:46 PM, Neil Zhang wrote:
> For example, arm64 doesn't have mach/irq.h.
>
> Signed-off-by: Neil Zhang
> Acked-by: Haojian Zhuang
> ---
> drivers/irqchip/irq-mmp.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/
On Fri, Dec 6, 2013 at 6:46 PM, Neil Zhang zhan...@marvell.com wrote:
For example, arm64 doesn't have mach/irq.h.
Signed-off-by: Neil Zhang zhan...@marvell.com
Acked-by: Haojian Zhuang haojian.zhu...@gmail.com
---
drivers/irqchip/irq-mmp.c |2 +-
1 file changed, 1 insertion(+), 1
On 12/10/2013 01:43 AM, Eric Miao wrote:
Haojian, could you help take this via your tree to arm-soc?
Applied.
Thanks
Haojian
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On 12/11/2013 02:31 AM, Marek Vasut wrote:
On Tuesday, December 10, 2013 at 11:48:59 AM, Daniel Mack wrote:
On 12/10/2013 09:43 AM, Haojian Zhuang wrote:
On 12/10/2013 12:39 PM, Sergei Ianovich wrote:
Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains
On 12/10/2013 12:39 PM, Sergei Ianovich wrote:
Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains that watchdog reset time is just
8us insead of 10ms in EMTS.
If SDRAM is not reset, it causes memory bus congestion and
the device hangs. We put SDRAM in selfresh
On 12/11/2013 02:31 AM, Marek Vasut wrote:
On Tuesday, December 10, 2013 at 11:48:59 AM, Daniel Mack wrote:
On 12/10/2013 09:43 AM, Haojian Zhuang wrote:
On 12/10/2013 12:39 PM, Sergei Ianovich wrote:
Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains
On 12/10/2013 01:43 AM, Eric Miao wrote:
Haojian, could you help take this via your tree to arm-soc?
Applied.
Thanks
Haojian
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On 12/10/2013 12:39 PM, Sergei Ianovich wrote:
Erratum 71 of PXA270M Processor Family Specification Update
(April 19, 2010) explains that watchdog reset time is just
8us insead of 10ms in EMTS.
If SDRAM is not reset, it causes memory bus congestion and
the device hangs. We put SDRAM in selfresh
On Thu, Dec 5, 2013 at 10:00 AM, Dan Williams wrote:
> On Wed, Dec 4, 2013 at 5:36 PM, Qiao Zhou wrote:
>> sram driver can be used by many chips besides CPU_MMP2, and so build
>> it alone. Also need to select MMP_SRAM for MMP_TDMA driver.
>>
>> Reported-by: Dan Williams
>> Signed-off-by: Qiao
On Thu, Dec 5, 2013 at 10:00 AM, Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Dec 4, 2013 at 5:36 PM, Qiao Zhou zhouq...@marvell.com wrote:
sram driver can be used by many chips besides CPU_MMP2, and so build
it alone. Also need to select MMP_SRAM for MMP_TDMA driver.
Reported-by: Dan
On Wed, Dec 4, 2013 at 4:21 PM, Qiao Zhou wrote:
> V1 -> V0:
> No need for help text for MMP_SRAM in Kconfig and move it into MMP_TDMA
> text in Kconfig.
>
> Qiao Zhou (2):
> arm: mmp: build sram driver alone
> dma: mmp-tdma: select sram driver
>
> arch/arm/mach-mmp/Kconfig |3 +++
>
On Wed, Dec 4, 2013 at 6:26 PM, Daniel Mack wrote:
> On 12/04/2013 11:22 AM, Thierry Reding wrote:
>> The conf and of_id variables are assigned but never used, so they may as
>> well just be removed.
>>
>> Signed-off-by: Thierry Reding
>
> Acked-by: Daniel Mack
>
>> ---
>>
On Wed, Dec 4, 2013 at 6:26 PM, Daniel Mack zon...@gmail.com wrote:
On 12/04/2013 11:22 AM, Thierry Reding wrote:
The conf and of_id variables are assigned but never used, so they may as
well just be removed.
Signed-off-by: Thierry Reding thierry.red...@gmail.com
Acked-by: Daniel Mack
On Wed, Dec 4, 2013 at 4:21 PM, Qiao Zhou zhouq...@marvell.com wrote:
V1 - V0:
No need for help text for MMP_SRAM in Kconfig and move it into MMP_TDMA
text in Kconfig.
Qiao Zhou (2):
arm: mmp: build sram driver alone
dma: mmp-tdma: select sram driver
arch/arm/mach-mmp/Kconfig |3
rivers/irqchip/irq-mmp.c
> index 2cb7cd0..470c5de 100644
> --- a/drivers/irqchip/irq-mmp.c
> +++ b/drivers/irqchip/irq-mmp.c
> @@ -22,7 +22,7 @@
> #include
>
> #include
> -#include
> +#include
>
> #include "irqchip.h"
>
> --
> 1.7.9.5
>
Ac
On Fri, Oct 11, 2013 at 4:23 PM, Neil Zhang wrote:
> Some of the Marvell SoCs use GIC as its interrupt controller,and ICU
> only used as wakeup logic. When AP subsystem is powered off, GIC will
> lose its context, the PMU will need ICU to wakeup the AP subsystem.
> So add wakeup entry for such
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