RE: [PATCH] PCI: Designware: remove wrong RC memory base/limit configuration

vger.kernel.org; helg...@kernel.org > Subject: Re: [PATCH] PCI: Designware: remove wrong RC memory base/limit > configuration > > Hi gabriele, > > [auto build test WARNING on pci/next] > [also build test WARNING on v4.6-rc3 next-20160415] > [if your patch is applied

RE: [PATCH] PCI: Designware: remove wrong RC memory base/limit configuration

vger.kernel.org; helg...@kernel.org > Subject: Re: [PATCH] PCI: Designware: remove wrong RC memory base/limit > configuration > > Hi gabriele, > > [auto build test WARNING on pci/next] > [also build test WARNING on v4.6-rc3 next-20160415] > [if your patch is applied

Re: [PATCH] PCI: Designware: remove wrong RC memory base/limit configuration

Hi gabriele, [auto build test WARNING on pci/next] [also build test WARNING on v4.6-rc3 next-20160415] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url:

Re: [PATCH] PCI: Designware: remove wrong RC memory base/limit configuration

Hi gabriele, [auto build test WARNING on pci/next] [also build test WARNING on v4.6-rc3 next-20160415] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url:

[PATCH] PCI: Designware: remove wrong RC memory base/limit configuration

From: gabriele paoloni Currently dw_pcie_setup_rc configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the cpu address (pp->mem_base) rather than the bus address (pp->mem_bus_addr): this is wrong and it

[PATCH] PCI: Designware: remove wrong RC memory base/limit configuration

From: gabriele paoloni Currently dw_pcie_setup_rc configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the cpu address (pp->mem_base) rather than the bus address (pp->mem_bus_addr): this is wrong and it is useless since the