Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

On Thu, Feb 18, 2021 at 05:21:16PM +0800, Icenowy Zheng wrote: > > > 于 2021年2月18日 GMT+08:00 下午5:18:39, Tobias Schramm 写到: > >Hi Icenowy, > > > > > We have introducee SDM-based accurate audio PLL on several > >> other SoCs. Some people is quite sensitive about audio-related > >things. > > > >

Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

于 2021年2月18日 GMT+08:00 下午5:18:39, Tobias Schramm 写到: >Hi Icenowy, > > > We have introducee SDM-based accurate audio PLL on several >> other SoCs. Some people is quite sensitive about audio-related >things. > > >While it is possible to support 24MHz * 128 / 25 / 5 = 24.576MHz >without >delta

Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

Hi Icenowy, > We have introducee SDM-based accurate audio PLL on several > other SoCs. Some people is quite sensitive about audio-related things. > While it is possible to support 24MHz * 128 / 25 / 5 = 24.576MHz without delta sigma modulation, matching 22.5792MHz is indeed not possible. I

Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

Hi Maxime, It's not really clear to me how that would help. The closest frequency we can provide for 24.576MHz would be 24580645 Hz, with N = 127, M = 31 and P = 4, so it would work with what we have already? As far as I'm aware the multiplier N ranges from 0 to 128 (offset of 1 That

Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

Hi Maxime, It's not really clear to me how that would help. The closest frequency we can provide for 24.576MHz would be 24580645 Hz, with N = 127, M = 31 and P = 4, so it would work with what we have already? As far as I'm aware the multiplier N ranges from 0 to 128 (offset of 1 from 0 to

Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

On Thu, Feb 18, 2021 at 4:06 PM Icenowy Zheng wrote: > > > > 于 2021年2月18日 GMT+08:00 下午3:58:35, Maxime Ripard 写到: > >Hi, > > > >On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote: > >> Previously the variable rate audio pll output was fixed to a divider > >of > >> four. This is

Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

于 2021年2月18日 GMT+08:00 下午3:58:35, Maxime Ripard 写到: >Hi, > >On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote: >> Previously the variable rate audio pll output was fixed to a divider >of >> four. This is unfortunately incompatible with generating commonly >used >> I2S core clock

Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

Hi, On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote: > Previously the variable rate audio pll output was fixed to a divider of > four. This is unfortunately incompatible with generating commonly used > I2S core clock rates like 24.576MHz from the 24MHz parent clock. > This commit

[PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output

Previously the variable rate audio pll output was fixed to a divider of four. This is unfortunately incompatible with generating commonly used I2S core clock rates like 24.576MHz from the 24MHz parent clock. This commit adds support for arbitrary audio pll output dividers to fix that.