RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
On Fri, 9 Apr 2021, Wu, Hao wrote:
On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
+
+static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
+{
+struct dfl_altera_spi *aspi = dev_get_drvdata(_dev->dev);
+
+platform_device_unregister(aspi->altr_spi);
+}
+
+#define FME_FEATURE_ID_MAX10_SPI0xe
+
+static const struct dfl_device_id dfl_spi_altera_ids[] = {
+{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
+{ }
+};
Maybe you can extend the Altera SPI driver with this part?
The file, drivers/spi/spi-altera.c, already has platform MODULE_
related
code. Wouldn't moving this code to that file produce conflicts?
I've seen other drivers support multiple busses, so it should be
possible, there might be nuances I'm missing in my brief look at this,
though.
I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
and the other one MODULE_DEVICE_TABLE(dfl, ...)
See drivers/i2c/busses/i2c-designware-platdrv.c for an example
(though
they might be guarding against what you describe with CONFIG_OF vs
CONFIG_ACPI)
If that doesn't work we could split it up into
altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
or something of that sort?
My point being, now that we have a bus, let's use it and develop
drivers
according to the Linux device model where possible :)
Agree. This does make sense from my side too. DFL core provides the
mechanism
to enumerate different IPs on FPGA, but each function driver needs to
go
to
related subsystem for review. : )
I understand that for FPGA case, it may have some additional logics for
specific
purposes based on common altera spi master IP, then additional code
for
I'm wondering if the additional logics are extensions for common spi-
altera.
Like
the
SPI_CORE_PARAMETER register, it is not within the register space of
spi-altera,
| | +-+
|DFL|--| ++ |
|BUS| | |SPI CORE| |
| | | |PARAM | |
| | | ++ |
| | | |
| | | ++ | +---+
| |Indirect| | |spi|
| |access +--+---|altera |
| |master | | +---+
| ++ |
+-+
a specific product still can be put into altera-spi-.c or altera-spi-dfl-
.c
So is it proper we integrate this feature into spi-altera? Previously
we have merged the dfl-n3000-nios, its spi part is very similar as
this driver. The dfl-n3000-nios make the spi-altera as a sub device.
Could we borrow the idea, or could we just integrate this driver in
dfl-n3000-nios?
Looks like those are enhancements of the IP. They can be applied even
I don't think the extra registers are the enhancement of the IP. They
are not part of the IP because they are not within the IP's register
space. They are like some external way of describing the IP like
Devicetree or ACPI.
Why adding new registers can't be consider as enhancement, those
changes serve the original IP and make it better, right? small mmio
footprint and parameter registers?
other buses are used, not only for DFL, like PCI device or platform device,
right? then why not put related code together with the original IP?
The code of devicetree or ACPI parsing are integrated in the IP drivers,
but for this case, it may not be proper for now, cause this style is not
formally introduced by any standard. IP specific parameters description
are not within the scope of DFL now.
Not sure if I get your point, but it's possible that we add some enhancements
to one IP then driver could be simplified and doesn't need devicetree any more.
For sure, it's IP specific thing, not the scope of DFL.
Then things become this: extension to IP to allow this IP to be used without
device tree, so that this IP can be used in DFL or PCI or other buses without
device tree?
It's good to extend an IP, but it needs a published SPEC and stable
register interfaces. For now, the spi-altera driver conforms to the
"SPI Core" chapter of the following spec:
https://www.intel.com/content/www/us/en/programmable/documentation/sf
o1400787952932.html
There is no info about the core parameter register and this specific
indirect access bus. That's why I don't see these additional parts as
the enhancements to spi-altera. This DFL feature is like a wrapper for
the spi-altera sub device.
It really doesn't matter, even if you consider this as an new IP, it's still a
SPI
Master, it's driver still need to be reviewed in drivers/spi subsystem. The
worst case is that we need to write a new spi-xxx.c driver, that's it.
From DFL part, DFL only can enumerate the common hardware resources,
but no good way to help thing like this, specific IP parameters (which handle
by devicetree in platform driver). So for some IPs , they still need some
extensions to avoid such dependency (on device tree for parameters). I guess
we may see more similar cases in the future.
Anyway, I think we reached
RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
> On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
> > > > > > > > > > +
> > > > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device
> > > > > > > > > > *dfl_dev)
> > > > > > > > > > +{
> > > > > > > > > > +struct dfl_altera_spi *aspi =
> > > > > > > > > > dev_get_drvdata(_dev->dev);
> > > > > > > > > > +
> > > > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > > > +}
> > > > > > > > > > +
> > > > > > > > > > +#define FME_FEATURE_ID_MAX10_SPI0xe
> > > > > > > > > > +
> > > > > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > > > > +{ }
> > > > > > > > > > +};
> > > > > > > > >
> > > > > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > > > > >
> > > > > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_
> > > related
> > > > > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > > > > >
> > > > > > > I've seen other drivers support multiple busses, so it should be
> > > > > > > possible, there might be nuances I'm missing in my brief look at
> > > > > > > this,
> > > > > > > though.
> > > > > > >
> > > > > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > > > > >
> > > > > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example
> (though
> > > > > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > > > > CONFIG_ACPI)
> > > > > > >
> > > > > > > If that doesn't work we could split it up into
> > > > > > >
> > > > > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > > > > or something of that sort?
> > > > > > >
> > > > > > > My point being, now that we have a bus, let's use it and develop
> drivers
> > > > > > > according to the Linux device model where possible :)
> > > > > >
> > > > > > Agree. This does make sense from my side too. DFL core provides the
> > > > > mechanism
> > > > > > to enumerate different IPs on FPGA, but each function driver needs
> > > > > > to
> go
> > > to
> > > > > > related subsystem for review. : )
> > > > > >
> > > > > > I understand that for FPGA case, it may have some additional logics
> > > > > > for
> > > specific
> > > > > > purposes based on common altera spi master IP, then additional code
> for
> > > > >
> > > > > I'm wondering if the additional logics are extensions for common spi-
> altera.
> > > Like
> > > > > the
> > > > > SPI_CORE_PARAMETER register, it is not within the register space of
> > > > > spi-altera,
> > > > >
> > > > >
> > > > > | | +-+
> > > > > |DFL|--| ++ |
> > > > > |BUS| | |SPI CORE| |
> > > > > | | | |PARAM | |
> > > > > | | | ++ |
> > > > > | | | |
> > > > > | | | ++ | +---+
> > > > > | |Indirect| | |spi|
> > > > > | |access +--+---|altera |
> > > > > | |master | | +---+
> > > > > | ++ |
> > > > > +-+
> > > > > > a specific product still can be put into altera-spi-.c or
> > > > > > altera-spi-dfl-
> > > .c
> > > > >
> > > > > So is it proper we integrate this feature into spi-altera? Previously
> > > > > we have merged the dfl-n3000-nios, its spi part is very similar as
> > > > > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > > > > Could we borrow the idea, or could we just integrate this driver in
> > > > > dfl-n3000-nios?
> > > >
> > > > Looks like those are enhancements of the IP. They can be applied even
> > >
> > > I don't think the extra registers are the enhancement of the IP. They
> > > are not part of the IP because they are not within the IP's register
> > > space. They are like some external way of describing the IP like
> > > Devicetree or ACPI.
> >
> > Why adding new registers can't be consider as enhancement, those
> > changes serve the original IP and make it better, right? small mmio
> > footprint and parameter registers?
> >
> > >
> > > > other buses are used, not only for DFL, like PCI device or platform
> > > > device,
> > > > right? then why not put related code together with the original IP?
> > >
> > > The code of devicetree or ACPI parsing are integrated in the IP drivers,
> > > but for this case, it may not be proper for now, cause this style is not
> > > formally introduced by any standard. IP specific parameters description
> > > are not within the scope of DFL now.
> >
> > Not sure if I get your point, but it's possible that we add some
> > enhancements
> > to one IP then driver could be simplified and doesn't need devicetree any
> > more.
> > For sure, it's IP specific thing, not the scope of DFL.
> >
> > Then things become this: extension to IP to allow this IP to be used without
> > device tree, so that
Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
> > > > > > > > > +
> > > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > > +{
> > > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(_dev->dev);
> > > > > > > > > +
> > > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > > +}
> > > > > > > > > +
> > > > > > > > > +#define FME_FEATURE_ID_MAX10_SPI0xe
> > > > > > > > > +
> > > > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > > > +{ }
> > > > > > > > > +};
> > > > > > > >
> > > > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > > > >
> > > > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_
> > related
> > > > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > > > >
> > > > > > I've seen other drivers support multiple busses, so it should be
> > > > > > possible, there might be nuances I'm missing in my brief look at
> > > > > > this,
> > > > > > though.
> > > > > >
> > > > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > > > >
> > > > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example
> > > > > > (though
> > > > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > > > CONFIG_ACPI)
> > > > > >
> > > > > > If that doesn't work we could split it up into
> > > > > >
> > > > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > > > or something of that sort?
> > > > > >
> > > > > > My point being, now that we have a bus, let's use it and develop
> > > > > > drivers
> > > > > > according to the Linux device model where possible :)
> > > > >
> > > > > Agree. This does make sense from my side too. DFL core provides the
> > > > mechanism
> > > > > to enumerate different IPs on FPGA, but each function driver needs to
> > > > > go
> > to
> > > > > related subsystem for review. : )
> > > > >
> > > > > I understand that for FPGA case, it may have some additional logics
> > > > > for
> > specific
> > > > > purposes based on common altera spi master IP, then additional code
> > > > > for
> > > >
> > > > I'm wondering if the additional logics are extensions for common
> > > > spi-altera.
> > Like
> > > > the
> > > > SPI_CORE_PARAMETER register, it is not within the register space of
> > > > spi-altera,
> > > >
> > > >
> > > > | | +-+
> > > > |DFL|--| ++ |
> > > > |BUS| | |SPI CORE| |
> > > > | | | |PARAM | |
> > > > | | | ++ |
> > > > | | | |
> > > > | | | ++ | +---+
> > > > | |Indirect| | |spi|
> > > > | |access +--+---|altera |
> > > > | |master | | +---+
> > > > | ++ |
> > > > +-+
> > > > > a specific product still can be put into altera-spi-.c or
> > > > > altera-spi-dfl-
> > .c
> > > >
> > > > So is it proper we integrate this feature into spi-altera? Previously
> > > > we have merged the dfl-n3000-nios, its spi part is very similar as
> > > > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > > > Could we borrow the idea, or could we just integrate this driver in
> > > > dfl-n3000-nios?
> > >
> > > Looks like those are enhancements of the IP. They can be applied even
> >
> > I don't think the extra registers are the enhancement of the IP. They
> > are not part of the IP because they are not within the IP's register
> > space. They are like some external way of describing the IP like
> > Devicetree or ACPI.
>
> Why adding new registers can't be consider as enhancement, those
> changes serve the original IP and make it better, right? small mmio
> footprint and parameter registers?
>
> >
> > > other buses are used, not only for DFL, like PCI device or platform
> > > device,
> > > right? then why not put related code together with the original IP?
> >
> > The code of devicetree or ACPI parsing are integrated in the IP drivers,
> > but for this case, it may not be proper for now, cause this style is not
> > formally introduced by any standard. IP specific parameters description
> > are not within the scope of DFL now.
>
> Not sure if I get your point, but it's possible that we add some enhancements
> to one IP then driver could be simplified and doesn't need devicetree any
> more.
> For sure, it's IP specific thing, not the scope of DFL.
>
> Then things become this: extension to IP to allow this IP to be used without
> device tree, so that this IP can be used in DFL or PCI or other buses without
> device tree?
It's good to extend an IP, but it needs a published SPEC and stable
register interfaces. For now, the spi-altera driver conforms to the
"SPI Core" chapter
RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
> > > > > > > > +
> > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(_dev->dev);
> > > > > > > > +
> > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +#define FME_FEATURE_ID_MAX10_SPI0xe
> > > > > > > > +
> > > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > > +{ }
> > > > > > > > +};
> > > > > > >
> > > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > > >
> > > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_
> related
> > > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > > >
> > > > > I've seen other drivers support multiple busses, so it should be
> > > > > possible, there might be nuances I'm missing in my brief look at this,
> > > > > though.
> > > > >
> > > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > > >
> > > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > > CONFIG_ACPI)
> > > > >
> > > > > If that doesn't work we could split it up into
> > > > >
> > > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > > or something of that sort?
> > > > >
> > > > > My point being, now that we have a bus, let's use it and develop
> > > > > drivers
> > > > > according to the Linux device model where possible :)
> > > >
> > > > Agree. This does make sense from my side too. DFL core provides the
> > > mechanism
> > > > to enumerate different IPs on FPGA, but each function driver needs to go
> to
> > > > related subsystem for review. : )
> > > >
> > > > I understand that for FPGA case, it may have some additional logics for
> specific
> > > > purposes based on common altera spi master IP, then additional code for
> > >
> > > I'm wondering if the additional logics are extensions for common
> > > spi-altera.
> Like
> > > the
> > > SPI_CORE_PARAMETER register, it is not within the register space of
> > > spi-altera,
> > >
> > >
> > > | | +-+
> > > |DFL|--| ++ |
> > > |BUS| | |SPI CORE| |
> > > | | | |PARAM | |
> > > | | | ++ |
> > > | | | |
> > > | | | ++ | +---+
> > > | |Indirect| | |spi|
> > > | |access +--+---|altera |
> > > | |master | | +---+
> > > | ++ |
> > > +-+
> > > > a specific product still can be put into altera-spi-.c or
> > > > altera-spi-dfl-
> .c
> > >
> > > So is it proper we integrate this feature into spi-altera? Previously
> > > we have merged the dfl-n3000-nios, its spi part is very similar as
> > > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > > Could we borrow the idea, or could we just integrate this driver in
> > > dfl-n3000-nios?
> >
> > Looks like those are enhancements of the IP. They can be applied even
>
> I don't think the extra registers are the enhancement of the IP. They
> are not part of the IP because they are not within the IP's register
> space. They are like some external way of describing the IP like
> Devicetree or ACPI.
Why adding new registers can't be consider as enhancement, those
changes serve the original IP and make it better, right? small mmio
footprint and parameter registers?
>
> > other buses are used, not only for DFL, like PCI device or platform device,
> > right? then why not put related code together with the original IP?
>
> The code of devicetree or ACPI parsing are integrated in the IP drivers,
> but for this case, it may not be proper for now, cause this style is not
> formally introduced by any standard. IP specific parameters description
> are not within the scope of DFL now.
Not sure if I get your point, but it's possible that we add some enhancements
to one IP then driver could be simplified and doesn't need devicetree any more.
For sure, it's IP specific thing, not the scope of DFL.
Then things become this: extension to IP to allow this IP to be used without
device tree, so that this IP can be used in DFL or PCI or other buses without
device tree?
Thanks
Hao
>
> >
> > The reason I suggested that function drivers which use DFL bus, still need
> > to go to related subsystem, because we know DFL quite well but may
> > not be the experts for every subsystem (e.g. SPI), and every IPs (e.g.
> > Altera SPI Master). Altera SPI Master driver maintainer could give more
> > valuable suggestions on your question if this feature can be integrated
> > into spi-altera or not. : )
>
> I agree that we put drivers to their related subsystem. I'm
RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
> On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > > >
> > > > > > > Hi Matthew,
> > > > > > >
> > > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > > matthew.gerl...@linux.intel.com wrote:
> > > > > > > > From: Matthew Gerlach
> > > > > > > >
> > > > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > > > controller. The SPI master is connected to an Intel SPI Slave
> > > > > > > > to
> > > > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > > > >
> > > > > > > > Signed-off-by: Matthew Gerlach
> > > > > > > > ---
> > > > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > > > drivers/fpga/Makefile | 1 +
> > > > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > > > ++
> > > > > > > > 3 files changed, 231 insertions(+)
> > > > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > > > >
> > > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > > index d591dd9..0a86994 100644
> > > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > > @@ -210,6 +210,15 @@ config
> FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > > >the card. It also instantiates the SPI master (spi-altera)
> > > > > > > > for
> > > > > > > >the card's BMC (Board Management Controller).
> > > > > > > >
> > > > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > > > +depends on FPGA_DFL
> > > > > > > > +select REGMAP
> > > > > > > > +help
> > > > > > > > + This is a DFL bus driver for the Altera SPI master
> > > > > > > > controller.
> > > > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > > > + bridge in a Intel MAX BMC.
> > > > > > > > +
> > > > > > > > config FPGA_DFL_PCI
> > > > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > > > depends on PCI && FPGA_DFL
> > > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > > > index 18dc9885..58a42ad 100644
> > > > > > > > --- a/drivers/fpga/Makefile
> > > > > > > > +++ b/drivers/fpga/Makefile
> > > > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o
> > > > > > > > dfl-afu-region.o
> dfl-
> > > > > afu-dma-region.o
> > > > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > > > >
> > > > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > > > nios.o
> > > > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > > > >
> > > > > > > > # Drivers for FPGAs which implement DFL
> > > > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c
> > > > > > > > b/drivers/fpga/dfl-spi-
> altera.c
> > > > > > > > new file mode 100644
> > > > > > > > index 000..9bec25fd
> > > > > > > > --- /dev/null
> > > > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > > > @@ -0,0 +1,221 @@
> > > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > > +/*
> > > > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > > > + *
> > > > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > > > + *
> > > > > > > > + * Authors:
> > > > > > > > + * Matthew Gerlach
> > > > > > > > + */
> > > > > > > > +
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +
> > > > > > > > +struct dfl_altera_spi {
> > > > > > > > +void __iomem *base;
> > > > > > > > +struct regmap *regmap;
> > > > > > > > +struct device *dev;
> > > > > > > > +struct platform_device *altr_spi;
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > > > +#define CLK_POLARITYBIT_ULL(14)
> > > > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > > > +
> > > > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > > > +#define INDIRECT_RD_DATA
Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
On Thu, Apr 08, 2021 at 11:53:06AM -0700, Moritz Fischer wrote:
> On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > > >
> > > > > > > Hi Matthew,
> > > > > > >
> > > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > > matthew.gerl...@linux.intel.com wrote:
> > > > > > > > From: Matthew Gerlach
> > > > > > > >
> > > > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > > > controller. The SPI master is connected to an Intel SPI Slave
> > > > > > > > to
> > > > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > > > >
> > > > > > > > Signed-off-by: Matthew Gerlach
> > > > > > > > ---
> > > > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > > > drivers/fpga/Makefile | 1 +
> > > > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > > > ++
> > > > > > > > 3 files changed, 231 insertions(+)
> > > > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > > > >
> > > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > > index d591dd9..0a86994 100644
> > > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > > >the card. It also instantiates the SPI master (spi-altera)
> > > > > > > > for
> > > > > > > >the card's BMC (Board Management Controller).
> > > > > > > >
> > > > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > > > +depends on FPGA_DFL
> > > > > > > > +select REGMAP
> > > > > > > > +help
> > > > > > > > + This is a DFL bus driver for the Altera SPI master
> > > > > > > > controller.
> > > > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > > > + bridge in a Intel MAX BMC.
> > > > > > > > +
> > > > > > > > config FPGA_DFL_PCI
> > > > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > > > depends on PCI && FPGA_DFL
> > > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > > > index 18dc9885..58a42ad 100644
> > > > > > > > --- a/drivers/fpga/Makefile
> > > > > > > > +++ b/drivers/fpga/Makefile
> > > > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o
> > > > > > > > dfl-afu-region.o dfl-
> > > > > afu-dma-region.o
> > > > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > > > >
> > > > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > > > nios.o
> > > > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > > > >
> > > > > > > > # Drivers for FPGAs which implement DFL
> > > > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c
> > > > > > > > b/drivers/fpga/dfl-spi-altera.c
> > > > > > > > new file mode 100644
> > > > > > > > index 000..9bec25fd
> > > > > > > > --- /dev/null
> > > > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > > > @@ -0,0 +1,221 @@
> > > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > > +/*
> > > > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > > > + *
> > > > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > > > + *
> > > > > > > > + * Authors:
> > > > > > > > + * Matthew Gerlach
> > > > > > > > + */
> > > > > > > > +
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +#include
> > > > > > > > +
> > > > > > > > +struct dfl_altera_spi {
> > > > > > > > +void __iomem *base;
> > > > > > > > +struct regmap *regmap;
> > > > > > > > +struct device *dev;
> > > > > > > > +struct platform_device *altr_spi;
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > > > +#define CLK_POLARITYBIT_ULL(14)
> > > > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > > > +
> > > > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > >
Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
On Thu, Apr 08, 2021 at 05:20:19PM +0800, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
> > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > matthew.gerl...@linux.intel.com wrote:
> > > > > > > From: Matthew Gerlach
> > > > > > >
> > > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > > >
> > > > > > > Signed-off-by: Matthew Gerlach
> > > > > > > ---
> > > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > > drivers/fpga/Makefile | 1 +
> > > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > > ++
> > > > > > > 3 files changed, 231 insertions(+)
> > > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > > >
> > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > index d591dd9..0a86994 100644
> > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > >the card. It also instantiates the SPI master (spi-altera) for
> > > > > > >the card's BMC (Board Management Controller).
> > > > > > >
> > > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > > +depends on FPGA_DFL
> > > > > > > +select REGMAP
> > > > > > > +help
> > > > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > > + bridge in a Intel MAX BMC.
> > > > > > > +
> > > > > > > config FPGA_DFL_PCI
> > > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > > depends on PCI && FPGA_DFL
> > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > > index 18dc9885..58a42ad 100644
> > > > > > > --- a/drivers/fpga/Makefile
> > > > > > > +++ b/drivers/fpga/Makefile
> > > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
> > > > > > > dfl-
> > > > afu-dma-region.o
> > > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > > >
> > > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > > nios.o
> > > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > > >
> > > > > > > # Drivers for FPGAs which implement DFL
> > > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c
> > > > > > > b/drivers/fpga/dfl-spi-altera.c
> > > > > > > new file mode 100644
> > > > > > > index 000..9bec25fd
> > > > > > > --- /dev/null
> > > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > > @@ -0,0 +1,221 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > +/*
> > > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > > + *
> > > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > > + *
> > > > > > > + * Authors:
> > > > > > > + * Matthew Gerlach
> > > > > > > + */
> > > > > > > +
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +
> > > > > > > +struct dfl_altera_spi {
> > > > > > > +void __iomem *base;
> > > > > > > +struct regmap *regmap;
> > > > > > > +struct device *dev;
> > > > > > > +struct platform_device *altr_spi;
> > > > > > > +};
> > > > > > > +
> > > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > > +#define CLK_POLARITYBIT_ULL(14)
> > > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > > +
> > > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > > +#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
> > > > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > > > +#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
> > > > > > > +#define INDIRECT_TIMEOUT1
> > > > > > >
Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
> > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > matthew.gerl...@linux.intel.com wrote:
> > > > > > > From: Matthew Gerlach
> > > > > > >
> > > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > > >
> > > > > > > Signed-off-by: Matthew Gerlach
> > > > > > > ---
> > > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > > drivers/fpga/Makefile | 1 +
> > > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > > ++
> > > > > > > 3 files changed, 231 insertions(+)
> > > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > > >
> > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > index d591dd9..0a86994 100644
> > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > >the card. It also instantiates the SPI master (spi-altera) for
> > > > > > >the card's BMC (Board Management Controller).
> > > > > > >
> > > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > > +depends on FPGA_DFL
> > > > > > > +select REGMAP
> > > > > > > +help
> > > > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > > + bridge in a Intel MAX BMC.
> > > > > > > +
> > > > > > > config FPGA_DFL_PCI
> > > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > > depends on PCI && FPGA_DFL
> > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > > index 18dc9885..58a42ad 100644
> > > > > > > --- a/drivers/fpga/Makefile
> > > > > > > +++ b/drivers/fpga/Makefile
> > > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
> > > > > > > dfl-
> > > > afu-dma-region.o
> > > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > > >
> > > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > > nios.o
> > > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > > >
> > > > > > > # Drivers for FPGAs which implement DFL
> > > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c
> > > > > > > b/drivers/fpga/dfl-spi-altera.c
> > > > > > > new file mode 100644
> > > > > > > index 000..9bec25fd
> > > > > > > --- /dev/null
> > > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > > @@ -0,0 +1,221 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > +/*
> > > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > > + *
> > > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > > + *
> > > > > > > + * Authors:
> > > > > > > + * Matthew Gerlach
> > > > > > > + */
> > > > > > > +
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +#include
> > > > > > > +
> > > > > > > +struct dfl_altera_spi {
> > > > > > > +void __iomem *base;
> > > > > > > +struct regmap *regmap;
> > > > > > > +struct device *dev;
> > > > > > > +struct platform_device *altr_spi;
> > > > > > > +};
> > > > > > > +
> > > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > > +#define CLK_POLARITYBIT_ULL(14)
> > > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > > +
> > > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > > +#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
> > > > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > > > +#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
> > > > > > > +#define INDIRECT_TIMEOUT1
> > > > > > >
RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
> On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > >
> > > > > Hi Matthew,
> > > > >
> > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > matthew.gerl...@linux.intel.com wrote:
> > > > > > From: Matthew Gerlach
> > > > > >
> > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > >
> > > > > > Signed-off-by: Matthew Gerlach
> > > > > > ---
> > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > drivers/fpga/Makefile | 1 +
> > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > ++
> > > > > > 3 files changed, 231 insertions(+)
> > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > >
> > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > index d591dd9..0a86994 100644
> > > > > > --- a/drivers/fpga/Kconfig
> > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > >the card. It also instantiates the SPI master (spi-altera) for
> > > > > >the card's BMC (Board Management Controller).
> > > > > >
> > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > +depends on FPGA_DFL
> > > > > > +select REGMAP
> > > > > > +help
> > > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > + bridge in a Intel MAX BMC.
> > > > > > +
> > > > > > config FPGA_DFL_PCI
> > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > depends on PCI && FPGA_DFL
> > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > index 18dc9885..58a42ad 100644
> > > > > > --- a/drivers/fpga/Makefile
> > > > > > +++ b/drivers/fpga/Makefile
> > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
> > > > > > dfl-
> > > afu-dma-region.o
> > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > >
> > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > nios.o
> > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > >
> > > > > > # Drivers for FPGAs which implement DFL
> > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c
> > > > > > b/drivers/fpga/dfl-spi-altera.c
> > > > > > new file mode 100644
> > > > > > index 000..9bec25fd
> > > > > > --- /dev/null
> > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > @@ -0,0 +1,221 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > +/*
> > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > + *
> > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > + *
> > > > > > + * Authors:
> > > > > > + * Matthew Gerlach
> > > > > > + */
> > > > > > +
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +#include
> > > > > > +
> > > > > > +struct dfl_altera_spi {
> > > > > > +void __iomem *base;
> > > > > > +struct regmap *regmap;
> > > > > > +struct device *dev;
> > > > > > +struct platform_device *altr_spi;
> > > > > > +};
> > > > > > +
> > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > +#define CLK_POLARITYBIT_ULL(14)
> > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > +
> > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > +#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
> > > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > > +#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
> > > > > > +#define INDIRECT_TIMEOUT1
> > > > > > +
> > > > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > > > + unsigned int *val)
> > > > > > +{
> > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > +void __iomem *base = aspi->base;
> > > > > > +int loops;
> > > > > > +u64 v;
> > > > > > +
> >
Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > >
> > > > Hi Matthew,
> > > >
> > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > matthew.gerl...@linux.intel.com wrote:
> > > > > From: Matthew Gerlach
> > > > >
> > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > >
> > > > > Signed-off-by: Matthew Gerlach
> > > > > ---
> > > > > drivers/fpga/Kconfig | 9 ++
> > > > > drivers/fpga/Makefile | 1 +
> > > > > drivers/fpga/dfl-spi-altera.c | 221
> > ++
> > > > > 3 files changed, 231 insertions(+)
> > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > >
> > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > index d591dd9..0a86994 100644
> > > > > --- a/drivers/fpga/Kconfig
> > > > > +++ b/drivers/fpga/Kconfig
> > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > >the card. It also instantiates the SPI master (spi-altera) for
> > > > >the card's BMC (Board Management Controller).
> > > > >
> > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > +depends on FPGA_DFL
> > > > > +select REGMAP
> > > > > +help
> > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > + bridge in a Intel MAX BMC.
> > > > > +
> > > > > config FPGA_DFL_PCI
> > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > depends on PCI && FPGA_DFL
> > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > index 18dc9885..58a42ad 100644
> > > > > --- a/drivers/fpga/Makefile
> > > > > +++ b/drivers/fpga/Makefile
> > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-
> > afu-dma-region.o
> > > > > dfl-afu-objs += dfl-afu-error.o
> > > > >
> > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > nios.o
> > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > >
> > > > > # Drivers for FPGAs which implement DFL
> > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > diff --git a/drivers/fpga/dfl-spi-altera.c
> > > > > b/drivers/fpga/dfl-spi-altera.c
> > > > > new file mode 100644
> > > > > index 000..9bec25fd
> > > > > --- /dev/null
> > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > @@ -0,0 +1,221 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > +/*
> > > > > + * DFL bus driver for Altera SPI Master
> > > > > + *
> > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > + *
> > > > > + * Authors:
> > > > > + * Matthew Gerlach
> > > > > + */
> > > > > +
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +#include
> > > > > +
> > > > > +struct dfl_altera_spi {
> > > > > +void __iomem *base;
> > > > > +struct regmap *regmap;
> > > > > +struct device *dev;
> > > > > +struct platform_device *altr_spi;
> > > > > +};
> > > > > +
> > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > +#define SHIFT_MODE_MSB 0
> > > > > +#define SHIFT_MODE_LSB 1
> > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > +#define CLK_POLARITYBIT_ULL(14)
> > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > +
> > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > +#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
> > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > +#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
> > > > > +#define INDIRECT_TIMEOUT1
> > > > > +
> > > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > > + unsigned int *val)
> > > > > +{
> > > > > +struct dfl_altera_spi *aspi = context;
> > > > > +void __iomem *base = aspi->base;
> > > > > +int loops;
> > > > > +u64 v;
> > > > > +
> > > > > +writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > > +
> > > > > +loops = 0;
> > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > +cpu_relax();
> > > > > +
> > > > > +if
RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
> > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> >
> > > Hi Matthew,
> > >
> > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> matthew.gerl...@linux.intel.com wrote:
> > > > From: Matthew Gerlach
> > > >
> > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > >
> > > > Signed-off-by: Matthew Gerlach
> > > > ---
> > > > drivers/fpga/Kconfig | 9 ++
> > > > drivers/fpga/Makefile | 1 +
> > > > drivers/fpga/dfl-spi-altera.c | 221
> ++
> > > > 3 files changed, 231 insertions(+)
> > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > >
> > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > index d591dd9..0a86994 100644
> > > > --- a/drivers/fpga/Kconfig
> > > > +++ b/drivers/fpga/Kconfig
> > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > the card. It also instantiates the SPI master (spi-altera) for
> > > > the card's BMC (Board Management Controller).
> > > >
> > > > +config FPGA_DFL_SPI_ALTERA
> > > > + tristate "FPGA DFL Altera SPI Master Driver"
> > > > + depends on FPGA_DFL
> > > > + select REGMAP
> > > > + help
> > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > + bridge in a Intel MAX BMC.
> > > > +
> > > > config FPGA_DFL_PCI
> > > > tristate "FPGA DFL PCIe Device Driver"
> > > > depends on PCI && FPGA_DFL
> > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > index 18dc9885..58a42ad 100644
> > > > --- a/drivers/fpga/Makefile
> > > > +++ b/drivers/fpga/Makefile
> > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-
> afu-dma-region.o
> > > > dfl-afu-objs += dfl-afu-error.o
> > > >
> > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> nios.o
> > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA) += dfl-spi-altera.o
> > > >
> > > > # Drivers for FPGAs which implement DFL
> > > > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> > > > diff --git a/drivers/fpga/dfl-spi-altera.c
> > > > b/drivers/fpga/dfl-spi-altera.c
> > > > new file mode 100644
> > > > index 000..9bec25fd
> > > > --- /dev/null
> > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > @@ -0,0 +1,221 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * DFL bus driver for Altera SPI Master
> > > > + *
> > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > + *
> > > > + * Authors:
> > > > + * Matthew Gerlach
> > > > + */
> > > > +
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +
> > > > +struct dfl_altera_spi {
> > > > + void __iomem *base;
> > > > + struct regmap *regmap;
> > > > + struct device *dev;
> > > > + struct platform_device *altr_spi;
> > > > +};
> > > > +
> > > > +#define SPI_CORE_PARAMETER 0x8
> > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > +#define SHIFT_MODE_MSB 0
> > > > +#define SHIFT_MODE_LSB 1
> > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > +#define CLK_POLARITYBIT_ULL(14)
> > > > +#define CLK_PHASE BIT_ULL(15)
> > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > +
> > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > +#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
> > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > +#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
> > > > +#define INDIRECT_TIMEOUT1
> > > > +
> > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > +unsigned int *val)
> > > > +{
> > > > + struct dfl_altera_spi *aspi = context;
> > > > + void __iomem *base = aspi->base;
> > > > + int loops;
> > > > + u64 v;
> > > > +
> > > > + writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > +
> > > > + loops = 0;
> > > > + while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > + cpu_relax();
> > > > +
> > > > + if (loops >= INDIRECT_TIMEOUT) {
> > > > + pr_err("%s timed out
Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
Hi Matthew,
On Tue, Apr 06, 2021 at 09:05:35AM -0700, matthew.gerl...@linux.intel.com wrote:
>
> Hi Moritz,
>
> On Mon, 5 Apr 2021, Moritz Fischer wrote:
>
> > Hi Matthew,
> >
> > On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com
> > wrote:
> > > From: Matthew Gerlach
> > >
> > > This patch adds DFL bus driver for the Altera SPI Master
> > > controller. The SPI master is connected to an Intel SPI Slave to
> > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > >
> > > Signed-off-by: Matthew Gerlach
> > > ---
> > > drivers/fpga/Kconfig | 9 ++
> > > drivers/fpga/Makefile | 1 +
> > > drivers/fpga/dfl-spi-altera.c | 221
> > > ++
> > > 3 files changed, 231 insertions(+)
> > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > >
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > index d591dd9..0a86994 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > the card. It also instantiates the SPI master (spi-altera) for
> > > the card's BMC (Board Management Controller).
> > >
> > > +config FPGA_DFL_SPI_ALTERA
> > > + tristate "FPGA DFL Altera SPI Master Driver"
> > > + depends on FPGA_DFL
> > > + select REGMAP
> > > + help
> > > + This is a DFL bus driver for the Altera SPI master controller.
> > > + The SPI master is connected to a SPI slave to Avalon Master
> > > + bridge in a Intel MAX BMC.
> > > +
> > > config FPGA_DFL_PCI
> > > tristate "FPGA DFL PCIe Device Driver"
> > > depends on PCI && FPGA_DFL
> > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > index 18dc9885..58a42ad 100644
> > > --- a/drivers/fpga/Makefile
> > > +++ b/drivers/fpga/Makefile
> > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
> > > dfl-afu-dma-region.o
> > > dfl-afu-objs += dfl-afu-error.o
> > >
> > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
> > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > >
> > > # Drivers for FPGAs which implement DFL
> > > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> > > new file mode 100644
> > > index 000..9bec25fd
> > > --- /dev/null
> > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > @@ -0,0 +1,221 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * DFL bus driver for Altera SPI Master
> > > + *
> > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > + *
> > > + * Authors:
> > > + * Matthew Gerlach
> > > + */
> > > +
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +
> > > +struct dfl_altera_spi {
> > > + void __iomem *base;
> > > + struct regmap *regmap;
> > > + struct device *dev;
> > > + struct platform_device *altr_spi;
> > > +};
> > > +
> > > +#define SPI_CORE_PARAMETER 0x8
> > > +#define SHIFT_MODE BIT_ULL(1)
> > > +#define SHIFT_MODE_MSB 0
> > > +#define SHIFT_MODE_LSB 1
> > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > +#define CLK_POLARITYBIT_ULL(14)
> > > +#define CLK_PHASE BIT_ULL(15)
> > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > +
> > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > +#define INDIRECT_WR BIT_ULL(8)
> > > +#define INDIRECT_RD BIT_ULL(9)
> > > +#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
> > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > +#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
> > > +#define INDIRECT_TIMEOUT1
> > > +
> > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > + unsigned int *val)
> > > +{
> > > + struct dfl_altera_spi *aspi = context;
> > > + void __iomem *base = aspi->base;
> > > + int loops;
> > > + u64 v;
> > > +
> > > + writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > +
> > > + loops = 0;
> > > + while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > +(loops++ < INDIRECT_TIMEOUT))
> > > + cpu_relax();
> > > +
> > > + if (loops >= INDIRECT_TIMEOUT) {
> > > + pr_err("%s timed out %d\n", __func__, loops);
> > > + return -ETIME;
> > > + }
> > > +
> > > + v = readq(base + INDIRECT_RD_DATA);
> > > +
> > > + *val = v & INDIRECT_DATA_MASK;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > +
Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
Hi Moritz,
On Mon, 5 Apr 2021, Moritz Fischer wrote:
Hi Matthew,
On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
This patch adds DFL bus driver for the Altera SPI Master
controller. The SPI master is connected to an Intel SPI Slave to
Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig | 9 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/dfl-spi-altera.c | 221 ++
3 files changed, 231 insertions(+)
create mode 100644 drivers/fpga/dfl-spi-altera.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index d591dd9..0a86994 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
the card. It also instantiates the SPI master (spi-altera) for
the card's BMC (Board Management Controller).
+config FPGA_DFL_SPI_ALTERA
+ tristate "FPGA DFL Altera SPI Master Driver"
+ depends on FPGA_DFL
+ select REGMAP
+ help
+ This is a DFL bus driver for the Altera SPI master controller.
+ The SPI master is connected to a SPI slave to Avalon Master
+ bridge in a Intel MAX BMC.
+
config FPGA_DFL_PCI
tristate "FPGA DFL PCIe Device Driver"
depends on PCI && FPGA_DFL
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885..58a42ad 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
dfl-afu-dma-region.o
dfl-afu-objs += dfl-afu-error.o
obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-nios.o
+obj-$(CONFIG_FPGA_DFL_SPI_ALTERA) += dfl-spi-altera.o
# Drivers for FPGAs which implement DFL
obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
new file mode 100644
index 000..9bec25fd
--- /dev/null
+++ b/drivers/fpga/dfl-spi-altera.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DFL bus driver for Altera SPI Master
+ *
+ * Copyright (C) 2020 Intel Corporation, Inc.
+ *
+ * Authors:
+ * Matthew Gerlach
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct dfl_altera_spi {
+ void __iomem *base;
+ struct regmap *regmap;
+ struct device *dev;
+ struct platform_device *altr_spi;
+};
+
+#define SPI_CORE_PARAMETER 0x8
+#define SHIFT_MODE BIT_ULL(1)
+#define SHIFT_MODE_MSB 0
+#define SHIFT_MODE_LSB 1
+#define DATA_WIDTH GENMASK_ULL(7, 2)
+#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
+#define CLK_POLARITYBIT_ULL(14)
+#define CLK_PHASE BIT_ULL(15)
+#define PERIPHERAL_ID GENMASK_ULL(47, 32)
+#define SPI_CLK GENMASK_ULL(31, 22)
+#define SPI_INDIRECT_ACC_OFST 0x10
+
+#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
+#define INDIRECT_WR BIT_ULL(8)
+#define INDIRECT_RD BIT_ULL(9)
+#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
+#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
+#define INDIRECT_DEBUG BIT_ULL(32)
+#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
+#define INDIRECT_TIMEOUT1
+
+static int indirect_bus_reg_read(void *context, unsigned int reg,
+unsigned int *val)
+{
+ struct dfl_altera_spi *aspi = context;
+ void __iomem *base = aspi->base;
+ int loops;
+ u64 v;
+
+ writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
+
+ loops = 0;
+ while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
+ (loops++ < INDIRECT_TIMEOUT))
+ cpu_relax();
+
+ if (loops >= INDIRECT_TIMEOUT) {
+ pr_err("%s timed out %d\n", __func__, loops);
+ return -ETIME;
+ }
+
+ v = readq(base + INDIRECT_RD_DATA);
+
+ *val = v & INDIRECT_DATA_MASK;
+
+ return 0;
+}
+
+static int indirect_bus_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct dfl_altera_spi *aspi = context;
+ void __iomem *base = aspi->base;
+ int loops;
+
+ writeq(val, base + INDIRECT_WR_DATA);
+ writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
+
+ loops = 0;
+ while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
+ (loops++ < INDIRECT_TIMEOUT))
+ cpu_relax();
+
+ if (loops >= INDIRECT_TIMEOUT) {
+ pr_err("%s timed out %d\n", __func__, loops);
+ return -ETIME;
+ }
+ return 0;
+}
+
+static const struct regmap_config indirect_regbus_cfg = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+
Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
Hi Matthew,
On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com wrote:
> From: Matthew Gerlach
>
> This patch adds DFL bus driver for the Altera SPI Master
> controller. The SPI master is connected to an Intel SPI Slave to
> Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
>
> Signed-off-by: Matthew Gerlach
> ---
> drivers/fpga/Kconfig | 9 ++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/dfl-spi-altera.c | 221
> ++
> 3 files changed, 231 insertions(+)
> create mode 100644 drivers/fpga/dfl-spi-altera.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index d591dd9..0a86994 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> the card. It also instantiates the SPI master (spi-altera) for
> the card's BMC (Board Management Controller).
>
> +config FPGA_DFL_SPI_ALTERA
> + tristate "FPGA DFL Altera SPI Master Driver"
> + depends on FPGA_DFL
> + select REGMAP
> + help
> + This is a DFL bus driver for the Altera SPI master controller.
> + The SPI master is connected to a SPI slave to Avalon Master
> + bridge in a Intel MAX BMC.
> +
> config FPGA_DFL_PCI
> tristate "FPGA DFL PCIe Device Driver"
> depends on PCI && FPGA_DFL
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 18dc9885..58a42ad 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
> dfl-afu-dma-region.o
> dfl-afu-objs += dfl-afu-error.o
>
> obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
> +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
>
> # Drivers for FPGAs which implement DFL
> obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> new file mode 100644
> index 000..9bec25fd
> --- /dev/null
> +++ b/drivers/fpga/dfl-spi-altera.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DFL bus driver for Altera SPI Master
> + *
> + * Copyright (C) 2020 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Matthew Gerlach
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct dfl_altera_spi {
> + void __iomem *base;
> + struct regmap *regmap;
> + struct device *dev;
> + struct platform_device *altr_spi;
> +};
> +
> +#define SPI_CORE_PARAMETER 0x8
> +#define SHIFT_MODE BIT_ULL(1)
> +#define SHIFT_MODE_MSB 0
> +#define SHIFT_MODE_LSB 1
> +#define DATA_WIDTH GENMASK_ULL(7, 2)
> +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> +#define CLK_POLARITYBIT_ULL(14)
> +#define CLK_PHASE BIT_ULL(15)
> +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> +#define SPI_CLK GENMASK_ULL(31, 22)
> +#define SPI_INDIRECT_ACC_OFST 0x10
> +
> +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> +#define INDIRECT_WR BIT_ULL(8)
> +#define INDIRECT_RD BIT_ULL(9)
> +#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
> +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> +#define INDIRECT_DEBUG BIT_ULL(32)
> +#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
> +#define INDIRECT_TIMEOUT1
> +
> +static int indirect_bus_reg_read(void *context, unsigned int reg,
> + unsigned int *val)
> +{
> + struct dfl_altera_spi *aspi = context;
> + void __iomem *base = aspi->base;
> + int loops;
> + u64 v;
> +
> + writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> +
> + loops = 0;
> + while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> +(loops++ < INDIRECT_TIMEOUT))
> + cpu_relax();
> +
> + if (loops >= INDIRECT_TIMEOUT) {
> + pr_err("%s timed out %d\n", __func__, loops);
> + return -ETIME;
> + }
> +
> + v = readq(base + INDIRECT_RD_DATA);
> +
> + *val = v & INDIRECT_DATA_MASK;
> +
> + return 0;
> +}
> +
> +static int indirect_bus_reg_write(void *context, unsigned int reg,
> + unsigned int val)
> +{
> + struct dfl_altera_spi *aspi = context;
> + void __iomem *base = aspi->base;
> + int loops;
> +
> + writeq(val, base + INDIRECT_WR_DATA);
> + writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> +
> + loops = 0;
> + while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> +(loops++ < INDIRECT_TIMEOUT))
> + cpu_relax();
> +
> + if (loops >= INDIRECT_TIMEOUT) {
> + pr_err("%s timed out %d\n", __func__, loops);
> + return -ETIME;
> + }
> + return 0;
[PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master
From: Matthew Gerlach
This patch adds DFL bus driver for the Altera SPI Master
controller. The SPI master is connected to an Intel SPI Slave to
Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
Signed-off-by: Matthew Gerlach
---
drivers/fpga/Kconfig | 9 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/dfl-spi-altera.c | 221 ++
3 files changed, 231 insertions(+)
create mode 100644 drivers/fpga/dfl-spi-altera.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index d591dd9..0a86994 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
the card. It also instantiates the SPI master (spi-altera) for
the card's BMC (Board Management Controller).
+config FPGA_DFL_SPI_ALTERA
+ tristate "FPGA DFL Altera SPI Master Driver"
+ depends on FPGA_DFL
+ select REGMAP
+ help
+ This is a DFL bus driver for the Altera SPI master controller.
+ The SPI master is connected to a SPI slave to Avalon Master
+ bridge in a Intel MAX BMC.
+
config FPGA_DFL_PCI
tristate "FPGA DFL PCIe Device Driver"
depends on PCI && FPGA_DFL
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885..58a42ad 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
dfl-afu-dma-region.o
dfl-afu-objs += dfl-afu-error.o
obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-nios.o
+obj-$(CONFIG_FPGA_DFL_SPI_ALTERA) += dfl-spi-altera.o
# Drivers for FPGAs which implement DFL
obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
new file mode 100644
index 000..9bec25fd
--- /dev/null
+++ b/drivers/fpga/dfl-spi-altera.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DFL bus driver for Altera SPI Master
+ *
+ * Copyright (C) 2020 Intel Corporation, Inc.
+ *
+ * Authors:
+ * Matthew Gerlach
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct dfl_altera_spi {
+ void __iomem *base;
+ struct regmap *regmap;
+ struct device *dev;
+ struct platform_device *altr_spi;
+};
+
+#define SPI_CORE_PARAMETER 0x8
+#define SHIFT_MODE BIT_ULL(1)
+#define SHIFT_MODE_MSB 0
+#define SHIFT_MODE_LSB 1
+#define DATA_WIDTH GENMASK_ULL(7, 2)
+#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
+#define CLK_POLARITYBIT_ULL(14)
+#define CLK_PHASE BIT_ULL(15)
+#define PERIPHERAL_ID GENMASK_ULL(47, 32)
+#define SPI_CLK GENMASK_ULL(31, 22)
+#define SPI_INDIRECT_ACC_OFST 0x10
+
+#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
+#define INDIRECT_WR BIT_ULL(8)
+#define INDIRECT_RD BIT_ULL(9)
+#define INDIRECT_RD_DATA(SPI_INDIRECT_ACC_OFST+0x8)
+#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
+#define INDIRECT_DEBUG BIT_ULL(32)
+#define INDIRECT_WR_DATA(SPI_INDIRECT_ACC_OFST+0x10)
+#define INDIRECT_TIMEOUT1
+
+static int indirect_bus_reg_read(void *context, unsigned int reg,
+unsigned int *val)
+{
+ struct dfl_altera_spi *aspi = context;
+ void __iomem *base = aspi->base;
+ int loops;
+ u64 v;
+
+ writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
+
+ loops = 0;
+ while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
+ (loops++ < INDIRECT_TIMEOUT))
+ cpu_relax();
+
+ if (loops >= INDIRECT_TIMEOUT) {
+ pr_err("%s timed out %d\n", __func__, loops);
+ return -ETIME;
+ }
+
+ v = readq(base + INDIRECT_RD_DATA);
+
+ *val = v & INDIRECT_DATA_MASK;
+
+ return 0;
+}
+
+static int indirect_bus_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct dfl_altera_spi *aspi = context;
+ void __iomem *base = aspi->base;
+ int loops;
+
+ writeq(val, base + INDIRECT_WR_DATA);
+ writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
+
+ loops = 0;
+ while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
+ (loops++ < INDIRECT_TIMEOUT))
+ cpu_relax();
+
+ if (loops >= INDIRECT_TIMEOUT) {
+ pr_err("%s timed out %d\n", __func__, loops);
+ return -ETIME;
+ }
+ return 0;
+}
+
+static const struct regmap_config indirect_regbus_cfg = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .fast_io = true,
+
+ .reg_write = indirect_bus_reg_write,
+ .reg_read = indirect_bus_reg_read,
+};
+
+static struct spi_board_info m10_bmc_info
