Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Thu, Jun 02, 2016 at 05:00:19PM +, David Carrillo-Cisneros wrote: > LBR_FROM_FLAG_MISPRED is at bit 63 so the bitshift wouldnt work . But I can > clean the bits unconditionally of the value, just as you said for the read > case. Argh, missed that. Ok, something like so then: #define

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Thu, Jun 02, 2016 at 05:00:19PM +, David Carrillo-Cisneros wrote: > LBR_FROM_FLAG_MISPRED is at bit 63 so the bitshift wouldnt work . But I can > clean the bits unconditionally of the value, just as you said for the read > case. Argh, missed that. Ok, something like so then: #define

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

> $ ./lbr_perf record --call-graph lbr -e cycles:k ./cqm_easy > > where lbr_perf is the patched perf tool, that allows to specify :k > on lbr mode. The above command will trigger a #GPF : Why would you want to do that? We usually have frame pointers for the kernel, so callstack LBR for the

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

> $ ./lbr_perf record --call-graph lbr -e cycles:k ./cqm_easy > > where lbr_perf is the patched perf tool, that allows to specify :k > on lbr mode. The above command will trigger a #GPF : Why would you want to do that? We usually have frame pointers for the kernel, so callstack LBR for the

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > Reviewed-by: Stephane Eranian Did you really? Don't just blanket issue these Stephane, look at the bloody patches before they go out please!

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > Reviewed-by: Stephane Eranian Did you really? Don't just blanket issue these Stephane, look at the bloody patches before they go out please!

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c > index 2dca66c..6aa2d8a 100644 > --- a/arch/x86/events/intel/lbr.c > +++ b/arch/x86/events/intel/lbr.c > @@ -80,6 +80,7 @@ static enum { > #define

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c > index 2dca66c..6aa2d8a 100644 > --- a/arch/x86/events/intel/lbr.c > +++ b/arch/x86/events/intel/lbr.c > @@ -80,6 +80,7 @@ static enum { > #define

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > @@ -536,6 +597,7 @@ static int intel_pmu_setup_sw_lbr_filter(struct > perf_event *event) > u64 br_type = event->attr.branch_sample_type; > int mask = 0; > > + > if (br_type & PERF_SAMPLE_BRANCH_USER) >

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > @@ -536,6 +597,7 @@ static int intel_pmu_setup_sw_lbr_filter(struct > perf_event *event) > u64 br_type = event->attr.branch_sample_type; > int mask = 0; > > + > if (br_type & PERF_SAMPLE_BRANCH_USER) >

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index a5e52ad4..1ce172d 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -3309,6 +3309,7 @@ static void

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index a5e52ad4..1ce172d 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -3309,6 +3309,7 @@ static void

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > + /* quirk only affects validation in wrmsr, so wrmsrl'value > + * should equal rdmsrl's one even with the quirk. > + */ broken comment style

Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote: > + /* quirk only affects validation in wrmsr, so wrmsrl'value > + * should equal rdmsrl's one even with the quirk. > + */ broken comment style

[PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

Intel's SDM states that bits 61:62 in MSR_LAST_BRANCH_FROM_x are the TSX flags for formats with LBR_TSX flags (i.e. LBR_FORMAT_EIP_EFLAGS2). However, when the CPU has TSX support deactivated, bits 61:62 actually behave as follows: - For wrmsr, bits 61:62 are considered part of the

[PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

Intel's SDM states that bits 61:62 in MSR_LAST_BRANCH_FROM_x are the TSX flags for formats with LBR_TSX flags (i.e. LBR_FORMAT_EIP_EFLAGS2). However, when the CPU has TSX support deactivated, bits 61:62 actually behave as follows: - For wrmsr, bits 61:62 are considered part of the