Hi Marc,
2017-08-22 17:20 GMT+09:00 Marc Zyngier :
> On 22/08/17 03:03, Masahiro Yamada wrote:
>> Hi Mark,
>>
>>
>> 2017-08-21 19:25 GMT+09:00 Marc Zyngier :
>>
+static struct irq_chip uniphier_aidet_irq_chip = {
+ .name = "AIDET",
+
Hi Marc,
2017-08-22 17:20 GMT+09:00 Marc Zyngier :
> On 22/08/17 03:03, Masahiro Yamada wrote:
>> Hi Mark,
>>
>>
>> 2017-08-21 19:25 GMT+09:00 Marc Zyngier :
>>
+static struct irq_chip uniphier_aidet_irq_chip = {
+ .name = "AIDET",
+ .irq_mask = irq_chip_mask_parent,
+
On Mon, Aug 21, 2017 at 07:01:03PM +0900, Masahiro Yamada wrote:
> UniPhier SoCs contain AIDET (ARM Interrupt Detector). This is intended
> to provide additional features that are not covered by GIC. The main
> purpose is to provide logic inverter to support low level and falling
> edge trigger
On Mon, Aug 21, 2017 at 07:01:03PM +0900, Masahiro Yamada wrote:
> UniPhier SoCs contain AIDET (ARM Interrupt Detector). This is intended
> to provide additional features that are not covered by GIC. The main
> purpose is to provide logic inverter to support low level and falling
> edge trigger
On 22/08/17 03:03, Masahiro Yamada wrote:
> Hi Mark,
>
>
> 2017-08-21 19:25 GMT+09:00 Marc Zyngier :
>
>>> +static struct irq_chip uniphier_aidet_irq_chip = {
>>> + .name = "AIDET",
>>> + .irq_mask = irq_chip_mask_parent,
>>> + .irq_unmask =
On 22/08/17 03:03, Masahiro Yamada wrote:
> Hi Mark,
>
>
> 2017-08-21 19:25 GMT+09:00 Marc Zyngier :
>
>>> +static struct irq_chip uniphier_aidet_irq_chip = {
>>> + .name = "AIDET",
>>> + .irq_mask = irq_chip_mask_parent,
>>> + .irq_unmask = irq_chip_unmask_parent,
>>> +
Hi Mark,
2017-08-21 19:25 GMT+09:00 Marc Zyngier :
>> +static struct irq_chip uniphier_aidet_irq_chip = {
>> + .name = "AIDET",
>> + .irq_mask = irq_chip_mask_parent,
>> + .irq_unmask = irq_chip_unmask_parent,
>> + .irq_eoi = irq_chip_eoi_parent,
>> +
Hi Mark,
2017-08-21 19:25 GMT+09:00 Marc Zyngier :
>> +static struct irq_chip uniphier_aidet_irq_chip = {
>> + .name = "AIDET",
>> + .irq_mask = irq_chip_mask_parent,
>> + .irq_unmask = irq_chip_unmask_parent,
>> + .irq_eoi = irq_chip_eoi_parent,
>> + .irq_set_type =
On 21/08/17 11:54, Masahiro Yamada wrote:
>>> + /* parent is GIC */
>>> + parent_fwspec.fwnode = domain->parent->fwnode;
>>> + parent_fwspec.param_count = 3;
>>> + parent_fwspec.param[0] = 0; /* SPI */
>>> + parent_fwspec.param[1] = hwirq;
>>> +
On 21/08/17 11:54, Masahiro Yamada wrote:
>>> + /* parent is GIC */
>>> + parent_fwspec.fwnode = domain->parent->fwnode;
>>> + parent_fwspec.param_count = 3;
>>> + parent_fwspec.param[0] = 0; /* SPI */
>>> + parent_fwspec.param[1] = hwirq;
>>> +
Hi Mark,
2017-08-21 19:25 GMT+09:00 Marc Zyngier :
> On 21/08/17 11:01, Masahiro Yamada wrote:
>> +static struct irq_chip uniphier_aidet_irq_chip = {
>> + .name = "AIDET",
>> + .irq_mask = irq_chip_mask_parent,
>> + .irq_unmask = irq_chip_unmask_parent,
>> +
Hi Mark,
2017-08-21 19:25 GMT+09:00 Marc Zyngier :
> On 21/08/17 11:01, Masahiro Yamada wrote:
>> +static struct irq_chip uniphier_aidet_irq_chip = {
>> + .name = "AIDET",
>> + .irq_mask = irq_chip_mask_parent,
>> + .irq_unmask = irq_chip_unmask_parent,
>> + .irq_eoi =
On 21/08/17 11:01, Masahiro Yamada wrote:
> UniPhier SoCs contain AIDET (ARM Interrupt Detector). This is intended
> to provide additional features that are not covered by GIC. The main
> purpose is to provide logic inverter to support low level and falling
> edge trigger type for interrupt
On 21/08/17 11:01, Masahiro Yamada wrote:
> UniPhier SoCs contain AIDET (ARM Interrupt Detector). This is intended
> to provide additional features that are not covered by GIC. The main
> purpose is to provide logic inverter to support low level and falling
> edge trigger type for interrupt
UniPhier SoCs contain AIDET (ARM Interrupt Detector). This is intended
to provide additional features that are not covered by GIC. The main
purpose is to provide logic inverter to support low level and falling
edge trigger type for interrupt lines from on-board devices.
Signed-off-by: Masahiro
UniPhier SoCs contain AIDET (ARM Interrupt Detector). This is intended
to provide additional features that are not covered by GIC. The main
purpose is to provide logic inverter to support low level and falling
edge trigger type for interrupt lines from on-board devices.
Signed-off-by: Masahiro
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