Brian Norris writes:
> On Sat, Sep 26, 2015 at 10:19:07PM +0200, Robert Jarzmik wrote:
>> Robert Jarzmik writes:
>>
>> > After the conversion of pxa architecture to common clock framework, the
>> > NAND clock can be disabled on driver exit.
>> >
>> > In this case, it happens that if the driver
Brian Norris writes:
> On Sat, Sep 26, 2015 at 10:19:07PM +0200, Robert Jarzmik wrote:
>> Robert Jarzmik writes:
>>
>> > After the conversion of pxa architecture to common clock framework, the
>> > NAND clock can be disabled on driver exit.
On Sat, Sep 26, 2015 at 10:19:07PM +0200, Robert Jarzmik wrote:
> Robert Jarzmik writes:
>
> > After the conversion of pxa architecture to common clock framework, the
> > NAND clock can be disabled on driver exit.
> >
> > In this case, it happens that if the driver used the NAND and set the
> >
On Sat, Sep 26, 2015 at 10:19:07PM +0200, Robert Jarzmik wrote:
> Robert Jarzmik writes:
>
> > After the conversion of pxa architecture to common clock framework, the
> > NAND clock can be disabled on driver exit.
> >
> > In this case, it happens that if the driver used
Robert Jarzmik writes:
> After the conversion of pxa architecture to common clock framework, the
> NAND clock can be disabled on driver exit.
>
> In this case, it happens that if the driver used the NAND and set the
> DFI arbitration bit, the next access to a static memory controller area,
>
Robert Jarzmik writes:
> After the conversion of pxa architecture to common clock framework, the
> NAND clock can be disabled on driver exit.
>
> In this case, it happens that if the driver used the NAND and set the
> DFI arbitration bit, the next access to a static
After the conversion of pxa architecture to common clock framework, the
NAND clock can be disabled on driver exit.
In this case, it happens that if the driver used the NAND and set the
DFI arbitration bit, the next access to a static memory controller area,
such as an ethernet card, will stall
After the conversion of pxa architecture to common clock framework, the
NAND clock can be disabled on driver exit.
In this case, it happens that if the driver used the NAND and set the
DFI arbitration bit, the next access to a static memory controller area,
such as an ethernet card, will stall
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