On 07/24/2017 08:14 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> dsa_is_cpu_port() checking ds->cpu_port_mask is not available in
> ds->ops->get_tag_protocol
>
> Since commit 14be36c2c96c ("net: dsa: Initialize all CPU and enabled
> ports masks in
On Mon, 24 Jul 2017, Martin Peres wrote:
> On 24/07/17 18:28, Thomas Gleixner wrote:
> > Output of 'cat /proc/interrupts' and a description what kind of 'old' Intel
> > platform that is.
>
> Sorry, I should have repeated the name outside of just the subject of the
> email. It is an Intel Eagle
On Wed, Jul 19, 2017 at 12:16:24PM +0100, Juri Lelli wrote:
> On 19/07/17 13:00, Peter Zijlstra wrote:
> > On Wed, Jul 19, 2017 at 10:20:29AM +0100, Juri Lelli wrote:
> > > On 19/07/17 09:21, Peter Zijlstra wrote:
> > > > On Wed, Jul 05, 2017 at 09:59:05AM +0100, Juri Lelli wrote:
> > > > > @@
On Mon, Jul 17, 2017 at 01:33:30PM +0300, Todor Tomov wrote:
> Add DT binding document for Qualcomm Camera subsystem driver.
>
> CC: Rob Herring
> CC: devicet...@vger.kernel.org
> Signed-off-by: Todor Tomov
> ---
>
On 07/23/2017 07:15 PM, Huang, Ying wrote:
> Hi, Tim,
>
> Tim Chen writes:
>
>> We will only reach the lock initialization code
>> in alloc_swap_slot_cache when the cpu's swap_slots_cache's slots
>> have not been allocated and swap_slots_cache has not been
On 07/20/2017 01:49 AM, Egil Hjelmeland wrote:
> Added read only file /sys/class/net//lan9303/alr_dump,
> that output 168 first ALR entires.
>
> Currently "bridge fdb show" does not include the CPU port, while
> "alr_dump" list all three ports per entry.
Agreed, and this is a limitation we would
On 07/20/2017 03:35 AM, Egil Hjelmeland wrote:
> Saving 2628 bytes.
>
> Signed-off-by: Egil Hjelmeland
Reviewed-by: Florian Fainelli
--
Florian
Hi,
On 07/24/2017 07:47 AM, Egil Hjelmeland wrote:
> This series extends the LAN9303 3 port switch DSA driver. Highlights:
> - Make the MDIO interface work
> - Bridging: Unicast offload
> - Bridging: Added fdb/mdb handling
> - Bridging: STP support
> - Documentation
>
> The last three
Hi Jeffy,
> Currently we are calling usb_submit_urb directly to submit deferred tx
> urbs after unanchor them.
>
> So the usb_giveback_urb_bh would failed to unref it in usb_unanchor_urb
> and cause memory leak:
> unreferenced object 0xffc0ce0fa400 (size 256):
> ...
> backtrace:
>[]
On 07/20/2017 06:57 AM, Egil Hjelmeland wrote:
> Workaround for dsa_switch_mdb_add adding CPU port to group,
> but forgetting to remove it:
>
> Remove port 0 if only port 0 is only port left.
>
> Signed-off-by: Egil Hjelmeland
> ---
> drivers/net/dsa/lan9303-core.c
Changes since v4:
- Added static __vm_insert_mixed() to mm/memory.c that holds the common
code for both vm_insert_mixed() and vm_insert_mixed_mkwrite() so we
don't have duplicate code and we don't have to pass boolean flags
around. (Dan & Jan)
- Added a comment for the PFN sanity
Add missing line breaks between the last two tests.
Signed-off-by: Shuah Khan
---
tools/testing/selftests/breakpoints/breakpoint_test.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/breakpoints/breakpoint_test.c
On Thu, 20 Jul 2017 10:02:33 +0530
Anup Patel wrote:
> Not allowing No-IOMMU mode for devices already having
> iommu_ops on their bus is very conservative.
>
> We now have IOMMU (such as ARM SMMU) which can bypass
> transcations when IOMMU is not configured for a given
On Mon, Jul 24, 2017 at 9:51 PM, Sudeep Holla wrote:
> On 24/07/17 16:41, Jassi Brar wrote:
>> SCMI calls
>> mbox_send_message(struct mbox_chan *chan, struct scmi_xfer *xfer);
>>
>> whereas the API expects
>> mbox_send_message(struct mbox_chan *chan, struct
On 24/07/17 18:16, Alex Williamson wrote:
> On Thu, 20 Jul 2017 12:17:12 +0100
> Robin Murphy wrote:
>
>> On 20/07/17 10:10, Will Deacon wrote:
>>> On Thu, Jul 20, 2017 at 09:32:00AM +0530, Anup Patel wrote:
On Wed, Jul 19, 2017 at 5:23 PM, Will Deacon
Thanks to the nested inlining, all drivers correctly calling
dma_mapping_error() after a mapping a page or single buffer generate two
calls to get_arch_dma_ops() per callsite, which all adds up to a fair
old chunk of useless code, e.g. ~3KB for an arm64 defconfig plus extras:
textdata
Although huge_pte_offset() returns NULL when encountering swap page
table entries, the callers of huge_pte_offset() correctly handling swap
entries.
Add support to the huge_pte_offset() to return the swap entries when it
encounters them during the page table walks.
Also update the function
In the future we would use dynamic allocation for IRQ which brings
non-1:1 mapping for IOAPIC domain. Thus, we need to respect return value
of mp_map_gsi_to_irq() and assign it back to the device structure.
Besides that we need to read GSI from interrupt pin register to avoid
cases when some
Em Sun, Jul 23, 2017 at 08:46:20AM -0700, Andi Kleen escreveu:
> On Sun, Jul 23, 2017 at 07:46:05AM +0900, Namhyung Kim wrote:
> > Hi Arnaldo and Taeung,
> >
> > (+ Andi)
> >
> > On Fri, Jul 21, 2017 at 11:47:48AM -0300, Arnaldo Carvalho de Melo wrote:
> > > Em Thu, Jul 20, 2017 at 06:36:55AM
This improves LCD support for the Droid 4.
Signed-off-by: Sebastian Reichel
---
arch/arm/boot/dts/omap4-droid4-xt894.dts | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts
As the only caller of dma_supported() outside of DMA API internals, the
qtfnmac driver stands out and invites scrutiny. Thankfully, it's not
being used for evil, but it is entirely redundant, since it open-codes a
check that the DMA mask setting functions are going to perform anyway.
In fact, the
Em Mon, Jul 24, 2017 at 11:49:30AM +0800, Jin, Yao escreveu:
> Hi Arnaldo,
>
> Is this patch OK for merging? It's more than 2 months no more comments.
This is not an area I'm completely familiar with, so having other people
vouch for it, reviewing, acking it surely should speed merging, can you
Em Mon, Jul 24, 2017 at 04:16:49PM +0200, Jiri Olsa escreveu:
> On Fri, Jul 21, 2017 at 05:31:59PM -0700, Sukadev Bhattiprolu wrote:
> > Andi Kleen [a...@firstfloor.org] wrote:
> > > From: Andi Kleen
> > >
> > > Today, when a JSON file fails parsing the build continues,
> >
Hi, James,
I appreciate your thorough and expeditious review.
>
>
> From: James Hogan
> Sent: Friday, July 21, 2017 7:45 AM
> To: Aleksandar Markovic
> Cc: linux-m...@linux-mips.org; Aleksandar Markovic; Miodrag Dinic; Goran
> Ferenc; Douglas Leung;
On 23/07/2017 03:05, Wanpeng Li wrote:
> From: Wanpeng Li
>
> When generating #PF VM-exit, check equality:
> (PFEC & PFEC_MASK) == PFEC_MATCH
> If there is equality, the 14 bit of exception bitmap is used to take decision
> about generating #PF VM-exit. If there is
Since the kernel segment registers are not prepared at the
entry of irq-entry code, if a kprobe on such code is
jump-optimized, accessing per-cpu variables may cause
kernel panic.
However, if the kprobe is not optimized, it kicks int3
exception and set segment registers correctly.
This checks
Starting with the A83T SoC, Allwinner introduced a new timing mode for
its MMC clocks. The new mode changes how the MMC controller sample and
output clocks are delayed to match chip and board specifics. There are
two controls for this, one on the CCU side controlling how the clocks
behave, and one
On Mon, Jul 24, 2017 at 05:16:34PM +0800, shuw...@redhat.com wrote:
> When running memory stress tests, kmemleak could be easily disabled in
> function create_object as system is out of memory and kmemleak failed to
> alloc from object_cache. Since there's no way to enable kmemleak after
> it's
On Mon, Jul 24, 2017 at 09:23:32AM +0200, Michal Hocko wrote:
> From: Michal Hocko
>
> David has noticed that the oom killer might kill additional tasks while
> the exiting oom victim hasn't terminated yet because the oom_reaper marks
> the curent victim MMF_OOM_SKIP too early
The MMC2 clock supports a new timing mode. When the new mode is active,
the output clock rate is halved.
This patch sets the feature flag for the new timing mode, and adds
a pre-divider based on the mode bit.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
On Fri, Jul 21, 2017 at 05:31:59PM -0700, Sukadev Bhattiprolu wrote:
> Andi Kleen [a...@firstfloor.org] wrote:
> > From: Andi Kleen
> >
> > Today, when a JSON file fails parsing the build continues,
> > but there are no json files built in, which is difficult to debug
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/asm
head: 9683a64fc3cb67e663859a6bb2e0db5dcee9ed32
commit: 39358a033b2e4432052265c1fa0f36f572d8cfb5 [6/13] objtool, x86: Add
facility for asm code to provide unwind hints
config: x86_64-randconfig-in0-07242041 (attached as
On 24/07/2017 15:57, Wanpeng Li wrote:
>
> if (!((vmcs12->exception_bitmap & (1u << nr)) ||
> -(nr == PF_VECTOR && vcpu->arch.exception.nested_apf)))
> +(nr == PF_VECTOR && (vcpu->arch.exception.nested_apf ||
> +nested_vmx_is_page_fault_vmexit(vmcs12,
>
On Mon 24-07-17 09:57:14, Tejun Heo wrote:
> Hello,
Hi,
and thanks for ths swift answer
> On Mon, Jul 24, 2017 at 03:42:40PM +0200, Michal Hocko wrote:
[...]
> > My understanding of the pcpu allocator is basically close to zero but it
> > seems weird to me that we would need many TB of vmalloc
From: Thierry Reding
In most of the cases, integers in this file can't be negative, so the
type can be more restricted for clarity.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpio-tegra.c | 57 ---
1 file
This adds a common drm helper to detect whether the EDID changed from
the last known cached one. This is useful help detect that a monitor was
changed during a suspend/resume cycle.
When that happens (a monitor is replaced by another one during suspend),
no hotplug event will be triggered so the
This introduces a dedicated work and related helpers to detect whether
a monitor was replaced by another one during suspend. This detection is
based on EDID change detection, using the associated generic drm helper.
This requires storing more information to the intel_connector structure,
such as
On 24/07/17 12:27, Johan Hovold wrote:
On Mon, Jul 24, 2017 at 11:05:49AM +0100, Bryan O'Donoghue wrote:
commit bdfb95c4baab ("staging: greybus: remove timesync protocol support")
commit 1e029b836108 ("staging: greybus: arche: remove timesync remains")
Subtract timesync from greybus/staging
Hi,
On mer., juil. 19 2017, Gregory CLEMENT
wrote:
> The NAND controller used in A7K/A8K is present on the CP110 master
> part. It is compatible with the pxa-nand driver.
>
> Unlike most of the controller on the CP110 this one is only present on
> the
On 7/22/2017 3:33 AM, Dan Carpenter wrote:
My static checker correctly complains that we should have a lower bound
on "node" to prevent an array underflow.
Fixes: 867e359b97c9 ("arch/tile: core support for Tilera 32-bit chips.")
Signed-off-by: Dan Carpenter
Thanks,
On Mon, 2017-07-24 at 17:04 +0200, Borislav Petkov wrote:
> On Mon, Jul 24, 2017 at 02:49:30PM +, Kani, Toshimitsu wrote:
> > We do not tell the error counts to customers.
>
> Please read what I said: do you tell your customers that the error
> counts they're seeing (or are *not* seeing) is
Hi Rafael,
Thanks for your reply.
> On Monday, July 24, 2017 05:43:14 AM Huaisheng HS1 Ye wrote:
> > After commit 82b4e03e01bc (intel_pstate: skip scheduler hook when in
> > "performance" mode) Software P-state control modes couldn't get
> > dynamic value during performance mode,
>
> Please
On 07/06/2017 06:58 PM, Masami Hiramatsu wrote:
> Hello,
>
> Here is v4 of ftracetest improvements, including test
> return code change and immediate logging features.
>
> This version just fixes a bug in [4/5] so that remove
> unneeded backslash.
>
> Thank you,
>
> ---
>
> Masami Hiramatsu
Hi Jonathan,
On 24/07/17 15:50, Jonathan Cameron wrote:
On Mon, 24 Jul 2017 11:29:21 +0100
Suzuki K Poulose wrote:
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU).
The DSU integrates one or more cores with an L3 memory system, control
logic,
On 24/07/17 16:31, Joe Perches wrote:
On Mon, 2017-07-24 at 16:32 +0100, Bryan O'Donoghue wrote:
Ah yes I remember now, those are two separate patches. Anyway my greybus
filter caught your mail which is what prompted me to send this out, I
wasn't sure if you wanted others to clean up their own
Must be set to 1 by user space when STP is used on the lan9303.
If bridging without local STP, leave at 0, so external STP BPDUs
are forwarded.
Hopefully the kernel can be improved so the driver can handle this
without user intervention, and this control can be removed.
Signed-off-by: Egil
Workaround for dsa_switch_mdb_add adding CPU port to group,
but forgetting to remove it:
Remove port 0 if only port 0 is only port left.
Signed-off-by: Egil Hjelmeland
---
drivers/net/dsa/lan9303-core.c | 11 +++
1 file changed, 11 insertions(+)
diff --git
display_config is never set, so we can assume that it is zero
Signed-off-by: Ricardo Ribalda Delgado
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git
Remove unused field display_config
Signed-off-by: Ricardo Ribalda Delgado
---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index
Remove unused field pm_display_cfg
Signed-off-by: Ricardo Ribalda Delgado
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index
pm_display_cfg is never set, so we can assume that it is zero
Signed-off-by: Ricardo Ribalda Delgado
---
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
On 2017-07-22 07:35, Adam Borowski wrote:
On Fri, Jul 21, 2017 at 11:56:21AM -0400, Austin S. Hemmelgarn wrote:
On 2017-07-20 17:27, Nick Terrell wrote:
This patch set adds xxhash, zstd compression, and zstd decompression
modules. It also adds zstd support to BtrFS and SquashFS.
Each patch
Hello,
On Mon, Jul 24, 2017 at 03:42:40PM +0200, Michal Hocko wrote:
> we are seeing a strange pcpu allocation failures on a large ppc machine
> on our older distribution kernel. Please note that I am not yet sure
> this is the case with the current up-to-date kernel and I do not have
> direct
2017-07-24 21:36 GMT+08:00 Paolo Bonzini :
> On 23/07/2017 03:05, Wanpeng Li wrote:
>> From: Wanpeng Li
>>
>> When generating #PF VM-exit, check equality:
>> (PFEC & PFEC_MASK) == PFEC_MATCH
>> If there is equality, the 14 bit of exception bitmap is
Does anyone have ideas how to preserve a /proc/$pid directory after a process
exit? I want to perform some audit on some process A from within
another process B. Process B have the pid of process A but after A
exit, B can no longer retrieve
info from /proc/$pid. I am wondering whether it is
On Mon, 24 Jul 2017, Zdenek Kabelac wrote:
> Hi
>
> I've problem with my USB storage devices: WD Elements 1TB.
> (Bus 004 Device 002: ID 1058:10a8 Western Digital Technologies, Inc. Elements
> Portable (WDBUZG))
>
>
> After kernel >4.9 when disk is attached via cable it has very low speed
From: Thierry Reding
Some kerneldoc has become stale or wasn't quite correct from the outset.
Fix up the most serious issues to silence warnings when building the
documentation.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpiolib.c | 82
On Mon, 24 Jul 2017 09:55:37 +0200
Fabrice Gasnier wrote:
> On 07/23/2017 12:53 PM, Jonathan Cameron wrote:
> > On Tue, 18 Jul 2017 14:35:31 +0200
> > Fabrice Gasnier wrote:
> >
> >> STM32 ADC allows each channel to be sampled with a different
On Mon, Jul 24, 2017 at 02:49:30PM +, Kani, Toshimitsu wrote:
> We do not tell the error counts to customers.
Please read what I said: do you tell your customers that the error
counts they're seeing (or are *not* seeing) is bogus because the BIOS is
hiding them? Not the *actual* numbers!
>
On Fri, Jul 21, 2017 at 09:55:59AM -0400, Joe Lawrence wrote:
> >>> I would do WARN() in klp_shadow_attach() when the variable
> >>> already existed are return NULL. Of course it might be inoncent
> >>> duplication. But it might mean that someone else is using another
> >>> variable of the same
KASAN fills kernel page tables with repeated values to map several
TBs of the virtual memory to the single kasan_zero_page:
kasan_zero_p4d ->
kasan_zero_pud ->
kasan_zero_pmd->
kasan_zero_pte->
kasan_zero_page
Walking the whole KASAN shadow range takes a
lan9303_enable_packet_processing, lan9303_disable_packet_processing()
Pass port number (0,1,2) as parameter instead of port offset.
Simplify accordingly.
Signed-off-by: Egil Hjelmeland
---
drivers/net/dsa/lan9303-core.c | 66
On 24/07/17 18:28, Thomas Gleixner wrote:
On Mon, 24 Jul 2017, Martin Peres wrote:
I am contacting you because your patch "bf22ff45b genirq: Avoid unnecessary
low level irq function calls" broke suspend/resume on an old Intel platform.
This was not caught in linux-next and only got introduced
Fixes after testing on actual HW:
- lan9303_mdio_write()/_read() must multiply register number
by 4 to get offset
- Indirect access (PMI) to phy register only work in I2C mode. In
MDIO mode phy registers must be accessed directly. Introduced
struct lan9303_phy_ops to handle the two modes.
On Mon, Jul 24, 2017 at 3:20 PM, Sudeep Holla wrote:
>
>
> On 08/07/17 06:32, Jassi Brar wrote:
>> Hi Roy, Matt, Nishant, Harb Abdulhamid, Loc,
>>
>> I have a gut feeling you guys were part of the SCMI spec committee. If
>> so, could you please chime in?
>>
>
> I take
For some mysterious reason enable switch fabric port 0 TX fails to
work, when the TX has previous been disabled. Resolved by not
disable/enable switch fabric port 0 at startup. Port 1 and 2 are
still disabled in early init.
Signed-off-by: Egil Hjelmeland
---
Added read only file /sys/class/net//lan9303/alr_dump,
that output 168 first ALR entires.
Currently "bridge fdb show" does not include the CPU port, while
"alr_dump" list all three ports per entry.
Example output:
9c:57:ad:79:d0:84 1 l
01:80:c2:00:00:00 0 s
00:13:cb:0d:01:95 0 s
Added functions for accessing / managing the lan9303 ALR (Address Logic
Resolution).
Implemented DSA methods: set_addr, port_fast_age, port_fdb_prepare,
port_fdb_add, port_fdb_del, port_fdb_dump, port_mdb_prepare,
port_mdb_add and port_mdb_del.
Since the lan9303 do not offer reading specific ALR
On 2017-07-24 10:06 AM, Ricardo Ribalda Delgado wrote:
> Hi Harry
> On Mon, Jul 24, 2017 at 4:01 PM, Harry Wentland
> wrote:
>
>>
>> This is used and needed by the DC display driver. See
>> display/amdgpu_dm/amdgpu_dm_services.c:193 in Alex's amd-staging-4.11 tree:
>>
>>
On Wed, Jul 19, 2017 at 09:28:55PM +0300, Andy Shevchenko wrote:
> There are new types and helpers that are supposed to be used in new code.
>
> As a preparation to get rid of legacy types and API functions do
> the conversion here.
Can you split the uapi changes into a separate patch?
I'd love
> diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
> index 29d6699d5a06..1c68709123aa 100644
> --- a/scripts/mod/file2alias.c
> +++ b/scripts/mod/file2alias.c
> @@ -36,7 +36,7 @@ typedef uint16_t__u16;
> typedef unsigned char__u8;
> typedef struct {
> __u8
On 07/21/2017 07:07 PM, James Bottomley wrote:
> On Fri, 2017-07-21 at 16:17 -0400, Waiman Long wrote:
>> On 07/21/2017 03:30 PM, James Bottomley wrote:
>>> On Fri, 2017-07-21 at 09:43 -0400, Waiman Long wrote:
Having a limit for the number of negative dentries does have an
undesirable
STM32 ADC allows each channel to be sampled with a different sampling
time. This series fixes common clock rate and adds optional device
tree property, so minimum sampling time can be tuned. This is done via
device tree as it's tightly coupled with hardware (analog source).
---
Changes in v2:
-
STM32 ADC allows each channel to be sampled with a different sampling
time. There's an application note that deals with this: 'How to get
the best ADC accuracy in STM32...' It basically depends on analog input
signal electrical properties (depends on board).
Add optional
Hi Namhyung,
On Sun, 2017-07-23 at 21:00 +0900, Namhyung Kim wrote:
> Hi Tom,
>
> On Mon, Jun 26, 2017 at 05:49:23PM -0500, Tom Zanussi wrote:
> > Synthetic events are user-defined events generated from hist trigger
> > variables saved from one or more other events.
> >
> > To define a
On Mon, Jul 24, 2017 at 08:09:15AM -0700, Andrey Smirnov wrote:
> Cc: cphe...@gmail.com
> Cc: Lucas Stach
> Cc: Nikita Yushchenko
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc:
Hello,
On (07/24/17 14:46), Sebastian Ott wrote:
> [ 347.644660] ==
> [ 347.644660] WARNING: possible circular locking dependency detected
> [ 347.644661] 4.13.0-rc2 #146 Not tainted
> [ 347.644661]
On Fri, 21 Jul, at 09:19:56PM, Baoquan He wrote:
>
> There are places where the efi map is getting and used like this. E.g
> in efi_high_alloc() of drivers/firmware/efi/libstub/efi-stub-helper.c.
> EFI developers worry the size of efi_memory_desc_t could not be the same
> as e->efi_memdesc_size?
>
Hi Tejun,
we are seeing a strange pcpu allocation failures on a large ppc machine
on our older distribution kernel. Please note that I am not yet sure
this is the case with the current up-to-date kernel and I do not have
direct access to the machine but it seems there were not many changes in
the
On Mon, Jul 24, 2017 at 04:31:22PM +0530, Viresh Kumar wrote:
> On 21-07-17, 15:03, Peter Zijlstra wrote:
> > On Thu, Jul 13, 2017 at 12:14:37PM +0530, Viresh Kumar wrote:
> > > diff --git a/kernel/sched/cpufreq_schedutil.c
> > > b/kernel/sched/cpufreq_schedutil.c
> > > index
On the SoCs that introduced the new timing mode for MMC controllers,
both the old (where the clock delays are set in the CCU) and new
(where the clock delays are set in the MMC controller) timing modes
are available, and we have to support them both. However there are
two bits that control which
On Sat, Jul 15, 2017 at 10:53:27AM +0200, Michal Kubecek wrote:
>On Sat, Jul 15, 2017 at 01:26:27AM +, Levin, Alexander (Sasha Levin) wrote:
>> From: Michal Kubeček
>>
>> [ Upstream commit a5cb659bbc1c8644efa0c3138a757a1e432a4880 ]
>>
>> Our customer encountered stuck NFS
Add a driver for RAVE Supervisory Processor, an MCU implementing
varoius bits of housekeeping functionality (watchdoging, backlight
control, LED control, etc) on RAVE family of products by Zodiac
Inflight Innovations.
This driver implementes core MFD/serdev device as well as
communication
Cc: cphe...@gmail.com
Cc: Lucas Stach
Cc: Nikita Yushchenko
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Acked-for-MFD-by: Lee Jones
Signed-off-by:
Hi everyone,
This patch series is v3 of the driver for supervisory processor found
on RAVE series of devices from ZII. Supervisory processor is a PIC
microcontroller connected to various electrical subsystems on RAVE
devices whose firmware implements protocol to command/qery them.
Changes since
On Mon, 2017-07-24 at 16:32 +0100, Bryan O'Donoghue wrote:
> Ah yes I remember now, those are two separate patches. Anyway my greybus
> filter caught your mail which is what prompted me to send this out, I
> wasn't sure if you wanted others to clean up their own crap, or if you
> wanted to
From: Sedat Dilek
The old example to describe ccflags-y usage is no more valid.
Signed-off-by: Sedat Dilek
---
Documentation/kbuild/makefiles.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
On Mon, 2017-07-24 at 17:16 +0200, Peter Zijlstra wrote:
> Here are a few patches that should improve things lib/int_sqrt.
Thanks Peter.
Allowing per-port access to Switch Engine Broadcast Throttling Register
Also added lan9303_write_switch_reg_mask()
Signed-off-by: Egil Hjelmeland
---
drivers/net/dsa/lan9303-core.c | 83 ++
1 file changed, 83 insertions(+)
Allowing dsa drivers to attach sysfs nodes.
Signed-off-by: Egil Hjelmeland
---
include/net/dsa.h | 1 +
net/dsa/slave.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 88da272d20d0..a71c0a2401ee 100644
Em Mon, 24 Jul 2017 17:37:16 +0200
Borislav Petkov escreveu:
> > Customers do not see error counts. I do not think it's bogus.
> > I am just trying to enable OS error reporting with ghes_edac.
>
> I know, you don't have to state the obvious constantly.
The problem I see is
On Fri, Jul 21, 2017 at 11:26:59AM +0800, Guochun Mao wrote:
> Add "mediatek,mt2712-nor" and "mediatek,mt7622-nor"
> for nor flash node's compatible.
The subject could be improved because it is exactly the same as the last
patch adding the 2701 and 7623. Also, use "dt-bindings: mtd: ..." for
On 24/07/17 16:41, Jassi Brar wrote:
> On Mon, Jul 24, 2017 at 3:20 PM, Sudeep Holla wrote:
>>
>>
>> On 08/07/17 06:32, Jassi Brar wrote:
>>> Hi Roy, Matt, Nishant, Harb Abdulhamid, Loc,
>>>
>>> I have a gut feeling you guys were part of the SCMI spec committee. If
>>> so,
On Wed, Jul 19, 2017 at 2:58 AM, Xin Long wrote:
> On Wed, Jul 19, 2017 at 3:02 AM, Alexander Potapenko
> wrote:
>> On Tue, Jul 18, 2017 at 4:55 PM, Alexander Potapenko
>> wrote:
>>> KMSAN reported use of uninitialized
Hello,
I am contacting you because your patch "bf22ff45b genirq: Avoid
unnecessary low level irq function calls" broke suspend/resume on an old
Intel platform.
This was not caught in linux-next and only got introduced in linux 4.13-rc1.
Here is the current place where the bug has been
Hi everyone,
This is v3 of my MMC controller support series.
Changes since v2:
- Really dropped CCU_FEATURE_MMC_ALWAYS_NEW
- Simplified SUNXI_CCU_MP_MMC_WITH_MUX_GATE macro
- Added Maxime's ack for mmc patches
Changes since v1:
- Fix patches already applied have been dropped
- V2
All of our MMC clocks are of the MP clock type. A few MMC clocks on some
SoCs, such as MMC2 on the A83T, support new/old timing mode switching.
>From a clock rate point of view, when the new timing mode is active. the
output clock rate is halved.
This patch adds a special wrapper class of
On Mon, 24 Jul 2017, Johan Hovold wrote:
> Make sure that the controller is runtime resumed when system suspending
> to avoid an external abort when accessing the interrupt registers:
>
> Unhandled fault: external abort on non-linefetch (0x1008) at 0xd025840a
> ...
> []
2017-07-24 22:44 GMT+08:00 Paolo Bonzini :
> On 24/07/2017 16:44, Wanpeng Li wrote:
>>> Wanpeng, can you test this on the testcases you had for commit
>>> d4912215d103 ("KVM: nVMX: Fix exception injection", 2017-06-05)?
>> Yeah, I will try it tomorrow. :)
>>
On 24/07/2017 10:57, Wanpeng Li wrote:
> From: Wanpeng Li
>
> Preemption can occur in the preemption timer expiration handler:
>
> CPU0CPU1
>
> preemption timer vmexit
> handle_preemption_timer(vCPU0)
> kvm_lapic_expired_hv_timer
>
1 - 100 of 2050 matches
Mail list logo