[PATCH 2/2] drm/bridge: Add IT6151 bridge driver

This patch adds a drm_bridge driver for the IT6151 MIPI to eDP bridge chip. Signed-off-by: CK Hu ck...@mediatek.com Signed-off-by: Jitao Shi jitao@mediatek.com --- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/it6151.c | 601

[PATCH 2/2] drm/bridge: Add IT6151 bridge driver

This patch adds a drm_bridge driver for the IT6151 MIPI to eDP bridge chip. Signed-off-by: CK Hu ck...@mediatek.com Signed-off-by: Jitao Shi jitao@mediatek.com --- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/it6151.c | 601

[PATCH 1/2] dt-bindings: drm/bridge: Add IT6151 bridge chip driver bindings.

Add devicetree bindings for IT6151 MIPI to eDP bridge chip driver. --- Documentation/devicetree/bindings/drm/bridge/it6151.txt | 15 +++ 1 file changed, 15 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/bridge/it6151.txt diff --git

[PATCH 1/2] dt-bindings: drm/bridge: Add IT6151 bridge chip driver bindings.

Add devicetree bindings for IT6151 MIPI to eDP bridge chip driver. Signed-off-by: CK Hu ck...@mediatek.com Signed-off-by: Jitao Shi jitao@mediatek.com --- Documentation/devicetree/bindings/drm/bridge/it6151.txt | 15 +++ 1 file changed, 15 insertions(+) create mode 100644

[RFC][PATCH 1/2] dt-bindings: drm/mediatek: Add Mediatek DRM dts binding

This patch includes 1. Mediatek DRM Device binding 2. Mediatek DSI Device binding 3. Mediatek CRTC Main Device binding 4. Mediatek DDP Device binding Signed-off-by: CK Hu ck...@mediatek.com --- .../bindings/drm/mediatek/mediatek,crtc-main.txt | 38 ++ .../bindings/drm

[RFC][PATCH 2/2] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.

This patch is a DRM Driver for Mediatek SoC MT8173. Now support one crtc with MIPI DSI interface. We used GEM framework for buffer management and use iommu for physically non-continuous memory. Signed-off-by: CK Hu ck...@mediatek.com --- drivers/gpu/drm/Kconfig |2

[RFC][PATCH 0/2] MT8173 DRM support

-mediatek/2015-March/58.html 2. add IOMMU dma_ops cherry picked from git://linux-arm.org/linux-rm iommu/dma commit d76a1911b02185bdc5f8b5525f9228cf266725c5 CK Hu (2): dt-bindings: drm/mediatek: Add Mediatek DRM dts binding drm/mediatek: Add DRM Driver for Mediatek SoC

[RFC 1/2] Dcumentation: bridge: Add documentation for ps8640 DT properties

From: Jitao Shi Add documentation for DT properties supported by ps8640 DSI-eDP converter. Signed-off-by: Jitao Shi --- .../devicetree/bindings/video/bridge/ps8640.txt| 48 1 file changed, 48 insertions(+) create mode

[RFC 2/2] drm/bridge: Add I2C based driver for ps8640 bridge

return 0; +} + +static int ps8640_remove(struct i2c_client *client) +{ + struct ps8640 *ps_bridge = i2c_get_clientdata(client); + + drm_bridge_remove(_bridge->bridge); + + return 0; +} + +static const struct i2c_device_id ps8640_i2c_table[] = { + {"parade,ps86

Re: [RFC v3 4/5] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: Some comments inline. On Thu, 2016-06-09 at 00:03 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c |

Re: [RFC v3 3/5] drm/mediatek: add shadow register support

Hi, YT: One comment inline. On Thu, 2016-06-09 at 00:03 +0800, YT Shen wrote: > We need to acquire mutex before using the resources, > and need to release it after finished. > So we don't need to write registers in the blanking period. > > Signed-off-by: YT Shen > --- >

Re: [PATCH v8 2/3] CMDQ: Mediatek CMDQ driver

he vblank. It controls > Global Command Engine (GCE) hardware to achieve this requirement. > Currently, CMDQ only supports display related hardwares, but we expect > it can be extended to other hardwares for future requirements. > > Signed-off-by: HS Liao <hs.l...@mediatek.com&

Re: [PATCH v7 2/4] CMDQ: Mediatek CMDQ driver

Hi, HS: Replay inline. On Tue, 2016-05-24 at 20:27 +0800, Horng-Shyang Liao wrote: > Hi CK, > > Reply in line. > > On Tue, 2016-05-24 at 11:05 +0800, CK Hu wrote: > > Hi, HS: > > > > Some comments below. > > > ... > > > +static void

Re: [PATCH v8 2/3] CMDQ: Mediatek CMDQ driver

obal Command Engine (GCE) hardware to achieve this requirement. > Currently, CMDQ only supports display related hardwares, but we expect > it can be extended to other hardwares for future requirements. > > Signed-off-by: HS Liao <hs.l...@mediatek.com> > Signed-off-by: CK Hu <

Re: [PATCH v8 2/3] CMDQ: Mediatek CMDQ driver

On Thu, 2016-06-23 at 15:54 +0800, Horng-Shyang Liao wrote: > Hi CK, > > On Thu, 2016-06-23 at 14:03 +0800, CK Hu wrote: > > Hi, HS: > > > > On Mon, 2016-05-30 at 11:19 +0800, HS Liao wrote: > > [...] > > > > > + > > >

Re: [PATCH v8 2/3] CMDQ: Mediatek CMDQ driver

he vblank. It controls > Global Command Engine (GCE) hardware to achieve this requirement. > Currently, CMDQ only supports display related hardwares, but we expect > it can be extended to other hardwares for future requirements. > > Signed-off-by: HS Liao <hs.l...@mediatek.com&

Re: [PATCH v8 2/3] CMDQ: Mediatek CMDQ driver

On Mon, 2016-06-20 at 19:22 +0800, Horng-Shyang Liao wrote: > On Mon, 2016-06-20 at 18:41 +0800, CK Hu wrote: > > Hi, HS: > > > > One comment inline. > > > > On Mon, 2016-05-30 at 11:19 +0800, HS Liao wrote: > > > This patch is first version of Mediatek

Re: [PATCH v8 2/3] CMDQ: Mediatek CMDQ driver

On Fri, 2016-06-24 at 19:39 +0800, Horng-Shyang Liao wrote: > On Tue, 2016-06-21 at 15:46 +0800, Horng-Shyang Liao wrote: > > On Tue, 2016-06-21 at 10:03 +0800, CK Hu wrote: > > > On Mon, 2016-06-20 at 19:22 +0800, Horng-Shyang Liao wrote: > > > > On Mon, 2016-06-

Re: [PATCH v7 2/4] CMDQ: Mediatek CMDQ driver

he vblank. It controls > Global Command Engine (GCE) hardware to achieve this requirement. > Currently, CMDQ only supports display related hardwares, but we expect > it can be extended to other hardwares for future requirements. > > Signed-off-by: HS Liao <hs.l...@mediatek.com&

Re: [RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701

Hi, YT: Some comments below. On Fri, 2016-05-20 at 23:05 +0800, yt.s...@mediatek.com wrote: > From: YT Shen > > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen >

Re: [RFC v2 3/5] drm/mediatek: add *driver_data for different hardware settings

Hi, YT: One comment below. On Fri, 2016-05-20 at 23:05 +0800, yt.s...@mediatek.com wrote: > From: YT Shen > > There are some hardware settings changed, between MT8173 & MT2701: > DISP_OVL address offset changed, color format definition changed. > DISP_RDMA fifo size

Re: [PATCH v7 4/4] CMDQ: suspend/resume protection

On Mon, 2016-05-23 at 20:23 +0800, HS Liao wrote: > Add suspend/resume protection mechanism to prevent active task(s) in > suspend. > > Signed-off-by: HS Liao > --- > drivers/soc/mediatek/mtk-cmdq.c | 174 > ++-- > 1 file changed, 166

Re: [RFC 2/3] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: On Thu, 2016-05-12 at 19:49 +0800, yt.s...@mediatek.com wrote: > From: YT Shen > > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701, and we have shadow > register support here. > > Signed-off-by: YT Shen

Re: [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support

Hi, Bibby: On Wed, 2016-07-27 at 16:25 +0800, Bibby Hsieh wrote: > If MT8173 can support HDMI 4K resoultion, the > VENCPLL should be configured to 800MHZ. > We didn't set VENCPLL directly, we set the > mm_sel to 400MHz statically in the board device tree. You may rewrite the description as

Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when resolution is 4K

Hi, Bibby: On Mon, 2016-07-25 at 14:24 +0800, Bibby Hsieh wrote: > Hi, CK, > > Thanks for your comments. > > On Wed, 2016-07-20 at 15:57 +0800, CK Hu wrote: > > Hi, Bibby: > > > > Some comments inline. > > > > On Wed, 2016-07-20 at 12:03 +080

Re: [PATCH v4 4/8] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: On Thu, 2016-07-28 at 15:17 +0800, YT Shen wrote: > Hi Philipp, CK, > > On Thu, 2016-07-28 at 10:07 +0800, CK Hu wrote: > > Hi, YT: > > > > On Wed, 2016-07-27 at 12:03 +0200, Philipp Zabel wrote: > > > Am Dienstag, den 26.07.2016, 18:42

Re: [PATCH 2/7] drm/mediatek: plane: Remove plane zpos/index

Hi, Bibby: On Fri, 2016-07-29 at 17:04 +0800, Bibby Hsieh wrote: > From: Daniel Kurtz > > It is not actually useful to a mtk plane to know its zpos/index, so just > remove this field. > > This let's us completely remove struct mtk_drm_plane in a follow up patch. 'let's

Re: [PATCH v4 4/8] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: On Wed, 2016-07-27 at 12:03 +0200, Philipp Zabel wrote: > Am Dienstag, den 26.07.2016, 18:42 +0800 schrieb YT Shen: > > Hi CK, > > > > On Wed, 2016-07-20 at 14:53 +0800, CK Hu wrote: > > > Hi, YT: > > > > > > Some comments inline. > &g

Re: [PATCH v6 07/10] drm/mediatek: add dsi transfer function

Hi, YT: On Wed, 2016-08-10 at 15:24 +0800, YT Shen wrote: > Hi CK, > > On Fri, 2016-08-05 at 18:08 +0800, CK Hu wrote: > > Hi, YT: > > > > On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote: > > > From: shaoming chen <shaoming.c...@mediatek.com>

Re: [PATCH v3 2/2] drm/mediatek: set mt8173 dithering function

Hi, Bibby: On Thu, 2016-07-21 at 11:21 +0800, Bibby Hsieh wrote: > Hi, CK > > I'm appreciate your comments. > > [snip...] > > > > > > @@ -469,7 +484,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct > > > mtk_ddp_comp *ovl) > > > if (state->pending_config) { > > >

Re: [PATCH v3 2/2] drm/mediatek: set mt8173 dithering function

Hi, Bibby: Some comments inline. On Thu, 2016-07-07 at 15:37 +0800, Bibby Hsieh wrote: > Some panels only accept bpc (bit per color) 6-bit. > But, the default bpc in mt8173 display data path is 8-bit. > If we didn't enable dithering function to convert bpc, > display cannot show the smooth

Re: [PATCH v4 5/8] drm/mediatek: add dsi interrupt control

Hi, YT: Some comments inline. On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote: > From: shaoming chen > > add dsi interrupt control > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 130 >

Re: [PATCH 2/4] drm/mediatek: enhance the HDMI driving current

Hi, Bibby: One comment inline. On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote: > From: Junzhi Zhao > > In order to improve 4K resolution performance, > we have to enhance the HDMI driving currend > when clock rate is greater than 165MHz. > > Signed-off-by:

Re: [PATCH v4 4/8] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: Some comments inline. On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c |

Re: [PATCH v4 7/8] drm/mediatek: add mipi panel support

Hi, YT: Some comments inline. On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote: > From: shaoming chen > > add dsi and mipi tx driver for mipi panel support > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c

Re: [PATCH 3/4] drm/mediatek: fix the wrong pixel clock when resolution is 4K

Hi, Bibby: Some comments inline. On Wed, 2016-07-20 at 12:03 +0800, Bibby Hsieh wrote: > From: Junzhi Zhao > > Pixel clock should be 297MHz when resolution is 4K. > > Signed-off-by: Junzhi Zhao > Signed-off-by: Bibby Hsieh

Re: [PATCH v4 6/8] drm/mediatek: add dsi transfer function

Hi, YT: Some comments inline. On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote: > From: shaoming chen > > add dsi read/write commands for transfer function > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c |

Re: [PATCH v3 1/2] drm/mediatek: Add gamma correction

Hi, Bibby: Some comments inline. On Thu, 2016-07-07 at 15:37 +0800, Bibby Hsieh wrote: > Apply gamma function to correct brightness values. > It applies arbitrary mapping curve to compensate the > incorrect transfer function of the panel. > > Signed-off-by: Bibby Hsieh

Re: [PATCH v4 3/8] drm/mediatek: add shadow register support

Hi, YT: One comment inline. On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote: > We need to acquire mutex before using the resources, > and need to release it after finished. > So we don't need to write registers in the blanking period. > > Signed-off-by: YT Shen > --- >

Re: [PATCH v4 4/8] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: One comment inline. On Fri, 2016-07-15 at 18:07 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6

[PATCH] drm: mediatek: add Maintainers entry for Mediatek DRM drivers

Add CK Hu and Philipp Zabel as maintainers for Mediatek DRM drivers. Signed-off-by: CK Hu <ck...@mediatek.com> --- MAINTAINERS |8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7304d2e..2a04cdc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -

Re: [PATCH v6 09/10] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6 ++ >

Re: [PATCH v6 10/10] arm: dts: mt2701: Add display subsystem related nodes for MT2701

Hi, YT: On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote: > This patch adds the device nodes for the DISP function blocks for MT2701 > > Signed-off-by: YT Shen > --- > arch/arm/boot/dts/mt2701.dtsi | 86 > + > 1 file changed, 86

Re: [PATCH v6 06/10] drm/mediatek: add dsi interrupt control

Hi, YT: On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote: > From: shaoming chen > > add dsi interrupt control > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 76 > >

Re: [PATCH v6 07/10] drm/mediatek: add dsi transfer function

Hi, YT: On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote: > From: shaoming chen > > add dsi read/write commands for transfer function > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 261 >

Re: [PATCH v5 06/10] drm/mediatek: add dsi interrupt control

Hi, YT: On Thu, 2016-07-28 at 17:28 +0800, YT Shen wrote: > From: shaoming chen > > add dsi interrupt control > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 92 > >

Re: [PATCH v5 07/10] drm/mediatek: add dsi transfer function

Hi, YT: On Thu, 2016-07-28 at 17:28 +0800, YT Shen wrote: > From: shaoming chen > > add dsi read/write commands for transfer function > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 286 >

Re: [GIT PULL] drm/mediatek: MT8173 gamma & dither support

Daniel Vetter's comments, > > there had been no further comments and I sent the pull request as the > > other sub-sys. > > > > I'm sorry for my mistake, I will re-arrange the tree for upstream. > > Next time, I will check with maintainer by email first, and sent the > > pull request. > > > It might be a bit hard to find out who's the maintainer considering > MAINTAINERS has no entry for this driver. > > Looking at how things are going Philipp Zabel will be the more likely > person for the task, yet I would be nice if someone from the Mediatek > squad is helping him out - CK Hu perhaps ? > > Regards, > Emil I'm willing to be one of Mediatek DRM driver maintainer. I wish this would make things easier. Regards, CK

Re: [PATCH v3] drm/mediatek: Support UYVY and YUYV format for overlay

Hi, Bibby: On Tue, 2017-01-24 at 12:40 +0800, Bibby Hsieh wrote: > MT8173 overlay can support UYVY and YUYV format, > we add the format in DRM driver. > > Signed-off-by: Bibby Hsieh <bibby.hs...@mediatek.com> > Reviewed-by: Daniel Kurtz <djku...@chromium.org> Acked-by

Re: [PATCH v12 11/12] drm/mediatek: update DSI sub driver flow for sending commands to panel

itialize DSI first so that we can send commands to panel. > > Signed-off-by: shaoming chen <shaoming.c...@mediatek.com> > Signed-off-by: YT Shen <yt.s...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 266 > +++

Re: [PATCH] drm/mediatek: hdmi: Filter interlaced resolutions

Hsieh <bibby.hs...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c > b/drivers/gpu/drm/mediatek/mtk_hdmi.c > index 0e8c4d9.

Re: [PATCH v11 08/12] drm/mediatek: add dsi interrupt control

Hi, YT: On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > From: shaoming chen <shaoming.c...@mediatek.com> > > add dsi interrupt control > > Signed-off-by: shaoming chen <shaoming.c...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> > --- >

Re: [PATCH v11 09/12] drm/mediatek: add dsi transfer function

Hi, YT: On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > From: shaoming chen <shaoming.c...@mediatek.com> > > add dsi read/write commands for transfer function > > Signed-off-by: shaoming chen <shaoming.c...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.

Re: [PATCH v11 07/12] drm/mediatek: cleaning up and refine

Hi, YT: On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > cleaning up unused define and refine function name and variable > > Signed-off-by: shaoming chen <shaoming.c...@mediatek.com> > Signed-off-by: YT Shen <yt.s...@mediatek.com> Acked-by: CK Hu <ck...@mediatek

Re: [PATCH v11 10/12] drm/mediatek: add non-continuous clock mode and EOT packet control

; > Signed-off-by: shaoming chen <shaoming.c...@mediatek.com> > Signed-off-by: YT Shen <yt.s...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gp

Re: [PATCH v11 12/12] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen <yt.s...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> > ---

Re: [PATCH v11 11/12] drm/mediatek: update DSI sub driver flow for sending commands to panel

Hi, YT: one comment inline. On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > This patch update enable/disable flow of DSI module. > Original flow works on there is a bridge chip: DSI -> bridge -> panel. > In this case: DSI -> panel, the DSI sub driver flow should be updated. > We need to

Re: [PATCH v11 05/12] drm/mediatek: add BLS component

Hi, YT: On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > Add BLS component for PWM + GAMMA function > > Signed-off-by: YT Shen <yt.s...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 5 -

Re: [PATCH v11 06/12] drm/mediatek: update display module connections

Hi, YT: On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > update connections for OVL, RDMA, BLS, DSI > > Signed-off-by: YT Shen <yt.s...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25

Re: [PATCH v11 04/12] drm/mediatek: add shadow register support

Hi, YT: On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > We need to acquire mutex before using the resources, > and need to release it after finished. > So we don't need to write registers in the blanking period. > > Signed-off-by: YT Shen <yt.s...@mediatek.com>

Re: [PATCH v11 03/12] drm/mediatek: add *driver_data for different hardware settings

changed. > And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod. > > Signed-off-by: YT Shen <yt.s...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 - > drivers/gpu/drm/med

Re: [PATCH v7 2/9] drm/mediatek: add *driver_data for different hardware settings

Hi, YT: On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > There are some hardware settings changed, between MT8173 & MT2701: > DISP_OVL address offset changed, color format definition changed. > DISP_RDMA fifo size changed. > DISP_COLOR offset changed. > MIPI_TX pll setting changed. > And add

Re: [PATCH v7 4/9] drm/mediatek: update display module connections

Hi, YT: On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > update connections for OVL, RDMA, BLS, DSI > > Signed-off-by: YT Shen > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 + > 1 file changed, 25 insertions(+) > [snip...] > @@ -111,6

Re: [PATCH v7 7/9] drm/mediatek: add dsi transfer function

Hi, YT: On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > From: shaoming chen > > add dsi read/write commands for transfer function > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 188 >

Re: [PATCH v7 6/9] drm/mediatek: add dsi interrupt control

Hi, YT: On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > From: shaoming chen > > add dsi interrupt control > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 76 > ++ >

Re: [PATCH v7 8/9] drm/mediatek: update DSI sub driver flow

Hi, YT: On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > This patch update enable/disable flow of DSI module and MIPI TX module > > Signed-off-by: shaoming chen > Signed-off-by: YT Shen > --- I think the description is too simple. Please

Re: [PATCH v4 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K

Hi, Bibby: Sorry for the late reply. On Wed, 2016-08-17 at 14:58 +0800, Bibby Hsieh wrote: > From: Junzhi Zhao > > Pixel clock should be 297MHz when resolution is 4K. > >From the code you modified, I think title should be: "Enlarge pll_rate range from (, ) to (, )"

Re: [PATCH v8 8/9] drm/mediatek: update DSI sub driver flow

Hi, YT: On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote: > This patch update enable/disable flow of DSI module and MIPI TX module. > Original flow works on there is a bridge chip: DSI -> bridge -> panel. > In this case: DSI -> panel, the DSI sub driver flow should be updated. > We need to

Re: [PATCH v7 7/9] drm/mediatek: add dsi transfer function

Hi, YT: On Wed, 2016-09-14 at 14:19 +0800, YT Shen wrote: > Hi CK, > > On Tue, 2016-09-13 at 17:25 +0800, CK Hu wrote: > > Hi, YT: > > > > On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote: > > > Hi CK, > > > > > > On Wed,

Re: [PATCH v7 7/9] drm/mediatek: add dsi transfer function

Hi, YT: On Wed, 2016-09-14 at 15:22 +0800, YT Shen wrote: > Hi CK, > > On Wed, 2016-09-14 at 14:39 +0800, CK Hu wrote: > > Hi, YT: > > > > On Wed, 2016-09-14 at 14:19 +0800, YT Shen wrote: > > > Hi CK, > > > > > > On Tue,

Re: [PATCH v8 4/9] drm/mediatek: update display module connections

Hi, YT: On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote: > update connections for OVL, RDMA, BLS, DSI > > Signed-off-by: YT Shen > --- [snip...] > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index

Re: [PATCH v8 6/9] drm/mediatek: add dsi interrupt control

Hi, YT: On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote: > From: shaoming chen > > add dsi interrupt control > > Signed-off-by: shaoming chen > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 78 > ++ >

Re: [PATCH v7 8/9] drm/mediatek: update DSI sub driver flow

Hi, YT: On Mon, 2016-09-12 at 18:15 +0800, YT Shen wrote: > Hi CK, > > On Wed, 2016-09-07 at 12:58 +0800, CK Hu wrote: > > Hi, YT: > > > > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > > > This patch update enable/disable flow of DSI module and MI

Re: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote: > Hi CK, > > On Wed, 2016-09-07 at 13:37 +0800, CK Hu wrote: > > Hi, YT: > > > > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > > > This patch add support for the Mediatek MT2701 DISP subsystem

Re: [PATCH v7 7/9] drm/mediatek: add dsi transfer function

Hi, YT: On Mon, 2016-09-12 at 18:16 +0800, YT Shen wrote: > Hi CK, > > On Wed, 2016-09-07 at 10:33 +0800, CK Hu wrote: > > Hi, YT: > > > > On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > > > From: shaoming chen <shaoming.c...@mediatek.com>

Re: [PATCH v14 2/4] CMDQ: Mediatek CMDQ driver

mmand Engine (GCE) hardware to achieve this requirement. > Currently, CMDQ only supports display related hardwares, but we expect > it can be extended to other hardwares for future requirements. > > Signed-off-by: HS Liao <hs.l...@mediatek.com> > Signed-off-by: CK Hu

Re: [PATCH v14 2/4] CMDQ: Mediatek CMDQ driver

Hi, HS: One comment inline On Fri, 2016-09-30 at 16:56 +0800, Horng-Shyang Liao wrote: > Hi CK, > > Please see my inline reply. > > On Fri, 2016-09-30 at 11:06 +0800, CK Hu wrote: > > Hi, HS: > > > > On Mon, 2016-09-05 at 09:44 +0800, HS Liao wrote:

Re: [PATCH v8 9/9] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: On Mon, 2016-09-12 at 20:01 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++ >

Re: [PATCH v7 9/9] drm/mediatek: add support for Mediatek SoC MT2701

Hi, YT: On Fri, 2016-09-02 at 19:24 +0800, YT Shen wrote: > This patch add support for the Mediatek MT2701 DISP subsystem. > There is only one OVL engine in MT2701. > > Signed-off-by: YT Shen [snip...] > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c >

Re: [PATCH 2/2] drm/mediatek: clear IRQ status before enable OVL interrupt

Acked-by: CK Hu <ck...@mediatek.com> On Thu, 2016-09-29 at 11:29 +0800, Bibby Hsieh wrote: > To make sure that the first vblank IRQ after enabling > vblank isn't too short or immediate, we have to clear > the IRQ status before enable OVL interrupt. > > Signed-off-by:

Re: [PATCH 1/2] drm/mediatek: set vblank_disable_allowed to true

Acked-by: CK Hu <ck...@mediatek.com> On Thu, 2016-09-29 at 11:29 +0800, Bibby Hsieh wrote: > MTK DRM driver didn't set the vblank_disable_allowed to > true, it cause that the irq_handler is called every > 16.6 ms (every vblank) when the display didn't be updated. > > Signe

Re: drm/mediatek: fixed the calc method of data rate per lane

Hi, Jitao: Sorry for late reply. Some comments inline. On Fri, 2016-08-26 at 14:10 +0800, Jitao Shi wrote: > Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx, > Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this > signal will cause h-time larger

Re: [PATCH] drm/mediatek: fix a typo

Acked-by: CK Hu <ck...@mediatek.com> On Thu, 2016-09-29 at 11:22 +0800, Bibby Hsieh wrote: > Fix the typo: OD_RELAYMODE->OD_CFG > > Signed-off-by: Bibby Hsieh <bibby.hs...@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |2 +- > 1 file ch

Re: [PATCH v5 0/3] MT8173 HDMI 4K support

e the HDMI driving current to improve performance. > 3) Make sure that pixel clock is 297MHz when resolution is 4K. > For this series, Acked-by: CK Hu <ck...@mediatek.com> > Changes since v4: > - Update commit message and patch title. > > Changes since v3: > - Rebase to

Re: [PATCH v2] drm/mediatek: fix a typo

Acked-by: CK Hu <ck...@mediatek.com> On Tue, 2016-10-18 at 16:23 +0800, Bibby Hsieh wrote: > If we want to set the hardware OD to relay mode, > we have to set OD_CFG register rather than > OD_RELAYMODE; otherwise, the system will access > the wrong a

Re: [PATCH v9 00/10] MT2701 DRM support

DSI > RDMA -> DPI > And we have shadow register support in MT2701. > > We remove dts patch from the patch series, which depends on MT2701 CCF and > scpsys. For this series, it looks good to me. Acked-by: CK Hu <ck...@mediatek.com> > > Changes since v8: > - enab

Re: [PATCH v5] drm/mediatek: fixed the calc method of data rate per lane

Hi, Jitao: On Wed, 2016-11-16 at 11:20 +0800, Jitao Shi wrote: > Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. > Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP > mode, those signals will cause h-time larger than normal and reduce FPS. > So need to

Re: DRM: urgent v4.9-rc6 build regression: master build: 2 failures 1 warnings (v4.9-rc5-213-g961b708)

Hi, Arnd: I've made a mistake that I've tried to build these patches on v4.9-rc1, but I does not set CONFIG_DRM_MEDIATEK=y, therefore I didn't find out these build fails. Now I fix the config problem, and I think I should build these patches on latest kernel version even though patch's owner test

Re: [PATCH v5] drm/mediatek: fixed the calc method of data rate per lane

Hi, Daniel: On Fri, 2016-11-18 at 11:22 +0800, Daniel Kurtz wrote: > Hi CK, > > On Thu, Nov 17, 2016 at 1:36 PM, CK Hu <ck...@mediatek.com> wrote: > > Hi, Jitao: > > > > > > On Wed, 2016-11-16 at 11:20 +0800, Jitao Shi wrote: > >> Tune dsi fram

Re: [PATCH v2] drm/mediatek: fixed the calc method of data rate per lane

Hi, Jitao: On Tue, 2016-10-25 at 13:40 +0800, Jitao Shi wrote: > Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx, > Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this > signal will cause h-time larger than normal and reduce FPS. > Need to

Re: [PATCH v3] drm/mediatek: fixed the calc method of data rate per lane

Hi, Jitao: On Wed, 2016-10-26 at 16:59 +0800, Jitao Shi wrote: > Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e. Tlpx, > Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP mode, this > signal will cause h-time larger than normal and reduce FPS. > Need to

Re: [PATCH] drm/mediatek: fix null pointer dereference

Hi, Matthias: Even though OVL HW would not be enabled before component_add() in current design, your patch would be safe for any situation. Acked-by CK Hu <ck...@mediatek.com> Regards, CK On Wed, 2016-10-26 at 16:09 +0200, Matthias Brugger wrote: > The probe function requests the

Re: [PATCH v10 12/13] drm/mediatek: update DSI sub driver flow for sending commands to panel

Hi, YT: some comments inline. On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote: > This patch update enable/disable flow of DSI module. > Original flow works on there is a bridge chip: DSI -> bridge -> panel. > In this case: DSI -> panel, the DSI sub driver flow should be updated. > We need to

Re: [PATCH v10 00/13] MT2701 DRM support

Hi, YT: On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote: > This is MT2701 DRM support PATCH v10, based on 4.9-rc1. > We add DSI interrupt control, transfer function for MIPI DSI panel support. > Most codes are the same, except some register changed. > > For example: > - DISP_OVL address offset

Re: [PATCH v10 11/13] drm/mediatek: add dsi rxtx control

Hi, YT: On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote: > add non-continuous clock mode and EOT packet control for dsi > I think commit title should be 'drm/mediatek: add non-continuous clock mode and EOT packet control for dsi', and commit message should describe more information about this

Re: [PATCH v10 09/13] drm/mediatek: add mipi_tx data rate check

Hi, YT: On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote: > modify data rate limitation (>lGbps/lane) for mipitx > I think MT2701 DRM can work correctly without this patch. Why do you put this patch in MT2701 series? Maybe you can send this patch independently. Regards, CK > Signed-off-by:

Re: [PATCH v10 10/13] drm/mediatek: add dsi ulp mode control

Hi, YT: On Fri, 2016-11-25 at 18:34 +0800, YT Shen wrote: > modify dsi enter ultra low power mode method > This looks like a power-saving patch. I think without this, MT2701 could still work correctly. The commit message is too simple, please describe why this patch is related to MT2701. If it

Re: [PATCH v11 02/12] drm/mediatek: add helpers for coverting from the generic components

On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote: > define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_ovl' > define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_rdma' > > Signed-off-by: YT Shen <yt.s...@mediatek.com> Acked-by CK Hu <ck...@mediatek.c

Re: [PATCH v2] drm/mediatek: separate color module to fixup error memory reallocation

On Fri, 2017-06-16 at 22:02 +0800, YT Shen wrote: > Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different > hardware settings) calls devm_kfree() and then devm_kzalloc() to > reallocate color module data structure. But this reallocation cannnot > guarantee the new address is

Re: [PATCH v3] drm: mediatek: change the variable type of rdma threshold

On Thu, 2017-06-22 at 10:43 +0800, Bibby Hsieh wrote: > For some greater resolution, the rdma threshold > variable will overflow. > > Signed-off-by: Bibby Hsieh > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 7 --- > 1 file changed, 4 insertions(+), 3

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