[PATCH 2/2] x86/intel_rdt: Fix bug in initialization, locks and write cbm mask.

en's masks (as it should). Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/include/asm/intel_rdt.h | 12 +--- arch/x86/kernel/cpu/intel_rdt.c | 24 ++-- 2 files changed, 27 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/a

[PATCH 1/2] x86/intel_rdt,intel_cqm: Remove build dependency of RDT code on CQM code.

Minor code move to remove build dependency of RDT code on perf_event_intel_cqm.c . Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/include/asm/pqr_common.h | 3 +++ arch/x86/kernel/cpu/Makefile | 6 +- arch/x86/kern

[PATCH] perf/core: make account/unaccount_sb_event consistent

oup event to terminate, e.g.: $ mkdir /dev/cgroup/devices/test $ perf stat -e cycles -a -G test sleep 0 ... see crash ... Patch rebased on peterz/queue/perf/core . Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- kerne

[PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX

r+0x8/0x10 [ 411.371599] ---[ end trace 1ed61b8a551e95d3 ]--- Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/core.c | 18 +++ arch/x86/events/intel/lbr.c | 73

[PATCH 1/3] perf/x86/intel: output LBR support statement after validation

m> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/core.c | 2 ++ arch/x86/events/intel/lbr.c | 9 - 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 7c66695..a5e5

[PATCH 0/3] fix MSR_LAST_BRANCH_FROM Haswell support

BRS_ON_PMI work-around by allowing LBR call-stack for kernel addresses. This series is rebased at torvalds/linux/master . David Carrillo-Cisneros (3): perf/x86/intel: output LBR support statement after validation perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX perf, perf/too

[PATCH 3/3] perf, perf/tool: trigger lbr_from signext bug

Change kernel and perf tool to activate tracking and context switch for kernel branches. Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/lbr.c | 3 ++- tools/perf/util/evsel.c | 17 ++--- 2 files changed, 16 insertions(+), 4 del

[PATCH v02 0/5] fix MSR_LAST_BRANCH_FROM Haswell support

ranch from quirk (as pointed by Peter Z.). - Format fixes. David Carrillo-Cisneros (5): perf/x86/intel: output LBR support statement after validation perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x bug when no TSX perf/x86/intel: trivial format and style fix perf/x86/intel: MSR_LAST_BRA

[PATCH v02 2/5] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x bug when no TSX

ext switch, that would be required if LBR callstack is to be enabled for ring 0. Signed-off-by: David Carrillo-Cisneros <davi...@google.com> Reviewed-by: Stephane Eranian <eran...@google.com> --- arch/x86/events/intel/core.c | 18 arch/x86/ev

[PATCH v02 3/5] perf/x86/intel: trivial format and style fix

Replace spaces by tabs in LBR_FROM_* constants to align with newly defined constant. Use BIT_ULL. Signed-off-by: David Carrillo-Cisneros <davi...@google.com> Reviewed-by: Stephane Eranian <eran...@google.com> --- arch/x86/events/intel/lbr.c | 6 +++--- 1 file changed, 3 inse

[PATCH v02 4/5] perf/x86/intel: MSR_LAST_BRANCH_FROM_x quirk for ctx switch

[ 411.354229] [] exit_to_usermode_loop+0x39/0x89 [ 411.360246] [] prepare_exit_to_usermode+0x2e/0x30 [ 411.366524] [] retint_user+0x8/0x10 [ 411.371599] ---[ end trace 1ed61b8a551e95d3 ]--- Signed-off-by: David Carrillo-Cisneros <davi...@google.com> Reviewed-by: Stephane Eranian

[PATCH v02 5/5] not required, used to test ctxsw, do not merge

DO NOT MERGE. Provided only to verify bug fix. Change kernel and perf tool to activate tracking and context switch for kernel branches. Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/lbr.c | 3 ++- tools/perf/util/evsel.c | 17 ++

[PATCH v02 1/5] perf/x86/intel: output LBR support statement after validation

commit 338b522ca43c ("perf/x86/intel: Protect LBR and extra_regs against KVM lying") added an additional test to LBR support detection that is performed after printing the LBR support statement to dmesg. Move the LBR support output after the very last test. Signed-off-by: Davi

Re: [PATCH 25/32] sched: introduce the finish_arch_pre_lock_switch() scheduler hook

it independent of perf. The idea is to have future versions of CAT to also rely on this hook. On Fri, Apr 29, 2016 at 11:05 AM, David Carrillo-Cisneros <davi...@google.com> wrote: > This hook is used in the following patch in the series to write to > PQR_ASSOC_MSR, a msr that is utilized bot

Re: [PATCH 26/32] perf/x86/intel/cqm: integrate CQM cgroups with scheduler

> > > On Fri, 29 Apr 2016, David Carrillo-Cisneros wrote: > > > When an event is terminated, intel_cqm_event_stop calls > > pqr_cache_update_rmid and sets state->next_rmid to the rmid of its > > parent in the RMID hierarchy. That would make next call to > > _

[PATCH 00/32] 2nd Iteration of Cache QoS Monitoring support.

vid Carrillo-Cisneros (31): perf/x86/intel/cqm: temporarily remove MBM from CQM and cleanup perf/x86/intel/cqm: remove check for conflicting events perf/x86/intel/cqm: remove all code for rotation of RMIDs perf/x86/intel/cqm: make read of RMIDs per package (Temporal) perf/core: remove unused

[PATCH 01/32] perf/x86/intel/cqm: temporarily remove MBM from CQM and cleanup

Removing MBM code from arch/x86/events/intel/cqm.c. MBM will be added using the new RMID infrastucture introduced in this patch series. Also, remove updates to CQM that are superseded by this series. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros

[PATCH 22/32] perf/x86/intel/cqm: introduce read_subtree

ed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 218 ++-- 1 file changed, 211 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c index 6e85021..c14f1c7 100644 --

[PATCH 02/32] perf/x86/intel/cqm: remove check for conflicting events

The new version of Intel's CQM uses a RMID hierarchy to avoid conflicts between cpu, cgroup and task events, making unnecessary to check and resolve conflicts between events of different types (ie. cgroup vs task). Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Ca

[PATCH 06/32] x86/intel,cqm: add CONFIG_INTEL_RDT configuration flag and refactor PQR

Add Intel's PQR as its own build target, remove its build dependency on CQM, and add CONFIG_INTEL_RDT as a configuration flag to build PQR and all of its related drivers (currently CQM, future: MBM, CAT, CDP). Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Ca

[PATCH 14/32] perf/x86/intel/cqm: add preallocation of anodes

Pre-allocate enough anodes to be able to at least hold one set of RMIDs per package before running out of anodes. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 10 ++ 1 file

[PATCH 09/32] perf/x86/intel/cqm: add per-package RMIDs, data and locks

and rotation logic. This per-package separation reduces the contention for each lock and mutex compared with the previous version (with system-wide mutex and lock). Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events

[PATCH 03/32] perf/x86/intel/cqm: remove all code for rotation of RMIDs

. It also avoid IPIs, and does not keep an unused rotation RMID in some cases (as present version does). Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 371 ---

[PATCH 32/32] perf/stat: revamp error handling for snapshot and per_pkg events

in snapshot event, as should be. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- tools/perf/builtin-stat.c | 37 ++--- tools/perf/util/counts.h | 19 +++ tools/perf/

[PATCH 29/32] perf,perf/x86,perf/powerpc,perf/arm,perf/*: add int error return to pmu::read

PMUs, pmu::read() simply returns 0. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/alpha/kernel/perf_event.c | 3 +- arch/arc/kernel/perf_event.c | 3 +- arch/arm64/include/asm/hw_breakpo

[PATCH 30/32] perf,perf/x86: add hook perf_event_arch_exec

com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/include/asm/perf_event.h | 2 ++ include/linux/perf_event.h| 5 + kernel/events/core.c | 1 + 3 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86

[PATCH 31/32] perf/stat: fix bug in handling events in error state

From: Stephane Eranian When an event is in error state, read() returns 0 instead of sizeof() buffer. In certain modes, such as interval printing, ignoring the 0 return value may cause bogus count deltas to be computed and thus invalid results printed. this patch fixes this

[PATCH 26/32] perf/x86/intel/cqm: integrate CQM cgroups with scheduler

. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 65 +-- arch/x86/events/intel/cqm.h | 2 -- arch/x86/include/asm/pqr_c

[PATCH 25/32] sched: introduce the finish_arch_pre_lock_switch() scheduler hook

in task switch have finished. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/include/asm/processor.h | 4 kernel/sched/core.c | 1 + kernel/sched/sched.h | 3 +++ 3 files changed,

[PATCH 28/32] perf/x86/intel/cqm: add CQM attributes to perf_event cgroup

Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 81 +++ arch/x86/include/asm/perf_event.h | 6 +++ 2 files changed, 87 insertions(+) diff --git a/arch/x86/events/intel/cqm.

[PATCH 27/32] perf/core: add perf_event cgroup hooks for subsystem attributes

Allow architectures to define additional attributes for the perf cgroup. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- include/linux/perf_event.h | 4 kernel/events/core.c | 2 ++ 2 files changed,

[PATCH 19/32] perf/core: introduce PMU event flag PERF_CGROUP_NO_RECURSION

attributes (not suitable for perf_event_attributes). - Are known by the PMU during initialization of struct perf_event. - Signal something to the generic code. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- i

[PATCH 12/32] perf/x86/intel/cqm: add per-package RMID rotation

: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 727 arch/x86/events/intel/cqm.h | 59 +++- 2 files changed, 784 insertions(+), 2 deletions(-) diff --git a

[PATCH 20/32] x86/intel/cqm: use PERF_CGROUP_NO_RECURSION in CQM

to signal perf's generic code to not add events for ancestors of current cgroup. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 8 1 file changed, 8 insertions(+) diff --git a/arc

[PATCH 21/32] perf/x86/intel/cqm: handle inherit event and inherit_stat flag

patches. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c index d8d3191..6e

[PATCH 18/32] perf/x86/intel/cqm: use pmu::event_terminate

Utilized to detach a monr from a cgroup before the event's reference to the cgroup is removed. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 16 +--- 1 file changed, 13 inse

[PATCH 24/32] perf/x86/intel/cqm: use PERF_INACTIVE_*_READ_* flags in CQM

), there is no need to read during sched_out of an event. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/events/intel/cqm.

[PATCH 13/32] perf/x86/intel/cqm: add polled update of RMID's llc_occupancy

. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 251 +++- arch/x86/events/intel/cqm.h | 36 +++ 2 files changed, 286 insertions(+), 1 deletion(-)

[PATCH 23/32] perf/core: introduce PERF_INACTIVE_*_READ_* flags

com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- include/linux/perf_event.h | 15 kernel/events/core.c | 59 +++--- 2 files changed, 60 insertions(+), 14 deletions(-) diff --git a/include/linux/perf_event.h b/i

[PATCH 11/32] perf/x86/intel/cqm: (I)state and limbo prmids

of limbo_prmids is polled periodically and (IL)state pmonrs with limbo prmids that had become clean will transition to (IN)state. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel

[PATCH 10/32] perf/x86/intel/cqm: basic RMID hierarchy with per package rmids

root monr is always (A)ctive. This patch also implements the essential mechanism of per-package lazy allocation of RMID. The (I)state and the transitions from and to it are introduced in the next patch in this series. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: Dav

[PATCH 15/32] perf/core: add hooks to expose architecture specific features in perf_cgroup

The hooks allows architectures to extend the behavior of the perf subsystem. In this patch series, the hooks will be used by Intel's CQM PMU to provide support for the llc_occupancy event. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros

[PATCH 16/32] perf/x86/intel/cqm: add cgroup support

cgroup logic until propertly initialized. The cgroup_init_mutex protects the initialization. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 594

[PATCH 08/32] perf/x86/intel/cqm: prepare for next patches

Move code around, delete unnecesary code and do some renaming in in order to increase readibility of next patches. Create cqm.h file. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel

[PATCH 17/32] perf/core: adding pmu::event_terminate

Allow a PMU to clean an event before the event's torn down in perf_events begins. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- include/linux/perf_event.h | 6 ++ kernel/events/core.c | 4 2 files

[PATCH 04/32] perf/x86/intel/cqm: make read of RMIDs per package (Temporal)

t from other packages. This patch also removes the unused field rmid_usecnt from intel_pqr_state. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 125 ++

[PATCH 05/32] perf/core: remove unused pmu->count

CQM was the only user of pmu->count, no need to have it anymore. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- include/linux/perf_event.h | 6 -- kernel/events/core.c | 10 -- kernel/trace/bpf

[PATCH 07/32] perf/x86/intel/cqm: separate CQM PMU's attributes from x86 PMU

Create a CQM_EVENT_ATTR_STR to use in CQM to remove dependency on the unrelated x86's PMU EVENT_ATTR_STR. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 17 - 1 file

Re: [PATCH v2 10/32] perf/x86/intel/cqm: introduce (I)state and limbo prmids

>> +static inline bool __pmonr__in_instate(struct pmonr *pmonr) >> +{ >> + lockdep_assert_held(&__pkg_data(pmonr, pkg_data_lock)); >> + return __pmonr__in_istate(pmonr) && !__pmonr__in_ilstate(pmonr); >> } > > This state tracking sucks. It's completely non obvious which combinations of >

[PATCH v2 00/32] 2nd Iteration of Cache QoS Monitoring support.

ges in 2nd version: - As requested by Peter Z., redo commit history to completely remove old version of CQM in a single patch. - Use topology_max_packages and fix build errors reported by Vikas Shivappa. - Split largest patches, clean up. - Rebased to peterz/queue perf/core . David Carri

[PATCH v2 01/32] perf/x86/intel/cqm: remove previous version of CQM and MBM

Completely remove previous version of CQM + MBM driver to ease review of new version (this patch series). Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/

[PATCH v2 08/32] perf/x86/intel/cqm: add pmu sysfs attribute

Expose max_recycle_threshold pmu attribute to user-space. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 48 + 1 file changed, 48 inserti

[PATCH v2 05/32] perf/x86/intel/cqm: encapsulate per-package RMIDs

of time when moderately stale values are acceptable, as is the case for some scenarios in this series (e.g. reading occupancy for limbo RMIDs, or multiple transversals of the RMID hierarchy). Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@g

[PATCH v2 20/32] perf/x86/intel/cqm: handle inherit event and inherit_stat flag

as descendats, a potential improvement for future patches. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/cqm.c b/arc

[PATCH v2 29/32] perf,perf/x86,perf/powerpc,perf/arm,perf/*: add int error return to pmu::read

PMUs, pmu::read() simply returns 0. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/alpha/kernel/perf_event.c | 3 +- arch/arc/kernel/perf_event.c | 3 +- arch/arm64/include/asm/hw_breakpo

[PATCH v2 26/32] perf/x86/intel/cqm: make one write of PQR_ASSOC per ctx switch

introduced finish_arch_pre_lock_switch hook. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 12 +++- arch/x86/include/asm/pqr_common.h | 21 ++--- arch/x8

[PATCH v2 07/32] perf/x86/intel/cqm: add helpers for per-package locking

Add helper macros and functions to acquire and release the locks and mutexes in pkg_data. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.h | 78 +

[PATCH v2 02/32] perf/x86/intel/cqm: software cache for MSR_IA32_PQR_ASSOC

ran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/include/asm/pqr_common.h | 44 +++ arch/x86/kernel/cpu/pqr_common.c | 8 +++ 2 files changed, 52 insertions(+) create mode 100644 arch/x86/include/asm/pqr_common.h

[PATCH v2 24/32] sched: introduce the finish_arch_pre_lock_switch() scheduler hook

) will be expanded by Intel's CAT update to the next CLOSID. Since Intel's CAT is independent to perf events, the hook to perform (1) is not suitable to be in perf, yet, must be called as close to perf sched_in as possible. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Ca

[PATCH v2 21/32] perf/x86/intel/cqm: introduce read_subtree

ed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 218 ++-- 1 file changed, 211 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c index 5314a33..12f563d 100644 --

[PATCH v2 19/32] x86/intel/cqm: use PERF_CGROUP_NO_RECURSION in CQM

to signal perf's generic code to not add events for ancestors of current cgroup. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 8 1 file changed, 8 insertions(+) diff --git a/arc

[PATCH v2 12/32] perf/x86/intel/cqm: schedule work for rotation task

Make execution of rotation a delayed_work that does a best effort to rotate __cqm_min_progress_rate pmonrs per-second in every package. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/inte

[PATCH v2 32/32] perf/stat: revamp read error handling, snapshot and per_pkg events

in snapshot event, as should be. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- tools/perf/builtin-stat.c | 37 ++--- tools/perf/util/counts.h | 19 +++ tools/perf/

[PATCH v2 06/32] perf/x86/intel/cqm: add per-package RMIDs, data and locks

-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 499 arch/x86/events/intel/cqm.h | 62 ++ include/linux/perf_event.h | 7 + 3 files changed, 568 inserti

[PATCH v2 03/32] x86/intel,cqm: add CONFIG_INTEL_RDT configuration flag

Add Intel's PQR as its own build target with no build dependency on CQM. Add CONFIG_INTEL_RDT as a configuration flag that builds PQR and related drivers (currently CQM, future: MBM, CAT, CDP). Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros

[PATCH v2 04/32] perf/x86/intel/cqm: add constants for CQM

Add initial constants and comments. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 20 arch/x86/events/intel/cqm.h | 31 +++ 2 files

[PATCH v2 17/32] perf/core,perf/x86/intel/cqm: add pmu::event_terminate

Allow a PMU to clean an event before the event's torn down in perf_events begins. Utilized in CQM to dettach the cgroup from monr before perf removes it from event. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arc

[PATCH v2 14/32] perf/x86/intel/cqm: add preallocation of anodes

Pre-allocate enough anodes to be able to at least hold one set of RMIDs per package before running out of anodes. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 10 ++ 1 file

[PATCH v2 13/32] perf/x86/intel/cqm: add polled update of RMID's llc_occupancy

. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 251 +++- arch/x86/events/intel/cqm.h | 36 +++ 2 files changed, 286 insertions(+), 1 deletion(-)

[PATCH v2 15/32] perf/core: add hooks to expose architecture specific features in perf_cgroup

The hooks allows architectures to extend the behavior of the perf subsystem. In this patch series, the hooks will be used by Intel's CQM PMU to provide support for the llc_occupancy event. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros

[PATCH v2 25/32] perf/x86/intel/cqm: integrate CQM cgroups with scheduler

from using a non-event cgroup RMID. The cgroup sched in code is called when the last RMID has mode PQR_RMID_MODE_NOEVENT. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.

[PATCH v2 31/32] perf/stat: fix bug in handling events in error state

From: Stephane Eranian When an event is in error state, read() returns 0 instead of sizeof() buffer. In certain modes, such as interval printing, ignoring the 0 return value may cause bogus count deltas to be computed and thus invalid results printed. this patch fixes this

[PATCH v2 27/32] perf/core: add perf_event cgroup hooks for subsystem attributes

Allow architectures to define additional attributes for the perf cgroup. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- include/linux/perf_event.h | 4 kernel/events/core.c | 2 ++ 2 files changed,

[PATCH v2 28/32] perf/x86/intel/cqm: add CQM attributes to perf_event cgroup

Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 81 +++ arch/x86/include/asm/perf_event.h | 10 + 2 files changed, 91 insertions(+) diff --git a/arch/x86/events/intel/

[PATCH v2 30/32] perf,perf/x86: add hook perf_event_arch_exec

com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/include/asm/perf_event.h | 2 ++ include/linux/perf_event.h| 5 + kernel/events/core.c | 1 + 3 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86

[PATCH v2 18/32] perf/core: introduce PMU event flag PERF_CGROUP_NO_RECURSION

attributes (not suitable for perf_event_attributes). - Are known by the PMU during initialization of struct perf_event. - Signal something to the generic code. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- i

[PATCH v2 23/32] perf/x86/intel/cqm: use PERF_INACTIVE_*_READ_* flags in CQM

), there is no need to read during sched_out of an event. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/events/intel/cqm.

[PATCH v2 22/32] perf/core: introduce PERF_INACTIVE_*_READ_* flags

. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- include/linux/perf_event.h | 17 kernel/events/core.c | 49 +- 2 files changed, 57 insertions(+), 9 deletions(-)

[PATCH v2 16/32] perf/x86/intel/cqm: add cgroup support

cgroup logic until propertly initialized. The cgroup_init_mutex protects the initialization. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 595

[PATCH v2 09/32] perf/x86/intel/cqm: basic RMID hierarchy with per package RMIDs

eaves. The root monr is always (A)ctive. This patch also implements the essential mechanism of per-package lazy allocation of RMID. The (I)state and the transitions from and to it are introduced in the next patch in this series. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-b

[PATCH v2 10/32] perf/x86/intel/cqm: introduce (I)state and limbo prmids

of limbo_prmids is polled periodically and (IL)state pmonrs with limbo prmids that had become "clean" will be transitioned to (IN)state and their prmid reused. Reviewed-by: Stephane Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/

[PATCH v2 11/32] perf/x86/intel/cqm: add per-package RMID rotation

ne Eranian <eran...@google.com> Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- arch/x86/events/intel/cqm.c | 659 arch/x86/events/intel/cqm.h | 40 +++ 2 files changed, 699 insertions(+) diff --git a/arch/x86/events/intel/c

Re: [PATCH 25/32] sched: introduce the finish_arch_pre_lock_switch() scheduler hook

That's a possibility, although it will increase the distance between pmu->add for other perf events and the effective time that CQM monitoring starts. On Fri, Apr 29, 2016 at 1:21 PM, Vikas Shivappa <vikas.shiva...@linux.intel.com> wrote: > > > On Fri, 29 Apr 2016, David Carri

Re: [PATCH 26/32] perf/x86/intel/cqm: integrate CQM cgroups with scheduler

; > On Fri, 29 Apr 2016, David Carrillo-Cisneros wrote: > >> Not sure I see the problem you point here. In step 3, PQR_ASSOC is >> updated with RMID1, __pqr_update is the one called using the scheduler >> hook, right after perf sched_in . >> >> On Fri, A

Re: [PATCH 00/32] 2nd Iteration of Cache QoS Monitoring support.

peterz/queue perf/core On Fri, Apr 29, 2016 at 2:06 PM Vikas Shivappa <vikas.shiva...@linux.intel.com> wrote: > > > > On Thu, 28 Apr 2016, David Carrillo-Cisneros wrote: > > > This series introduces the next iteration of kernel support for the > > Cache QoS Moni

Re: [PATCH 26/32] perf/x86/intel/cqm: integrate CQM cgroups with scheduler

es to PQR MSR within the per-pcu >> pqr state variable. This interface to update RMIDs and CLOSIDs will be >> also utilized in upcoming versions of Intel's MBM and CAT drivers. >> >> Reviewed-by: Stephane Eranian <eran...@google.com> >> Signed-off-by: David Carri

Re: [PATCH 26/32] perf/x86/intel/cqm: integrate CQM cgroups with scheduler

el.com> wrote: > > > > On Fri, 29 Apr 2016, David Carrillo-Cisneros wrote: > > > if __intel_cqm_no_event_sched_in does nothing, the PQR_ASSOC msr is > > still updated if state->rmid != state->next_rmid in __pqr_update, > > But due to 2 and 3 below

Re: [PATCH v2 11/32] perf/x86/intel/cqm: add per-package RMID rotation

On Wed, May 18, 2016 at 2:39 PM Thomas Gleixner <t...@linutronix.de> wrote: > > On Wed, 11 May 2016, David Carrillo-Cisneros wrote: > > @@ -216,6 +216,9 @@ static int pkg_data_init_cpu(int cpu) > > INIT_LIST_HEAD(_data->istate_pmonrs_lru); > > INIT_LI

Re: [PATCH 05/32] x86/intel_rdt: Implement scheduling support for Intel RDT

On Mon, Jul 25, 2016 at 11:05 AM Luck, Tony wrote: > > On Mon, Jul 25, 2016 at 11:31:24AM -0500, Nilay Vaish wrote: > > I was thinking more about this software caching of CLOSids. How > > likely do you think these CLOSids would be found cached? I think the > > software

Re: [PATCH] perf/core: set cgroup for cpu contexts for new cgroup events

to the wrong git tree, please drop us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/David-Carrillo-Cisneros/perf-core-set-cgroup-for-cpu-contexts-for-new-cgroup-events/20160802-110924 > config: x86_64-randconfig-x012-201631 (attached as .confi

[PATCH v2] perf/core: set cgroup in cpu contexts for new cgroup events

usive variables from builds without CONFIG_CGROUP_PERF. Signed-off-by: David Carrillo-Cisneros <davi...@google.com> --- include/linux/perf_event.h | 4 kernel/events/core.c | 54 ++ 2 files changed, 40 insertions(+), 18 deletions(-) diff --git a

[PATCH 1/3] perf/core: check return value of perf_event_read IPI

The call to smp_call_function_single in perf_event_read() may fail and, when it does, its error value is the one to return. Signed-off-by: David Carrillo-Cisneros <davi...@google.com> Reviewed-by: Stephane Eranian <eran...@google.com> --- kernel/events/core.c | 4 ++-- 1 fil

Re: [PATCH v2] perf/core: set cgroup in cpu contexts for new cgroup events

Hi Vegard, I don't think this patch fixes your bug, but it touches some code that may be related. David On Wed, Aug 3, 2016 at 8:46 AM, Vegard Nossum <vegard.nos...@gmail.com> wrote: > Hi, > > On 2 August 2016 at 09:48, David Carrillo-Cisneros <davi...

Re: [PATCH 30/32] x86/intel_rdt_rdtgroup.c: Process schemas input from rscctrl interface

> +static int get_res_type(char **res, enum resource_type *res_type) > +{ > + char *tok; > + > + tok = strsep(res, ":"); > + if (tok == NULL) > + return -EINVAL; > + > + if (!strcmp(tok, "L3")) { Maybe use strstrip to allow a more readable input ? i.e. "L3 :

Re: [PATCH 06/32] x86/intel_rdt: Hot cpu support for Cache Allocation

> +static inline void intel_rdt_cpu_start(int cpu) > +{ > + struct intel_pqr_state *state = _cpu(pqr_state, cpu); > + > + state->closid = 0; > + mutex_lock(_group_mutex); > + if (rdt_cpumask_update(cpu)) > + smp_call_function_single(cpu, cbm_update_msrs, NULL,

Re: [PATCH 2/3] perf/core: introduce pmu_event_flags and PMUEF_READ_CPU_PKG

>> struct list_headsb_list; >> + >> + /* Per-event flags to generic code set by PMU. */ >> + int pmu_event_flags; >> + > > It appears to me we already have group_flags and attach_state which both > are serialized by ctx->lock. > > Could we

Re: [PATCH 2/3] perf/core: introduce pmu_event_flags and PMUEF_READ_CPU_PKG

>> Introduce the flag PMUEF_READ_CPU_PKG, useful for uncore events, that >> allows a PMU to signal the generic perf code that an event is readable >> on the current CPU if the event is: >> - active in a CPU in the same package as the current CPU (local CPU) > > Ok that I get.. > >> - not

Re: [PATCH 2/3] perf/core: introduce pmu_event_flags and PMUEF_READ_CPU_PKG

On Thu, Aug 4, 2016 at 10:27 AM, Peter Zijlstra <pet...@infradead.org> wrote: > On Thu, Aug 04, 2016 at 10:23:43AM -0700, David Carrillo-Cisneros wrote: >> >> Introduce the flag PMUEF_READ_CPU_PKG, useful for uncore events, that >> >> allows a PMU to signal th

[PATCH v2 1/4] perf/core: check return value of perf_event_read IPI

The call to smp_call_function_single in perf_event_read() may fail and, when it does, its error value is the one to return. Signed-off-by: David Carrillo-Cisneros <davi...@google.com> Reviewed-by: Stephane Eranian <eran...@google.com> --- kernel/events/core.c | 6 +++--- 1 fil

[PATCH v2 4/4] perf/x86: use PMUEF_READ_CPU_PKG in uncore events

Add flag to Intel's uncore and RAPL. Signed-off-by: David Carrillo-Cisneros <davi...@google.com> Reviewed-by: Stephane Eranian <eran...@google.com> --- arch/x86/events/intel/rapl.c | 2 ++ arch/x86/events/intel/uncore.c | 2 ++ arch/x86/events/intel/uncore_snb.c | 2 ++ 3 f

  1   2   3   4   5   6   7   8   9   10   >