On Thu, 2012-10-04 at 19:40 +0200, Michal Simek wrote:
From: Wendy Liang wendy.li...@petalogix.com
Add the id and sector mappings for SPI flash chips.
An equivalent patch is already in David Woodhouse's l2-mtd tree:
Hi Sören,
On Tue, 2013-03-05 at 12:04 -0800, Sören Brinkmann wrote:
For this reasons, I'd like to propose moving Zynq into the same
direction. I.e. adding a clock controller with the following DT
description (details may change but the general idea should become
clear):
clkc: clkc {
On Fri, 2013-01-18 at 12:11 +0530, Philip Avinash wrote:
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index eaef5e7..f4209d8 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -393,5 +393,17 @@
ti,hwmods =
On Fri, 2012-08-31 at 11:27 +0200, Philipp Zabel wrote:
This driver requests and remaps a memory region as configured in the
device tree. It serves memory from this region via the genalloc API.
Other drivers can retrieve the genalloc pool from a phandle pointing
to this drivers' device node
On Tue, 2013-10-22 at 10:05 +0100, Lee Jones wrote:
This is the first time this patch has been sent to me.
I need Dmitry's input (no pun intended) on how he's like to deal with
this. At a bare minimum I'd like his Ack.
Is there anything I can do to push this forward? The earlier we get the
On Tue, 2013-11-05 at 17:15 +, Lee Jones wrote:
On Tue, 05 Nov 2013, Jan Lübbe wrote:
On Tue, 2013-10-22 at 10:05 +0100, Lee Jones wrote:
This is the first time this patch has been sent to me.
I need Dmitry's input (no pun intended) on how he's like to deal
,
Jan Lübbe
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Rodolfo, would you take these patches?
Regards,
Jan
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht
Marc,
On Fri, 2014-08-22 at 12:09 +0100, Marc Zyngier wrote:
Here, you're using it to program something that sits between the
device and the GIC. This is a separate block, with its own hardware
configuration, that modifies the interrupt signal. This should be
reflected in the device-tree and
Hi Gary,
On Do, 2015-04-02 at 12:21 -0700, Gary E. Miller wrote:
In the conversion from platform to device tree the capture-clear
option was lost.
capture-clear is needed so that time_pps_fetch() will report both
edges of each PPS pulse. Both edges are needed so that userland
programs,
it can't pass the tuning procedure.
So this patch add the tuning-step setting in driver, so that user can
set the tuning-step value in dts.
From your description, the correct tuning-step value only depends on the
SoC. Why not derive it from the compatible string?
Regards,
Jan Lübbe
On Mi, 2014-11-26 at 19:05 +0200, Grygorii Strashko wrote:
On 11/26/2014 06:04 PM, Uwe Kleine-König wrote:
On Wed, Nov 26, 2014 at 03:59:53PM +0200, Grygorii Strashko wrote:
Having a board where the I2C bus locks up occasionally made it clear
that the bus recovery in the i2c-davinci driver
1 1>; /* sub display with merging wfe */
It seems that you use two cells instead of one as you declared above.
This should be consistent.
Also, why do you need an explicit phandle to the gce if you already use
mailboxes?
Best regards,
Jan Lübbe
--
Pengutronix e.K.
On Mo, 2017-02-27 at 16:27 -0600, Rob Herring wrote:
> On Mon, Feb 27, 2017 at 3:48 AM, Jan Lübbe <j...@pengutronix.de> wrote:
> > On Di, 2017-02-21 at 15:57 +0100, Richard Leitner wrote:
> >> >>> This is a lot of properties. Are you really findin
On Di, 2017-02-21 at 15:57 +0100, Richard Leitner wrote:
> >>> This is a lot of properties. Are you really finding a need for all of
> >>> them? Is this to handle h/w designers too cheap to put down the EEPROM?
> >>> Maybe better to just define an eeprom property in the format the h/w
> >>>
On Mo, 2016-11-28 at 17:04 -0600, Grygorii Strashko wrote:
> This patch adds support of the CPTS HW_TS_PUSH events which are generated
> by external low frequency time stamp channels on TI's OMAP CPSW and
> Keystone 2 platforms. It supports up to 8 external time stamp channels for
> HW_TS_PUSH
On Mo, 2016-11-28 at 17:04 -0600, Grygorii Strashko wrote:
> --- a/Documentation/devicetree/bindings/net/keystone-netcp.txt
> +++ b/Documentation/devicetree/bindings/net/keystone-netcp.txt
> @@ -127,6 +127,16 @@ Optional properties:
> The number of external time stamp channels.
>
On Sat, 2017-07-22 at 08:53 -0700, Kevin Hilman wrote:
> > Boot Failures Detected:
> >
> > arm:
> >
> > multi_v7_defconfig
> > imx6ul-pico-hobbit_rootfs:nfs: 1 failed lab
> >
> > tegra_defconfig
> > tegra124-jetson-tk1_rootfs:nfs: 1 failed lab
>
> @Jan looks like a
On Thu, 2017-08-10 at 21:17 +, Chris Packham wrote:
> On 11/08/17 08:38, Rob Herring wrote:
> > On Mon, Aug 07, 2017 at 01:46:39PM +1200, Chris Packham wrote:
[...]
> > > +Optional properties:
> > > + - marvell,reduced-width: some SoCs that use this SDRAM controller have
> > > + a reduced
On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote:
> + if (of_property_read_bool(np, "arm,ecc-enable")) {
> + mask |= L2C_AUX_CTRL_EVTMON_ENABLE;
> + val |= L2C_AUX_CTRL_EVTMON_ENABLE;
> + } else if (of_property_read_bool(np, "arm,ecc-disable")) {
> +
Chris,
On So, 2017-06-11 at 22:55 +, Chris Packham wrote:
> On 09/06/17 20:58, Jan Lübbe wrote:
> > On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote:
> >> + if (of_property_read_bool(np, "arm,ecc-enable")) {
> >> +
Hi Chris,
On Fr, 2017-06-09 at 15:14 +0200, Jan Lübbe wrote:
> > +static void mvebu_init_csrows(struct mem_ctl_info *mci,
> > + struct mvebu_mc_pdata *pdata)
> [...]
> > + devtype = (ctl >> 20) & 0x3;
> > +
Hi,
I've CCed Rob as the original author of the ARM EDAC scrub function.
On Fr, 2017-06-09 at 15:14 +0200, Jan Lübbe wrote:
> [...]
> > + mci->scrub_mode = SCRUB_SW_SRC;
> I'm not sure if this works as expected ARM as it is currently
> implemented, but that's a topic fo
Hi Chris!
On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote:
> This adds an EDAC driver for the memory controller and L2 cache used on
> a number of Marvell Armada SoCs.
Why have two separate drivers in the same file and enabled with the same
Kconfig option?
[...]
> +static void
On Fri, 2018-07-20 at 11:16 +0530, Udit Agarwal wrote:
> +==
> +Secure Key
> +==
> +
> +Secure key is the new type added to kernel key ring service.
> +Secure key is a symmetric type key of minimum length 32 bytes
> +and with maximum possible length to be 128 bytes. It is produced
Hi,
On Sat, 2018-07-21 at 14:44 +, Udit Agarwal wrote:
> Thanks for sharing the documentation changes and feedback.
>
> Below are the answers to the questions:
>
> 1. Currently the secure key patch series has been added to support
> only data blobs.
> It is not supporting key blobs as of
On Tue, 2013-10-22 at 10:05 +0100, Lee Jones wrote:
> This is the first time this patch has been sent to me.
>
> I need Dmitry's input (no pun intended) on how he's like to deal with
> this. At a bare minimum I'd like his Ack.
Is there anything I can do to push this forward? The earlier we get
On Tue, 2013-11-05 at 17:15 +, Lee Jones wrote:
> On Tue, 05 Nov 2013, Jan Lübbe wrote:
>
> > On Tue, 2013-10-22 at 10:05 +0100, Lee Jones wrote:
> > > This is the first time this patch has been sent to me.
> > >
> > > I need Dmitry's input (no
as a non-critical
> fix assuming the bootloaders are not yet using this:
>
> Acked-by: Tony Lindgren
It seems this didn't get applied. It fixes the touchscreen on a
BeagleBone black with the 7" LCD and we should avoid having people use
the wrong binding.
Samuel or Lee
Rodolfo, would you take these patches?
Regards,
Jan
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht
Hi Sören,
On Tue, 2013-03-05 at 12:04 -0800, Sören Brinkmann wrote:
> For this reasons, I'd like to propose moving Zynq into the same
> direction. I.e. adding a clock controller with the following DT
> description (details may change but the general idea should become
> clear):
> clkc: clkc
On Sat, 2017-07-22 at 08:53 -0700, Kevin Hilman wrote:
> > Boot Failures Detected:
> >
> > arm:
> >
> > multi_v7_defconfig
> > imx6ul-pico-hobbit_rootfs:nfs: 1 failed lab
> >
> > tegra_defconfig
> > tegra124-jetson-tk1_rootfs:nfs: 1 failed lab
>
> @Jan looks like a
On Thu, 2017-08-10 at 21:17 +, Chris Packham wrote:
> On 11/08/17 08:38, Rob Herring wrote:
> > On Mon, Aug 07, 2017 at 01:46:39PM +1200, Chris Packham wrote:
[...]
> > > +Optional properties:
> > > + - marvell,reduced-width: some SoCs that use this SDRAM controller have
> > > + a reduced
On Thu, 2012-10-04 at 19:40 +0200, Michal Simek wrote:
> From: Wendy Liang
>
> Add the id and sector mappings for SPI flash chips.
An equivalent patch is already in David Woodhouse's l2-mtd tree:
On Fri, 2012-08-31 at 11:27 +0200, Philipp Zabel wrote:
> This driver requests and remaps a memory region as configured in the
> device tree. It serves memory from this region via the genalloc API.
>
> Other drivers can retrieve the genalloc pool from a phandle pointing
> to this drivers' device
On Fri, 2013-01-18 at 12:11 +0530, Philip Avinash wrote:
> diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
> index eaef5e7..f4209d8 100644
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> @@ -393,5 +393,17 @@
> ti,hwmods
On Sun, 2021-01-31 at 09:29 -0500, Mimi Zohar wrote:
> On Sun, 2021-01-31 at 15:14 +0100, Jan Lübbe wrote:
> > On Sun, 2021-01-31 at 07:09 -0500, Mimi Zohar wrote:
>
>
>
> > >
> > > [1] The ima-evm-utils README contains EVM examples of "trusted
On Mon, 2021-02-01 at 11:11 -0500, Mimi Zohar wrote:
> On Mon, 2021-02-01 at 16:31 +0100, Jan Lübbe wrote:
> > On Sun, 2021-01-31 at 09:29 -0500, Mimi Zohar wrote:
> > > Usage::
> > >
> > > keyctl add encrypted name "new [format] key-type:master-k
On Mon, 2021-02-01 at 11:36 +, David Howells wrote:
> Jan Lübbe wrote:
>
> > ... But at this point, you can still do 'keyctl read' on that key, exposing
> > the key material to user space.
>
> I wonder if it would help to provide a keyctl function to mark a ke
On Tue, 2021-02-02 at 17:45 +0530, Sumit Garg wrote:
> Hi Jan,
>
> On Sun, 31 Jan 2021 at 23:40, James Bottomley wrote:
> >
> > On Sun, 2021-01-31 at 15:14 +0100, Jan Lübbe wrote:
> > > On Sun, 2021-01-31 at 07:09 -0500, Mimi Zohar wrote:
> > > >
On Wed, 2021-02-03 at 17:20 +0530, Sumit Garg wrote:
> On Tue, 2 Feb 2021 at 18:04, Jan Lübbe wrote:
> >
> > On Tue, 2021-02-02 at 17:45 +0530, Sumit Garg wrote:
> > > Hi Jan,
> > >
> > > On Sun, 31 Jan 2021 at 23:40, James Bottomley wrote:
> >
On Wed, 2019-05-22 at 11:00 -0700, Andrew Morton wrote:
> On Wed, 22 May 2019 18:16:14 +0200 Jan Luebbe wrote:
>
> > Commit 0a1eb2d474ed ("fs/proc: Stop reporting eip and esp in
> > /proc/PID/stat") stopped reporting eip/esp and commit fd7d56270b52
> > ("fs/proc: Report eip/esp in /prod/PID/stat
Hi Philipp,
see below...
On Thu, 2019-09-19 at 16:29 +0200, Philipp Puschmann wrote:
> For some years and since many kernel versions there are reports that the
> RX UART SDMA channel stops working at some point. The workaround was to
> disable DMA for RX. This commit tries to fix the problem
On Mon, 2019-09-23 at 17:06 +0200, Philipp Puschmann wrote:
> Thanks for testing.
> With my local setup i still have very few tx timeouts too. But i think they
> have a different
> cause and especially different consequences. When the problem addressed by
> this series
> appear you get a whole
On Thu, 2019-08-29 at 20:09 -0400, Stefan Berger wrote:
> From: Stefan Berger
>
> The tpm_tis_core has to set the TPM_CHIP_FLAG_IRQ before probing for
> interrupts since there is no other place in the code that would set
> it.
Thanks for this patch! I tested it to fix a
[ 13.198129] tpm
On Thu, 2019-05-30 at 02:58 +0200, John Ogness wrote:
> Commit 0a1eb2d474ed ("fs/proc: Stop reporting eip and esp in
> /proc/PID/stat") stopped reporting eip/esp and commit fd7d56270b52
> ("fs/proc: Report eip/esp in /prod/PID/stat for coredumping")
> reintroduced the feature to fix a regression
Hi Franck,
thanks for working on this!
On Fri, 2019-03-01 at 17:09 +0100, Franck LENORMAND wrote:
> The creation of such structures and its use was not exposed to userspace so
> it was complicated to use and required custom development. We would like to
> ease this using interface which are
On Fri, 2018-07-20 at 11:16 +0530, Udit Agarwal wrote:
> +==
> +Secure Key
> +==
> +
> +Secure key is the new type added to kernel key ring service.
> +Secure key is a symmetric type key of minimum length 32 bytes
> +and with maximum possible length to be 128 bytes. It is produced
Hi,
On Sat, 2018-07-21 at 14:44 +, Udit Agarwal wrote:
> Thanks for sharing the documentation changes and feedback.
>
> Below are the answers to the questions:
>
> 1. Currently the secure key patch series has been added to support
> only data blobs.
> It is not supporting key blobs as of
Marc,
On Fri, 2014-08-22 at 12:09 +0100, Marc Zyngier wrote:
> Here, you're using it to program something that sits between the
> device and the GIC. This is a separate block, with its own hardware
> configuration, that modifies the interrupt signal. This should be
> reflected in the device-tree
Hi Gary,
On Do, 2015-04-02 at 12:21 -0700, Gary E. Miller wrote:
> In the conversion from platform to device tree the capture-clear
> option was lost.
>
> capture-clear is needed so that time_pps_fetch() will report both
> edges of each PPS pulse. Both edges are needed so that userland
>
p value as 2, otherwise it can't pass the tuning procedure.
>
> So this patch add the tuning-step setting in driver, so that user can
> set the tuning-step value in dts.
>From your description, the correct tuning-step value only depends on the
SoC. Why not derive it from the compatible str
On Mi, 2014-11-26 at 19:05 +0200, Grygorii Strashko wrote:
> On 11/26/2014 06:04 PM, Uwe Kleine-König wrote:
> > On Wed, Nov 26, 2014 at 03:59:53PM +0200, Grygorii Strashko wrote:
> >> Having a board where the I2C bus locks up occasionally made it clear
> >> that the bus recovery in the
Hi Chris,
On Fr, 2017-06-09 at 15:14 +0200, Jan Lübbe wrote:
> > +static void mvebu_init_csrows(struct mem_ctl_info *mci,
> > + struct mvebu_mc_pdata *pdata)
> [...]
> > + devtype = (ctl >> 20) & 0x3;
> > +
Chris,
On So, 2017-06-11 at 22:55 +, Chris Packham wrote:
> On 09/06/17 20:58, Jan Lübbe wrote:
> > On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote:
> >> + if (of_property_read_bool(np, "arm,ecc-enable")) {
> >> +
On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote:
> + if (of_property_read_bool(np, "arm,ecc-enable")) {
> + mask |= L2C_AUX_CTRL_EVTMON_ENABLE;
> + val |= L2C_AUX_CTRL_EVTMON_ENABLE;
> + } else if (of_property_read_bool(np, "arm,ecc-disable")) {
> +
Hi Chris!
On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote:
> This adds an EDAC driver for the memory controller and L2 cache used on
> a number of Marvell Armada SoCs.
Why have two separate drivers in the same file and enabled with the same
Kconfig option?
[...]
> +static void
Hi,
I've CCed Rob as the original author of the ARM EDAC scrub function.
On Fr, 2017-06-09 at 15:14 +0200, Jan Lübbe wrote:
> [...]
> > + mci->scrub_mode = SCRUB_SW_SRC;
> I'm not sure if this works as expected ARM as it is currently
> implemented, but that's a topic fo
On Mo, 2017-02-27 at 16:27 -0600, Rob Herring wrote:
> On Mon, Feb 27, 2017 at 3:48 AM, Jan Lübbe wrote:
> > On Di, 2017-02-21 at 15:57 +0100, Richard Leitner wrote:
> >> >>> This is a lot of properties. Are you really finding a need for all of
> >> >>&
On Di, 2017-02-21 at 15:57 +0100, Richard Leitner wrote:
> >>> This is a lot of properties. Are you really finding a need for all of
> >>> them? Is this to handle h/w designers too cheap to put down the EEPROM?
> >>> Maybe better to just define an eeprom property in the format the h/w
> >>>
On Mo, 2016-11-28 at 17:04 -0600, Grygorii Strashko wrote:
> --- a/Documentation/devicetree/bindings/net/keystone-netcp.txt
> +++ b/Documentation/devicetree/bindings/net/keystone-netcp.txt
> @@ -127,6 +127,16 @@ Optional properties:
> The number of external time stamp channels.
>
On Mo, 2016-11-28 at 17:04 -0600, Grygorii Strashko wrote:
> This patch adds support of the CPTS HW_TS_PUSH events which are generated
> by external low frequency time stamp channels on TI's OMAP CPSW and
> Keystone 2 platforms. It supports up to 8 external time stamp channels for
> HW_TS_PUSH
1 1>; /* sub display with merging wfe */
It seems that you use two cells instead of one as you declared above.
This should be consistent.
Also, why do you need an explicit phandle to the gce if you already use
mailboxes?
Best regards,
Jan Lübbe
--
Pengutronix e.K.
On Mon, 2021-02-01 at 14:46 -0500, Mimi Zohar wrote:
> On Mon, 2021-02-01 at 17:38 +0100, Jan Lübbe wrote:
> > On Mon, 2021-02-01 at 11:11 -0500, Mimi Zohar wrote:
> > > On Mon, 2021-02-01 at 16:31 +0100, Jan Lübbe wrote:
> > > > On Sun, 2021-01-31 at
On Mon, 2021-02-08 at 16:50 -0500, Mimi Zohar wrote:
> On Mon, 2021-02-08 at 15:38 +0100, Jan Lübbe wrote:
>
> > As it seems that this feature would not be appropriate for all use-cases and
> > threat models, I wonder if making it optional would be acceptable. Something
> &g
On Sun, 2021-01-31 at 07:09 -0500, Mimi Zohar wrote:
> On Sat, 2021-01-30 at 19:53 +0200, Jarkko Sakkinen wrote:
> > On Thu, 2021-01-28 at 18:31 +0100, Ahmad Fatoum wrote:
> > > Hello,
> > >
> > > I've been looking into how a migration to using trusted/encrypted keys
> > > would look like
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