On 06/16/2014 01:43 PM, Stefano Stabellini wrote:
On Fri, 13 Jun 2014, Daniel Kiper wrote:
efi_set_rtc_mmss() is never used to set RTC due to bugs found
on many EFI platforms. It is set directly by mach_set_rtc_mmss().
Signed-off-by: Daniel Kiper daniel.ki...@oracle.com
---
On 08/22/2014 11:32 AM, Jan Beulich wrote:
On 19.08.14 at 15:25, jgr...@suse.com wrote:
@@ -118,8 +167,14 @@ void pat_init(void)
PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, UC);
/* Boot CPU check */
- if (!boot_pat_state)
+ if (!boot_pat_state) {
cache mode
Changes since RFC:
- renamed functions and variables as suggested by Toshi Kani
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (3):
x86: Make page cache mode a real type
x86: Enable PAT to use
...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/cacheflush.h | 38 +
arch/x86/include/asm/fb.h | 6 +-
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h| 6 +-
arch/x86/include/asm
With the dynamical mapping between cache modes and pgprot values it is now
possible to use all cache modes via the Xen hypervisor PAT settings in a
pv domain.
All to be done is to read the PAT configuration MSR and set up the translation
tables accordingly.
Signed-off-by: Juergen Gross jgr
cache mode
Changes since RFC:
- renamed functions and variables as suggested by Toshi Kani
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (3):
x86: Make page cache mode a real type
x86: Enable PAT to use
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c | 8 ++
arch/x86/mm/pat.c| 54
On 08/26/2014 12:59 PM, David Vrabel wrote:
On 26/08/14 07:16, Juergen Gross wrote:
With the dynamical mapping between cache modes and pgprot values it is now
possible to use all cache modes via the Xen hypervisor PAT settings in a
pv domain.
All to be done is to read the PAT configuration MSR
On 08/26/2014 09:44 PM, Toshi Kani wrote:
On Tue, 2014-08-26 at 08:16 +0200, Juergen Gross wrote:
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because there are a lot
During test of Xen pvSCSI frontend module I found the following issue:
When unplugging a passed-through SCSI-device the SCSI Host is removed.
When calling the final scsi_host_put() from the driver an Oops is
happening:
[ 219.816292] (file=drivers/scsi/xen-scsifront.c, line=808)
On 08/01/2014 07:41 AM, Juergen Gross wrote:
During test of Xen pvSCSI frontend module I found the following issue:
When unplugging a passed-through SCSI-device the SCSI Host is removed.
When calling the final scsi_host_put() from the driver an Oops is
happening:
[ 219.816292] (file=drivers
On 08/01/2014 09:05 AM, James Bottomley wrote:
On Fri, 2014-08-01 at 08:02 +0200, Juergen Gross wrote:
On 08/01/2014 07:41 AM, Juergen Gross wrote:
During test of Xen pvSCSI frontend module I found the following issue:
When unplugging a passed-through SCSI-device the SCSI Host is removed
On 08/01/2014 10:24 PM, James Bottomley wrote:
On Fri, 2014-08-01 at 05:03 -0700, Christoph Hellwig wrote:
On Fri, Aug 01, 2014 at 08:27:05AM +0200, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
If a scsi host driver specifies .cmd_len in it's scsi_host_template, a driver's
On 08/04/2014 01:08 PM, Christoph Hellwig wrote:
On Mon, Aug 04, 2014 at 06:26:09AM +0200, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
If a scsi host driver specifies .cmd_len in it's scsi_host_template, a driver's
private command pool is needed. scsi_find_host_cmd_pool
On 08/04/2014 01:24 PM, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
If a scsi host driver specifies .cmd_len in it's scsi_host_template, a driver's
private command pool is needed. scsi_find_host_cmd_pool() will locate it, but
scsi_alloc_host_cmd_pool() isn't saving the pool
On 08/04/2014 01:49 PM, Boaz Harrosh wrote:
On 08/04/2014 02:30 PM, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
If a scsi host driver specifies .cmd_len in it's scsi_host_template, a driver's
private command pool is needed. scsi_find_host_cmd_pool() will locate
On 08/20/2014 02:05 PM, One Thousand Gnomes wrote:
The Linux kernel currently supports only 4 different cache modes. The PAT MSR
is set up in a way that the setting of _PAGE_PAT in a pte doesn't matter: the
top 4 entries in the PAT MSR are the same as the 4 lower entries.
This results in the
On 08/20/2014 09:26 PM, Toshi Kani wrote:
On Tue, 2014-08-19 at 15:25 +0200, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only
On 08/22/2014 12:09 AM, Toshi Kani wrote:
On Tue, 2014-08-19 at 15:25 +0200, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only
On 08/13/2014 11:29 AM, David Vrabel wrote:
On 12/08/14 14:43, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
bind_interdomain_evtchn_to_irq() is currently a private function. It is used
only by bind_interdomain_evtchn_to_irqhandler() to register an irq-handler for
an event channel
On 08/13/2014 11:53 AM, David Vrabel wrote:
On 12/08/14 14:43, jgr...@suse.com wrote:
From: Juergen Gross jgr...@suse.com
bind_interdomain_evtchn_to_irq() is currently a private function. It is used
only by bind_interdomain_evtchn_to_irqhandler() to register an irq-handler for
an event channel
On 08/13/2014 11:54 AM, David Vrabel wrote:
On 13/08/14 10:43, Juergen Gross wrote:
static int scsiback_init_sring(struct vscsibk_info *info, grant_ref_t
ring_ref,
evtchn_port_t evtchn)
{
...
irq = bind_interdomain_evtchn_to_irq(info-domid, evtchn
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
Adding relevant mailing lists.
On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross jgr...@suse.com wrote:
I'm just about to create a patch for full PAT support in the Linux
Hi,
I'm just about to create a patch for full PAT support in the Linux
kernel, including Xen. For this purpose I introduce a translation
between cache modes and pte bits.
Scanning the kernel sources for usage of the cache mode bits in the
pte I discovered drivers/gpu/drm/i915/i915_gem_gtt.h is
On 08/15/2014 12:21 PM, Ville Syrjälä wrote:
On Thu, Aug 14, 2014 at 05:55:11AM +0200, Juergen Gross wrote:
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
Adding relevant mailing lists.
On Fri, Aug 8, 2014 at 1:23 PM
On 08/18/2014 12:21 PM, Ville Syrjälä wrote:
On Mon, Aug 18, 2014 at 07:31:58AM +0200, Juergen Gross wrote:
On 08/15/2014 12:21 PM, Ville Syrjälä wrote:
On Thu, Aug 14, 2014 at 05:55:11AM +0200, Juergen Gross wrote:
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15
Ping?
On 10/20/2014 05:59 AM, Juergen Gross wrote:
Hi x86 maintainers,
any reason you seem to ignore this patch series? I think I've replied
to all open issues and sent the patches more than one month ago. Each
patch has a Reviewed-by. Is there something else missing?
Juergen
On 10/13/2014
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross jgr...@suse.com
Reviewed-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Konrad Rzeszutek Wilk konrad.w...@oracle.com
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c
With the dynamical mapping between cache modes and pgprot values it is
now possible to use all cache modes via the Xen hypervisor PAT settings
in a pv domain.
All to be done is to read the PAT configuration MSR and set up the
translation tables accordingly.
Signed-off-by: Juergen Gross jgr
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (3):
x86: Make page cache mode a real type
x86: Enable PAT to use cache mode translation tables
Support Xen pv-domains using PAT
arch/x86/include/asm/cacheflush.h
...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
Reviewed-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Konrad Rzeszutek Wilk konrad.w...@oracle.com
---
arch/x86/include/asm/cacheflush.h | 38 +
arch/x86/include/asm/fb.h | 6 +-
arch/x86/include/asm/io.h
. This could lead to a leaked memory page and to the loss of
some p2m entries.
Avoid the race by using the read compare value for checking the need
of a new p2m leaf.
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/xen/p2m.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
On 10/16/2014 05:50 PM, David Vrabel wrote:
On 16/10/14 07:13, Juergen Gross wrote:
When a new p2m leaf is allocated this leaf is linked into the p2m tree
via cmpxchg. Unfortunately the compare value for checking the success
of the update is read after checking for the need of a new leaf
.
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/xen/p2m.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c
index d1b3da2..b456b04 100644
--- a/arch/x86/xen/p2m.c
+++ b/arch/x86/xen/p2m.c
@@ -532,12 +532,13 @@ static
Hi x86 maintainers,
any reason you seem to ignore this patch series? I think I've replied
to all open issues and sent the patches more than one month ago. Each
patch has a Reviewed-by. Is there something else missing?
Juergen
On 10/13/2014 10:13 AM, Juergen Gross wrote:
The x86 architecture
On 09/04/2014 04:43 PM, Andrew Cooper wrote:
On 04/09/14 15:31, Jan Beulich wrote:
On 04.09.14 at 15:02, andrew.coop...@citrix.com wrote:
On 04/09/14 13:59, David Vrabel wrote:
On 04/09/14 13:38, Juergen Gross wrote:
Direct Xen to place the initial P-M table outside of the initial
mapping
On 09/04/2014 02:59 PM, David Vrabel wrote:
On 04/09/14 13:38, Juergen Gross wrote:
Direct Xen to place the initial P-M table outside of the initial
mapping, as otherwise the 1G (implementation) / 2G (theoretical)
restriction on the size of the initial mapping limits the amount
of memory
On 09/04/2014 04:53 PM, David Vrabel wrote:
On 04/09/14 15:29, Jan Beulich wrote:
On 04.09.14 at 14:52, david.vra...@citrix.com wrote:
On 04/09/14 13:38, Juergen Gross wrote:
--- a/arch/x86/xen/xen-head.S
+++ b/arch/x86/xen/xen-head.S
@@ -124,6 +124,9 @@ NEXT_HYPERCALL(arch_6)
ELFNOTE
On 09/04/2014 02:52 PM, Jan Beulich wrote:
On 04.09.14 at 14:38, jgr...@suse.com.non-mime.internet wrote:
As the KEXEC and DUMPCORE related ELFNOTES are not relevant for the
kernel they are omitted from elfnote.h.
But the defines are still in the patch:
Oops, old header version. I'll
On 09/05/2014 11:05 AM, Andrew Cooper wrote:
On 05/09/14 08:55, Juergen Gross wrote:
On 09/04/2014 04:43 PM, Andrew Cooper wrote:
On 04/09/14 15:31, Jan Beulich wrote:
On 04.09.14 at 15:02, andrew.coop...@citrix.com wrote:
On 04/09/14 13:59, David Vrabel wrote:
On 04/09/14 13:38, Juergen
on non-x86 arch by moving definition of
update_cache_mode_entry() to x86 specific header
Changes since RFC:
- renamed functions and variables as suggested by Toshi Kani
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen
With the dynamical mapping between cache modes and pgprot values it is
now possible to use all cache modes via the Xen hypervisor PAT settings
in a pv domain.
All to be done is to read the PAT configuration MSR and set up the
translation tables accordingly.
Signed-off-by: Juergen Gross jgr
...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/cacheflush.h | 38 +
arch/x86/include/asm/fb.h | 6 +-
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h| 6 +-
arch/x86/include/asm
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross jgr...@suse.com
Reviewed-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c | 8 ++
arch/x86/mm/mm_internal.h
On 08/29/2014 01:21 AM, Toshi Kani wrote:
On Tue, 2014-08-26 at 08:16 +0200, Juergen Gross wrote:
Update the translation tables from cache mode to pgprot values according to
the PAT settings. This enables changing the cache attributes of a PAT index in
just one place without having to change
On 08/29/2014 04:55 PM, Konrad Rzeszutek Wilk wrote:
On Fri, Aug 29, 2014 at 03:44:06PM +0100, Jan Beulich wrote:
On 29.08.14 at 16:27, stefan.ba...@canonical.com wrote:
Sure. Btw, someone also contacted me saying they have the same problem
without
changing the layout but having really big
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (3):
x86: Make page cache mode a real type
x86: Enable PAT to use cache mode translation tables
Support Xen pv-domains using PAT
arch/x86/include/asm/cacheflush.h | 38 ---
arch/x86/include
...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
Reviewed-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/cacheflush.h | 38 +
arch/x86/include/asm/fb.h | 6 +-
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h
With the dynamical mapping between cache modes and pgprot values it is
now possible to use all cache modes via the Xen hypervisor PAT settings
in a pv domain.
All to be done is to read the PAT configuration MSR and set up the
translation tables accordingly.
Signed-off-by: Juergen Gross jgr
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross jgr...@suse.com
Reviewed-by: Toshi Kani toshi.k...@hp.com
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c | 8 ++
arch/x86/mm/mm_internal.h
The pvscsi frontend driver requires the xenbus frontend driver. Reflect
this in Kconfig.
Signed-off-by: Juergen Gross jgr...@suse.com
---
drivers/scsi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 9130df1..ff62dc1 100644
On 09/30/2014 08:32 AM, Chen Gang wrote:
On 9/29/14 21:57, David Vrabel wrote:
On 29/09/14 10:59, Chen Gang wrote:
If no any additional reply within 2 days, I shall send patch v2 for it:
use dev_warn() instead of xenbus_dev_error() and remove 'fail' code block
I think this driver is
modifies xen specific kernel
initialization to be able to switch to the linear mapped p2m list
introduced in the sewcond patch.
Juergen Gross (2):
Xen: Delay remapping memory of pv-domain
Xen: switch to linear virtual mapped sparse p2m list
arch/x86/include/asm/pgtable_types.h | 1 +
arch/x86
memory
initialization time due to it's fixed structure.
A further advantage is the reduction in complexity and code volume as
we don't have to be careful regarding memory restrictions during p2m
updates.
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/xen/page.h | 1 -
arch
: 18:07 - 17:47
User:104:00 - 103:30
Tested on 64 bit dom0 and 32 bit domU.
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/pgtable_types.h | 1 +
arch/x86/include/asm/xen/page.h | 30 +-
arch/x86/mm/pageattr.c | 20 +
arch/x86/xen/mmu.c
On 10/27/2014 04:16 PM, David Vrabel wrote:
On 27/10/14 14:52, Juergen Gross wrote:
Paravirtualized kernels running on Xen use a three level tree for
translation of guest specific physical addresses to machine global
addresses. This p2m tree is used for construction of page table
entries, so
On 10/28/2014 12:53 PM, Andrew Cooper wrote:
On 28/10/14 09:51, Ian Campbell wrote:
On Tue, 2014-10-28 at 06:00 +0100, Juergen Gross wrote:
On 10/27/2014 04:16 PM, David Vrabel wrote:
On 27/10/14 14:52, Juergen Gross wrote:
Paravirtualized kernels running on Xen use a three level tree
On 10/28/2014 01:46 PM, Andrew Cooper wrote:
On 28/10/14 12:44, David Vrabel wrote:
On 28/10/14 12:42, Andrew Cooper wrote:
On 28/10/14 12:39, David Vrabel wrote:
On 28/10/14 12:07, Juergen Gross wrote:
Okay, back to the original question: is the (up to) 64 MB virtual
mapping of the p2m list
On 10/28/2014 01:39 PM, David Vrabel wrote:
On 28/10/14 12:07, Juergen Gross wrote:
Okay, back to the original question: is the (up to) 64 MB virtual
mapping of the p2m list on 32-bit pv domains a problem or not?
I think up-to 64 MiB of vmalloc area is fine. The vmalloc space can
On 10/28/2014 06:34 PM, David Vrabel wrote:
Can these patches be split up? They're hard to review as-is. e.g., the
changes to page allocation look they could be split out.
On 27/10/14 14:52, Juergen Gross wrote:
Early in the boot process the memory layout of a pv-domain is changed
to match
On 10/29/2014 06:30 AM, Juergen Gross wrote:
On 10/28/2014 06:34 PM, David Vrabel wrote:
Can these patches be split up? They're hard to review as-is. e.g., the
changes to page allocation look they could be split out.
On 27/10/14 14:52, Juergen Gross wrote:
Early in the boot process
On 10/29/2014 11:28 AM, Ingo Molnar wrote:
* Thomas Gleixner t...@linutronix.de wrote:
On Mon, 27 Oct 2014, Juergen Gross wrote:
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true
With the dynamical mapping between cache modes and pgprot values it is
now possible to use all cache modes via the Xen hypervisor PAT settings
in a pv domain.
All to be done is to read the PAT configuration MSR and set up the
translation tables accordingly.
Signed-off-by: Juergen Gross jgr
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
drivers/video/fbdev/vermilion/vermilion.c | 6 --
1 file changed, 4 insertions(+), 2 deletions
The PAT bit in the ptes is not moved to the correct position when
copying page protection attributes between entries of different sized
pages. Translate the ptes according to their page size.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
configurations, e.g. supporting Xen.
Signed-off-by: Juergen Gross jgr...@suse.com
Reviewed-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Konrad Rzeszutek Wilk konrad.w...@oracle.com
---
arch/x86/include/asm/pat.h | 1 +
arch/x86/include/asm/pgtable_types.h | 4 +++
arch/x86/mm/init.c
Instead of directly using cache mode bits in the pte switch to usage of
the new cache mode type.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/fb.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/cacheflush.h | 38 --
arch/x86/include/asm/pat.h| 2
Remove no longer used defines from pgtable_types.h as they are not
used any longer.
Switch __PAGE_KERNEL_NOCACHE to use cache mode type instead of pte
bits.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type. This requires to change
io_reserve_memtype() as well.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/pat.h | 2 +-
arch/x86
Dumping page table protection bits is not correct for entries on levels
2 and 3 regarding the PAT bit, which is at a different position as on
level 4.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/mm/dump_pagetables.c | 24
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type. This requires changing some callers of
is_new_memtype_allowed() to be changed as well.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type in the functiuons for modifying page
attributes.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/mm/pageattr.c | 54
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/io.h | 2 +-
arch/x86/include/asm/pat.h | 2 +-
arch/x86/mm/ioremap.c
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type. As those are the main callers of
lookup_memtype(), change this as well.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/mm/pat.c | 32
by moving definition of
update_cache_mode_entry() to x86 specific header
Changes since RFC:
- renamed functions and variables as suggested by Toshi Kani
- corrected cache mode bits for WT and WP
- modified handling of PAT MSR write under Xen as suggested by Jan Beulich
Juergen Gross (17):
x86
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/mm/init_64.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
drivers/video/fbdev/gbefb.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Instead of directly using the cache mode bits in the pte switch to
using the cache mode type.
Signed-off-by: Stefan Bader stefan.ba...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/pci/i386.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch
...@canonical.com
Signed-off-by: Juergen Gross jgr...@suse.com
---
arch/x86/include/asm/pgtable_types.h | 73 +++-
arch/x86/mm/init.c | 29 ++
2 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/pgtable_types.h
b
On 10/31/2014 03:06 PM, Ingo Molnar wrote:
* Juergen Gross jgr...@suse.com wrote:
Changes in V5:
- split up first patch as requested by Ingo Molnar and Thomas Gleixner
- add a helper function in pat_init_cache_modes() as requested by Ingo Molnar
The structure of this series looks great
On 09/17/2014 04:59 PM, Juergen Gross wrote:
Direct Xen to place the initial P-M table outside of the initial
mapping, as otherwise the 1G (implementation) / 2G (theoretical)
restriction on the size of the initial mapping limits the amount
of memory a domain can be handed initially
Hi,
any chance to have this in 3.18?
Juergen
On 09/12/2014 12:35 PM, Juergen Gross wrote:
The x86 architecture offers via the PAT (Page Attribute Table) a way to
specify different caching modes in page table entries. The PAT MSR contains
8 entries each specifying one of 6 possible cache modes
is redirected to UC- per the
default setup in __cachemode2pte_tbl[].
Signed-off-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Juergen Gross jgr...@suse.com
---
arch/x86/mm/pat.c | 64 +
1 file changed, 49 insertions(+), 15 deletions
is also the same as
the BIOS default setup in case the system has PAT but nopat boot
option is specified.
As a result of this change, cache aliasing is checked for all cases
including !pat_enabled.
Signed-off-by: Toshi Kani toshi.k...@hp.com
Reviewed-by: Juergen Gross jgr...@suse.com
---
arch
On 11/19/2014 08:43 PM, Konrad Rzeszutek Wilk wrote:
On Fri, Nov 14, 2014 at 06:14:06PM +0100, Juergen Gross wrote:
On 11/14/2014 05:47 PM, Konrad Rzeszutek Wilk wrote:
On Fri, Nov 14, 2014 at 05:53:19AM +0100, Juergen Gross wrote:
On 11/13/2014 08:56 PM, Konrad Rzeszutek Wilk wrote
On 11/19/2014 09:41 PM, Konrad Rzeszutek Wilk wrote:
On Tue, Nov 11, 2014 at 06:43:38AM +0100, Juergen Gross wrote:
Paravirtualized kernels running on Xen use a three level tree for
translation of guest specific physical addresses to machine global
addresses. This p2m tree is used
On 09/09/2014 07:24 PM, Toshi Kani wrote:
On Mon, 2014-09-08 at 10:01 +0200, Juergen Gross wrote:
At the moment there are a lot of places that handle setting or getting
the page cache mode by treating the pgprot bits equal to the cache mode.
This is only true because there are a lot
On 09/02/2014 09:22 PM, Konrad Rzeszutek Wilk wrote:
On Mon, Sep 01, 2014 at 06:03:06AM +0200, Juergen Gross wrote:
On 08/29/2014 04:55 PM, Konrad Rzeszutek Wilk wrote:
On Fri, Aug 29, 2014 at 03:44:06PM +0100, Jan Beulich wrote:
On 29.08.14 at 16:27, stefan.ba...@canonical.com wrote:
Sure
elfnote.h.
Signed-off-by: Juergen Gross jgr...@suse.com
---
include/xen/interface/elfnote.h | 102 ++-
include/xen/interface/xen.h | 272
2 files changed, 348 insertions(+), 26 deletions(-)
diff --git a/include/xen/interface/elfnote.h b
without mapping it and the
initial p2m list can be mapped by Xen to an arbitrary selected virtual
address. The following patches activate those options and thus remove
the limitations.
Juergen Gross (3):
xen: sync some headers with xen tree
xen: eliminate scalability issues from initrd handling
Size restrictions native kernels wouldn't have resulted from the initrd
getting mapped into the initial mapping. The kernel doesn't really need
the initrd to be mapped, so use infrastructure available in Xen to avoid
the mapping and hence the restriction.
Signed-off-by: Juergen Gross jgr
of the initial mapping after the copy
without having to care about address invalidation.
Signed-off-by: Juergen Gross jgr...@suse.com
Signed-off-by: Jan Beulich jbeul...@suse.com
---
arch/x86/xen/mmu.c | 116 +---
arch/x86/xen/setup.c| 65
than 512 GB in a pv
domain, but this would require a reorganization of the p2m tree built
by the kernel at boot time. As this reorganization would affect the
Xen tools and kexec, too, it is not included in this patch set. This
topic can be addressed later.
Juergen Gross (3):
xen: sync some headers
elfnote.h.
Signed-off-by: Juergen Gross jgr...@suse.com
---
include/xen/interface/elfnote.h | 48 ++-
include/xen/interface/xen.h | 272
2 files changed, 294 insertions(+), 26 deletions(-)
diff --git a/include/xen/interface/elfnote.h b/include/xen
of the initial mapping after the copy
without having to care about address invalidation.
Signed-off-by: Juergen Gross jgr...@suse.com
Signed-off-by: Jan Beulich jbeul...@suse.com
---
arch/x86/xen/mmu.c | 115 +---
arch/x86/xen/setup.c| 65
Size restrictions native kernels wouldn't have resulted from the initrd
getting mapped into the initial mapping. The kernel doesn't really need
the initrd to be mapped, so use infrastructure available in Xen to avoid
the mapping and hence the restriction.
Signed-off-by: Juergen Gross jgr
On 09/17/2014 03:45 PM, David Vrabel wrote:
On 17/09/14 05:12, Juergen Gross wrote:
Size restrictions native kernels wouldn't have resulted from the initrd
getting mapped into the initial mapping. The kernel doesn't really need
the initrd to be mapped, so use infrastructure available in Xen
On 09/17/2014 04:07 PM, David Vrabel wrote:
On 17/09/14 05:12, Juergen Gross wrote:
Direct Xen to place the initial P-M table outside of the initial
mapping, as otherwise the 1G (implementation) / 2G (theoretical)
restriction on the size of the initial mapping limits the amount
of memory
On 09/17/2014 04:42 PM, David Vrabel wrote:
On 17/09/14 15:20, Juergen Gross wrote:
On 09/17/2014 04:07 PM, David Vrabel wrote:
Are you missing a ClearPagePinned(..) here?
Probably, yes.
Jan pointed out that this is not needed.
@@ -1529,6 +1604,22 @@ static pte_t __init mask_rw_pte
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