[PATCH v6 0/6] perf: Support for ARM DynamIQ Shared Unit

This series adds support for the PMU in ARM DynamIQ Shared Unit (DSU). The DSU integrates one or more cores with an L3 memory system, control logic, and external interfaces to form a multicore cluster. The PMU allows counting the various events related to L3, SCU etc, using 32bit independent

[PATCH v6 0/6] perf: Support for ARM DynamIQ Shared Unit

This series adds support for the PMU in ARM DynamIQ Shared Unit (DSU). The DSU integrates one or more cores with an L3 memory system, control logic, and external interfaces to form a multicore cluster. The PMU allows counting the various events related to L3, SCU etc, using 32bit independent