On 23/06/17 02:37, Jan Lübbe wrote:
> Hi Chris,
>
> On Fr, 2017-06-09 at 15:14 +0200, Jan Lübbe wrote:
>>> +static void mvebu_init_csrows(struct mem_ctl_info *mci,
>>> + struct mvebu_mc_pdata *pdata)
>> [...]
>>> + devtype = (ctl >> 20) & 0x3;
>>> + switch
On 23/06/17 02:37, Jan Lübbe wrote:
> Hi Chris,
>
> On Fr, 2017-06-09 at 15:14 +0200, Jan Lübbe wrote:
>>> +static void mvebu_init_csrows(struct mem_ctl_info *mci,
>>> + struct mvebu_mc_pdata *pdata)
>> [...]
>>> + devtype = (ctl >> 20) & 0x3;
>>> + switch
Hi Chris,
On Fr, 2017-06-09 at 15:14 +0200, Jan Lübbe wrote:
> > +static void mvebu_init_csrows(struct mem_ctl_info *mci,
> > + struct mvebu_mc_pdata *pdata)
> [...]
> > + devtype = (ctl >> 20) & 0x3;
> > + switch (devtype) {
> > + case 0x0:
> > +
Hi Chris,
On Fr, 2017-06-09 at 15:14 +0200, Jan Lübbe wrote:
> > +static void mvebu_init_csrows(struct mem_ctl_info *mci,
> > + struct mvebu_mc_pdata *pdata)
> [...]
> > + devtype = (ctl >> 20) & 0x3;
> > + switch (devtype) {
> > + case 0x0:
> > +
On 10/06/17 01:19, Jan Lübbe wrote:
>> +
>> +if (edac_op_state == EDAC_OPSTATE_INT) {
>> +/* acquire interrupt that reports errors */
>> +pdata->irq = platform_get_irq(pdev, 0);
>> +res = devm_request_irq(>dev,
>> +
On 10/06/17 01:19, Jan Lübbe wrote:
>> +
>> +if (edac_op_state == EDAC_OPSTATE_INT) {
>> +/* acquire interrupt that reports errors */
>> +pdata->irq = platform_get_irq(pdev, 0);
>> +res = devm_request_irq(>dev,
>> +
Hi Chris!
On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote:
> This adds an EDAC driver for the memory controller and L2 cache used on
> a number of Marvell Armada SoCs.
Why have two separate drivers in the same file and enabled with the same
Kconfig option?
[...]
> +static void
Hi Chris!
On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote:
> This adds an EDAC driver for the memory controller and L2 cache used on
> a number of Marvell Armada SoCs.
Why have two separate drivers in the same file and enabled with the same
Kconfig option?
[...]
> +static void
On Thu, Jun 08, 2017 at 04:11:21PM +1200, Chris Packham wrote:
> This adds an EDAC driver for the memory controller and L2 cache used on
> a number of Marvell Armada SoCs.
>
> Signed-off-by: Chris Packham
> Cc: linux-arm-ker...@lists.infradead.org
> ---
>
On Thu, Jun 08, 2017 at 04:11:21PM +1200, Chris Packham wrote:
> This adds an EDAC driver for the memory controller and L2 cache used on
> a number of Marvell Armada SoCs.
>
> Signed-off-by: Chris Packham
> Cc: linux-arm-ker...@lists.infradead.org
> ---
> drivers/edac/Kconfig | 7 +
>
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