From: Shunqian Zheng <zhen...@rock-chips.com>

It's a Designware MIPI D-PHY, used for ISP0 in rk3399.

Signed-off-by: Shunqian Zheng <zhen...@rock-chips.com>
Signed-off-by: Jacob Chen <jacob2.c...@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 66a912fab5dd..8ef321f03010 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1292,6 +1292,16 @@
                        status = "disabled";
                };
 
+               mipi_dphy_rx0: mipi-dphy-rx0 {
+                       compatible = "rockchip,rk3399-mipi-dphy";
+                       clocks = <&cru SCLK_MIPIDPHY_REF>,
+                               <&cru SCLK_DPHY_RX0_CFG>,
+                               <&cru PCLK_VIO_GRF>;
+                       clock-names = "dphy-ref", "dphy-cfg", "grf";
+                       power-domains = <&power RK3399_PD_VIO>;
+                       status = "disabled";
+               };
+
                u2phy0: usb2-phy@e450 {
                        compatible = "rockchip,rk3399-usb2phy";
                        reg = <0xe450 0x10>;
-- 
2.15.1

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