Re: [PATCH v4 2/2] v4l: cadence: Add Cadence MIPI-CSI2 RX driver

2017-10-13 Thread Maxime Ripard
Hi Benoit, On Wed, Oct 11, 2017 at 01:22:59PM +, Benoit Parrot wrote: > Maxime Ripard wrote on Wed [2017-Oct-11 > 11:24:09 +0200]: > > On Fri, Sep 29, 2017 at 05:27:09PM +, Benoit Parrot wrote: > > > > +static int csi2rx_get_resources(struct csi2rx_priv

Re: [PATCH v4 2/2] v4l: cadence: Add Cadence MIPI-CSI2 RX driver

2017-10-11 Thread Benoit Parrot
Hi Maxime, Maxime Ripard wrote on Wed [2017-Oct-11 11:24:09 +0200]: > Hi Benoit, > > On Fri, Sep 29, 2017 at 05:27:09PM +, Benoit Parrot wrote: > > > +static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, > > > + struct

Re: [PATCH v4 2/2] v4l: cadence: Add Cadence MIPI-CSI2 RX driver

2017-10-11 Thread Maxime Ripard
Hi Benoit, On Fri, Sep 29, 2017 at 05:27:09PM +, Benoit Parrot wrote: > > +static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, > > + struct platform_device *pdev) > > +{ > > + struct resource *res; > > + unsigned char i; > > + u32 reg; > > + > > + res

Re: [PATCH v4 2/2] v4l: cadence: Add Cadence MIPI-CSI2 RX driver

2017-09-29 Thread Benoit Parrot
Maxime Ripard wrote on Fri [2017-Sep-22 12:08:23 +0200]: > The Cadence CSI-2 RX Controller is an hardware block meant to be used as a > bridge between a CSI-2 bus and pixel grabbers. > > It supports operating with internal or external D-PHY, with up to 4 lanes,

[PATCH v4 2/2] v4l: cadence: Add Cadence MIPI-CSI2 RX driver

2017-09-22 Thread Maxime Ripard
The Cadence CSI-2 RX Controller is an hardware block meant to be used as a bridge between a CSI-2 bus and pixel grabbers. It supports operating with internal or external D-PHY, with up to 4 lanes, or without any D-PHY. The current code only supports the former case. It also support dynamic