);
Overall, I'd like this to be split into several patches:
- One for the bindings documentation
- One for the driver
- One that adds the controller to the DT
- One that adds the pin muxing options
- and finally one that enables the IR receiver on the boards.
Thanks!
Maxime
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. The names
being generic, if there ever comes a time where you have a second
controller, you don't have to do anything confusing or inconsistent.
Thanks!
Maxime
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to call clk_set_rate and not
to expect the clock to run at the proper frequency.
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-base + SUNXI_IR_CTL_REG);
+
+ writel(tmp | 0x3, ir-base + SUNXI_IR_CTL_REG);
We don't like magic numbers too much. Please add some #define for
those.
Thanks!
Maxime
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: ir@01c21c00 {
... and this one are indented a tab too far.
Maxime
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, ir;
+ interrupts = 0 6 4;
+ reg = 0x01C21c00 0x40;
You're mixing upper and lower case letters here, please make it lower
case.
Thanks!
Maxime
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= rc_allocate_device();
+
You can drop the extra line here
Maxime
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if you want to keep it as a
function.
In both cases, you don't want your function to be declared in the
middle of your defines.
Thanks,
Maxime
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+
I told you numerous times already that I wanted this patch to be split
into at least three of them:
- One to add the device to the DTSI.
- One to add the pins
- and one to enable the devices in the DTS.
Please address this comment.
Maxime
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= sunxi_ir_match,
+ },
+};
+
+module_platform_driver(sunxi_ir_driver);
+
+MODULE_DESCRIPTION(Allwinner sunXi IR controller driver);
+MODULE_AUTHOR(Alexsey Shestacov wingr...@linux-sunxi.org);
+MODULE_LICENSE(GPL);
--
1.9.3
Thanks!
Maxime
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, but it doesn't apply, since the above node
doesn't exist. Please rebase on top of v3.16-rc1 and resend the patch.
Maxime
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Hi,
On Mon, Jun 09, 2014 at 12:08:11AM +0600, Alexander Bersenev wrote:
This patch adds pins for two IR controllers on A20
Signed-off-by: Alexander Bersenev b...@hackerdom.ru
Signed-off-by: Alexsey Shestacov wingr...@linux-sunxi.org
Applied, thanks.
Maxime
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wingr...@linux-sunxi.org
Applied, thanks.
Maxime
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On Sat, Jun 21, 2014 at 05:04:05PM +0600, Alexander Bersenev wrote:
This patch adds records for two IR controllers on A20
Signed-off-by: Alexander Bersenev b...@hackerdom.ru
Signed-off-by: Alexsey Shestacov wingr...@linux-sunxi.org
Applied, thanks.
Maxime
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On Mon, Jun 23, 2014 at 01:08:24PM -0700, Александр Берсенев wrote:
Thanks,
Should I send applied patches in the further versions of this patch set?
No, you don't have to.
Maxime
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Carvalho Chehab mche...@osg.samsung.com
I think merging it through your tree would be just fine.
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Maxime
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, of_iomap(node, 0));
As of_iomap can fail, I'd rather check the returned value before
calling sunxi_factors_register.
I know it wasn't done before, but it's the right thing to do, as it
would lead to an instant crash if that fails.
Thanks!
Maxime
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will
be the same.
The only thing we need to pay attention to is how client drivers
react when they cannot grab their clock. They should return
-EPROBE_DEFER, but that remains to be checked.
Maxime
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is specified in dt.
Signed-off-by: Hans de Goede hdego...@redhat.com
As this is meant to be merged via some other tree:
Acked-by: Mauro Carvalho Chehab mche...@osg.samsung.com
Again, I think it'll be perfectly fine in your tree :)
Once the documentation is updated,
Acked-by: Maxime Ripard
On Fri, Nov 21, 2014 at 09:42:09AM +0100, Hans de Goede wrote:
Hi,
On 11/21/2014 09:26 AM, Maxime Ripard wrote:
Hi Mauro,
On Thu, Nov 20, 2014 at 02:28:56PM -0200, Mauro Carvalho Chehab wrote:
Em Thu, 20 Nov 2014 16:55:24 +0100
Hans de Goede hdego...@redhat.com escreveu:
Add
On Fri, Nov 21, 2014 at 09:44:51AM +0100, Hans de Goede wrote:
Hi,
On 11/21/2014 09:35 AM, Maxime Ripard wrote:
Hi Hans,
On Thu, Nov 20, 2014 at 04:55:20PM +0100, Hans de Goede wrote:
Before this commit sunxi_factors_register uses of_iomap(node, 0) to get
the clk registers
On Fri, Nov 21, 2014 at 11:13:17AM +0100, Hans de Goede wrote:
Hi,
On 11/21/2014 10:59 AM, Maxime Ripard wrote:
On Fri, Nov 21, 2014 at 09:42:09AM +0100, Hans de Goede wrote:
Hi,
On 11/21/2014 09:26 AM, Maxime Ripard wrote:
Hi Mauro,
On Thu, Nov 20, 2014 at 02:28:56PM -0200
On Fri, Nov 21, 2014 at 10:13:10AM +0100, Hans de Goede wrote:
Hi,
On 11/21/2014 09:49 AM, Maxime Ripard wrote:
Hi,
On Thu, Nov 20, 2014 at 04:55:22PM +0100, Hans de Goede wrote:
Add a driver for mod0 clocks found in the prcm. Currently there is only
one mod0 clocks in the prcm
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Hi,
On Tue, Nov 25, 2014 at 09:29:21AM +0100, Hans de Goede wrote:
Hi,
On 11/24/2014 11:03 PM, Maxime Ripard wrote:
On Fri, Nov 21, 2014 at 10:13:10AM +0100, Hans de Goede wrote:
Hi,
On 11/21/2014 09:49 AM, Maxime Ripard wrote:
Hi,
On Thu, Nov 20, 2014 at 04:55:22PM +0100, Hans de
On Sun, Nov 23, 2014 at 02:38:14PM +0100, Hans de Goede wrote:
Add pinmux settings for the ir receive pin of the A31.
Signed-off-by: Hans de Goede hdego...@redhat.com
Applied, thanks!
Maxime
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On Thu, Nov 27, 2014 at 09:41:09AM +0100, Hans de Goede wrote:
Hi,
On 11/26/2014 10:13 PM, Maxime Ripard wrote:
Hi,
On Tue, Nov 25, 2014 at 09:29:21AM +0100, Hans de Goede wrote:
Hi,
On 11/24/2014 11:03 PM, Maxime Ripard wrote:
On Fri, Nov 21, 2014 at 10:13:10AM +0100, Hans de Goede
it
have a compatible of its own, but still needs to access some of the
PRCM registers?
Maxime
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On Thu, Nov 27, 2014 at 05:40:56PM +0100, Boris Brezillon wrote:
Hi,
On Wed, 26 Nov 2014 22:13:18 +0100
Maxime Ripard maxime.rip...@free-electrons.com wrote:
[...]
I remember someone (Chen-Yu? Boris?) saying that the 1wire clock was
not really a mod0 clk. From what I could gather
Hi,
On Fri, Nov 28, 2014 at 02:37:14PM +0100, Hans de Goede wrote:
Hi,
On 11/27/2014 08:05 PM, Maxime Ripard wrote:
Hi,
On Thu, Nov 27, 2014 at 11:10:51AM +0100, Hans de Goede wrote:
Hi,
On 11/27/2014 10:28 AM, Chen-Yu Tsai wrote:
Hi,
On Thu, Nov 27, 2014 at 4:41 PM, Hans de Goede
On Wed, Dec 03, 2014 at 10:49:20AM +0100, Hans de Goede wrote:
Hi,
On 12/02/2014 04:45 PM, Maxime Ripard wrote:
Ok, so thinking more about this, I'm still convinced that the MFD
framework is only getting in the way here.
You still haven't said of what exactly it's getting in the way
On Mon, Dec 08, 2014 at 09:19:02AM +0100, Hans de Goede wrote:
Hi,
On 07-12-14 19:08, Maxime Ripard wrote:
On Wed, Dec 03, 2014 at 10:49:20AM +0100, Hans de Goede wrote:
snip
So it should not have a simple-bus compatible either, and as such we cannot
simply change the mod0 driver from
if a reset controller is specified in dt.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Mauro Carvalho Chehab mche...@osg.samsung.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/media/sunxi-ir.txt | 2 ++
drivers/media/rc
On Wed, Dec 17, 2014 at 06:18:20PM +0100, Hans de Goede wrote:
Add a node for the ir receiver found on the A31.
Signed-off-by: Hans de Goede hdego...@redhat.com
Applied, thanks!
Maxime
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On Wed, Dec 17, 2014 at 06:18:22PM +0100, Hans de Goede wrote:
The Mele M9 has an ir receiver, enable it.
Signed-off-by: Hans de Goede hdego...@redhat.com
Applied, thanks!
Maxime
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Applied, thanks!
Maxime
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, 0);
- if (!reg) {
- pr_err(Could not get registers for mod0-clk: %s\n,
-node-name);
+ if (!reg)
return;
- }
A comment here would be nice to mention that this is intentional.
It looks good otherwise, thanks!
Maxime
--
Maxime
On Wed, Dec 17, 2014 at 06:18:19PM +0100, Hans de Goede wrote:
Add an ir_clk sub-node to the prcm node.
Signed-off-by: Hans de Goede hdego...@redhat.com
Applied, thanks!
Maxime
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users, but could you repost
these patches with this ?
Thanks,
Maxime
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On Wed, Dec 17, 2014 at 06:18:12PM +0100, Hans de Goede wrote:
While working on pinctrl for the A31s, I noticed that function 4 of
PA15 - PA18 was missing, add these.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Maxime
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-a31.c for the second one, right?
with the missing pins and functions removed.
Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the
prcm pins are identical between the A31 and the A31s.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Maxime Ripard maxime.rip
On Sat, Dec 20, 2014 at 11:24:55AM +0100, Hans de Goede wrote:
Hi,
On 19-12-14 19:34, Maxime Ripard wrote:
On Wed, Dec 17, 2014 at 06:18:23PM +0100, Hans de Goede wrote:
Add a dtsi file for A31s based boards.
Since the A31s is the same die as the A31 in a different package, this dtsi
stuff to moving label references, can you fix this up, or
do you want me to do a follow up patch ?
Note that having this fixed is a pre-req for the csq-cs908 dts patch.
Ah, right. I edited your previous patch to add the label.
Thanks!
Maxime
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Hi,
On Mon, Dec 22, 2014 at 02:46:12PM +0100, Hans de Goede wrote:
On 21-12-14 23:39, Maxime Ripard wrote:
On Sat, Dec 20, 2014 at 11:24:55AM +0100, Hans de Goede wrote:
Hi,
On 19-12-14 19:34, Maxime Ripard wrote:
On Wed, Dec 17, 2014 at 06:18:23PM +0100, Hans de Goede wrote:
Add a dtsi
ze it correctly.
>
> Fixes: b4e3e59fb59c ("[media] rc: add sunxi-ir driver")
> Signed-off-by: Chen-Yu Tsai <w...@csie.org>
You should probably Cc stable on this one.
Thanks!
Maxime
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h
On Mon, Mar 20, 2017 at 11:22:02AM +0100, Maxime Ripard wrote:
> Hi Mauro,
>
> On Tue, Mar 07, 2017 at 02:39:28PM +0100, Maxime Ripard wrote:
> > The Makefile was a free for all without a clear order defined. Sort all the
> > options based on the Kconfig symbol.
> >
Hi Mauro,
On Tue, Mar 07, 2017 at 02:39:28PM +0100, Maxime Ripard wrote:
> The Makefile was a free for all without a clear order defined. Sort all the
> options based on the Kconfig symbol.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Any news o
The Makefiles were a free for all without a clear order defined. Sort all the
options based on the Kconfig symbol.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Hi Mauro,
Here is my makefile ordering patch again, this time with all the Makefiles
in drivers
On Wed, Apr 19, 2017 at 08:15:45AM -0300, Mauro Carvalho Chehab wrote:
> Em Thu, 6 Apr 2017 16:40:51 +0200
> Maxime Ripard <maxime.rip...@free-electrons.com> escreveu:
>
> > The Makefiles were a free for all without a clear order defined. Sort all
> > the
> > op
The Makefile was a free for all without a clear order defined. Sort all the
options based on the Kconfig symbol.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
drivers/media/platform/Makefile | 89 ++---
1 file changed, 31 inse
Hi Rob,
Sorry for the slow answer.
On Fri, Jul 07, 2017 at 11:21:05AM -0500, Rob Herring wrote:
> On Mon, Jul 03, 2017 at 02:40:22PM +0200, Maxime Ripard wrote:
> > The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to
> > 4 CSI-2 lanes, and can route the fr
tory and
> doing a continuous scp to create network traffic.
>
> This patch series is based on top of the mainline kernel as of
> yesterday (so with all the sun4i and cec patches for 4.13 merged).
For the whole serie:
Reviewed-by: Maxime Ripard <maxime.rip...@free-electrons.com>
>
Hi,
On Tue, Jul 11, 2017 at 11:06:52PM +0200, Hans Verkuil wrote:
> On 11/07/17 22:39, Maxime Ripard wrote:
> > On Tue, Jul 11, 2017 at 08:30:33AM +0200, Hans Verkuil wrote:
> >> From: Hans Verkuil <hans.verk...@cisco.com>
> >>
> >> This patch series adds
mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
d
The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to
4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on
the hardware implementation.
It can operate with an external D-PHY, an internal one or no D-PHY at all
in some configurations.
Signed-off-by: Maxime
async: add subnotifier
registration for subdevices" from Niklas Söderlund.
Let me know what you think!
Maxime
Changes from v1:
- Amended the DT bindings as suggested by Rob
- Rebase on top of 4.13-rc1 and latest Niklas' serie iteration
Maxime Ripard (2):
dt-bindings: media: Add Cadence MI
in the futrue. But the sunxi_video.c and sunxi_csi.c are common.
>
> I'd say it is a premature optimization. The file separation is fine, IMO, but
> the added csi_ops indirection makes the code less readable. Someone with
> access to R40 hardware with CSI setup would be a better pos
calibration data), in case it differs from the
> + sensor node.
Wouldn't it makes sense (especially if you want to provide user space
access) to reuse what nvmem provides for this?
Maxime
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of this magic number? Is it platform dependent? Are there
> other devices doing DMA that need this adjustment?
This is the RAM base address in most (but not all) Allwinner
SoCs. You'll want to use PHYS_OFFSET instead.
Maxime
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Hi Sakari,
On Wed, Jul 19, 2017 at 12:21:06PM +0300, Sakari Ailus wrote:
> On Wed, Jul 19, 2017 at 09:52:55AM +0200, Maxime Ripard wrote:
> > Hi Sakari,
> >
> > On Wed, Jun 14, 2017 at 12:47:14PM +0300, Sakari Ailus wrote:
> > > Many camera sensor devices cont
rything else happens
>in the v4l2-async framework. This leaves the interface in a good
>position for possible changes in v4l2-async.
>
> This is tested on Renesas H3 and M3-W together with the Renesas CSI-2
> and VIN Gen3 driver (posted separately). It is based on top of t
On Tue, Jul 04, 2017 at 03:25:45PM +0800, Yong wrote:
> On Mon, 3 Jul 2017 13:25:21 +0200
> Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
>
> > Hi,
> >
> > On Mon, Jul 03, 2017 at 06:59:52PM +0800, Yong wrote:
> > > > > + se
the
A23, A33, A80, A83T, H3, and probably the H5 and A64.
Maxime
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mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
d
ifier
registration for subdevices" from Niklas Söderlund.
Let me know what you think!
Maxime
Maxime Ripard (2):
dt-bindings: media: Add Cadence MIPI-CSI2RX Device Tree bindings
v4l: cadence: Add Cadence MIPI-CSI2 RX driver
.../devicetree/bindings/media/cdns-csi2rx.txt | 87
dri
The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to
4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on
the hardware implementation.
It can operate with an external D-PHY, an internal one or no D-PHY at all
in some configurations.
Signed-off-by: Maxime
ing? (or did you choose to ignore it for now?)
> + return IRQ_HANDLED;
> + }
> +
> + if (status & CSI_CH_INT_STA_FD_PD) {
> + sun6i_video_frame_done(>csi.video);
> + }
> +
> + regmap_write(regmap, CSI_CH_INT_STA_REG, status);
Isn't it redundant with the one you did in the condition a bit above?
You should also check that your device indeed generated an
interrupt. In the occurence of a spourious interrupt, your code will
return IRQ_HANDLED, which is the wrong thing to do.
I think you should reverse your logic a bit here to make this
easier. You should just check that your status flags are indeed set,
and if not just bail out and return IRQ_NONE.
And if they are, go on with treating your interrupt.
> +
> + return IRQ_HANDLED;
> +}
> +
> +static const struct regmap_config sun6i_csi_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x1000,
> +};
> +
> +static int sun6i_csi_resource_request(struct sun6i_csi_dev *sdev,
> + struct platform_device *pdev)
> +{
> + struct resource *res;
> + void __iomem *io_base;
> + int ret;
> + int irq;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + io_base = devm_ioremap_resource(>dev, res);
> + if (IS_ERR(io_base))
> + return PTR_ERR(io_base);
> +
> + sdev->regmap = devm_regmap_init_mmio(>dev, io_base,
> + _csi_regmap_config);
> + if (IS_ERR(sdev->regmap)) {
> + dev_err(>dev, "Failed to init register map\n");
> + return PTR_ERR(sdev->regmap);
> + }
> +
> + sdev->clk_ahb = devm_clk_get(>dev, "ahb");
> + if (IS_ERR(sdev->clk_ahb)) {
> + dev_err(>dev, "Unable to acquire ahb clock\n");
> + return PTR_ERR(sdev->clk_ahb);
> + }
> + sdev->clk_mod = devm_clk_get(>dev, "mod");
> + if (IS_ERR(sdev->clk_mod)) {
> + dev_err(>dev, "Unable to acquire csi clock\n");
> + return PTR_ERR(sdev->clk_mod);
> + }
> +
> + sdev->clk_ram = devm_clk_get(>dev, "ram");
> + if (IS_ERR(sdev->clk_ram)) {
> + dev_err(>dev, "Unable to acquire dram-csi clock\n");
> + return PTR_ERR(sdev->clk_ram);
> + }
> +
> + sdev->rstc_ahb = devm_reset_control_get_optional_shared(>dev,
> NULL);
It is not optional, the reset line is always going to be there (at
least on the SoCs that have been out so far), and a missing reset line
in the DT must be reported as an error, since the device will not be
able to operate properly.
Thanks!
Maxime
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gt; + - reg: base address and size of the memory-mapped region.
> + - interrupts: interrupt associated to this IP
> + - clocks: phandles to the clocks feeding the CSI
> +* ahb: the CSI interface clock
We've been bad at this, but we're trying to have the same clock name
here across all dev
uld also check that your device indeed generated an
> > interrupt. In the occurence of a spourious interrupt, your code will
> > return IRQ_HANDLED, which is the wrong thing to do.
> >
> > I think you should reverse your logic a bit here to make this
> > easier. You should just check that your status flags are indeed set,
> > and if not just bail out and return IRQ_NONE.
> >
> > And if they are, go on with treating your interrupt.
>
> OK. I will add check for status flags.
> BTW, how can a spurious interrupt occurred?
Usually it's either through some interference, or some poorly designed
controller. This is unlikely, but it's something you should take into
account.
Thanks!
Maxime
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ing the driver from probing properly, etc), even though
that component might not be essential.
This is how DRM operates, and you sometimes end up in some very dumb
situations where you wait for say, the DSI controller to probe, while
you only care about HDMI in your system.
But this seems to be on
p needing but
> since here we are only dealing with one, why not just make it a
> member of the struct csi2rx_priv object.
As far as I know, only the notifier will use that array. The notifier
will be removed before that array is de-allocated, and the user-space
never has access to it, so I'm not sure the same issue arises here.
Maxime
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the channel(s).
> Will we be adding a method to select/filter specific data type? For
> instance if we only want to grab YUV data in one stream and only
> RGB24 in another. Of course that would not be possible here as is...
Ah, right, I forgot about that. I've actually started that di
Hi Hans,
On Fri, Sep 08, 2017 at 10:59:44AM +, Hans Verkuil wrote:
> Hi Maxime,
>
> On 07/18/17 18:29, Maxime Ripard wrote:
> > Hi,
> >
> > On Tue, Jul 11, 2017 at 11:06:52PM +0200, Hans Verkuil wrote:
> >> On 11/07/17 22:39, Maxime Ripard wrote:
>
g
Changes from v1:
- Amended the DT bindings as suggested by Rob
- Rebase on top of 4.13-rc1 and latest Niklas' serie iteration
Maxime Ripard (2):
dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings
v4l: cadence: Add Cadence MIPI-CSI2 RX driver
.../devicetree/bindings/
<r...@kernel.org>
Acked-by: Benoit Parrot <bpar...@ti.com>
Acked-by: Sakari Ailus <sakari.ai...@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
.../devicetree/
mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
d
On Thu, Sep 21, 2017 at 09:19:43PM +, Hans Verkuil wrote:
> On 21/09/17 22:37, Maxime Ripard wrote:
> > Hi Hans,
> >
> > On Fri, Sep 08, 2017 at 10:59:44AM +, Hans Verkuil wrote:
> >> Hi Maxime,
> >>
> >> On 07/18/17 18:29, Maxime Ripard w
channel input on the pixel interface can be directly
mapped to CSI2, the datatype input is actually a selection signal (3-bits)
mapping to a table of up to 8 preconfigured datatypes/formats (programmed
at start-up)
The block supports up to 8 input datatypes.
Signed-off-by: Maxime Ripard <maxime.
The Cadence MIPI-CSI2 RX controller is a CSI2 bridge that supports up to 4
video streams and can output on up to 4 CSI-2 lanes, depending on the
hardware implementation.
It can operate with an external D-PHY, an internal one or no D-PHY at all
in some configurations.
Signed-off-by: Maxime Ripard
evice notifier support, N9 flash DTS" by
Sakari Ailus
Let me know what you think!
Maxime
Maxime Ripard (2):
dt-bindings: media: Add Cadence MIPI-CSI2 TX Device Tree bindings
v4l: cadence: Add Cadence MIPI-CSI2 TX driver
.../devicetree/bindings/media/cdns,csi2tx.txt | 97 +
dri
Hi Sakari,
On Fri, Sep 22, 2017 at 12:01:06PM +, Sakari Ailus wrote:
> On Fri, Sep 22, 2017 at 01:47:02PM +0200, Maxime Ripard wrote:
> > The Cadence MIPI-CSI2 RX controller is a CSI2 bridge that supports up to 4
>
> Should this be TX?
>
> I was just thinking what does
Hi Sakari,
On Fri, Sep 22, 2017 at 11:35:23AM +, Sakari Ailus wrote:
> Hi Maxime,
>
> On Fri, Sep 22, 2017 at 12:08:22PM +0200, Maxime Ripard wrote:
> > The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to
> > 4 CSI-2 lanes, and can route the fram
gt; > +{
> > + /*
> > +* Let the last user turn off the lights
> > +*/
> > + if (!atomic_dec_and_test(>count))
> > + return 0;
> > +
> > + /* FIXME: Disable the IP here */
>
> Shouldn't this be addressed?
Yes, but it's still unclear how at the moment. It will of course
eventually be implemented.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Hi Benoit,
On Wed, Oct 11, 2017 at 01:22:59PM +, Benoit Parrot wrote:
> Maxime Ripard <maxime.rip...@free-electrons.com> wrote on Wed [2017-Oct-11
> 11:24:09 +0200]:
> > On Fri, Sep 29, 2017 at 05:27:09PM +, Benoit Parrot wrote:
> > > > +static int csi2rx_ge
or it just doesn't not match the comment
> above, where it is says that the DT is set to the stream ID...
As explained in the cover letter, you actually have two datatypes, the
input one that is in the 0-8 range, which is then mapped through that
register to a MIPI-CSI2 datatype. The comment refe
}
> > +
> > + for (i = 0; i < csi2rx->max_streams; i++) {
> > + char clk_name[16];
> > +
> > + snprintf(clk_name, sizeof(clk_name), "pixel_if%u_clk", i);
> > + csi2rx->pixel_clk[i] = devm_clk_get(>dev, clk_name);
> > + if (IS_ERR(csi2rx->pixel_clk[i])) {
> > + dev_err(>dev, "Couldn't get clock %s\n",
> > clk_name);
> > + return PTR_ERR(csi2rx->pixel_clk[i]);
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int csi2rx_parse_dt(struct csi2rx_priv *csi2rx)
> > +{
> > + struct v4l2_fwnode_endpoint v4l2_ep;
> > + struct device_node *ep, *remote;
>
> *remote is now unused.
It's fixed, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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t
enables the CSI2-RX which in turn enables CSI2-TX. The pattern
generator is enabled all the time.
> We have a few corner cases in V4L2 for such devices in graph parsing and
> stream control. The parsing of the device's fwnode graph endpoints are what
> the device can do, but it doesn't k
th the video stream itself, but that
can be detected after the block has been enabled.
> > + csi2tx->lanes = csi2tx_get_num_lanes(>dev);
> > + if (csi2tx->lanes < 0) {
> > + dev_err(>dev, "Invalid number of lanes, bailing out.\n");
> > + ret = csi2tx->lanes;
> > + goto err_free_priv;
> > + }
>
> csi2tx->lanes is unsigned so it will never be negative.
Ah, right, I'll change that.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Hi Baruch,
On Sun, Jul 30, 2017 at 09:08:01AM +0300, Baruch Siach wrote:
> On Fri, Jul 28, 2017 at 06:02:33PM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > Thanks for the second iteration!
> >
> > On Thu, Jul 27, 2017 at 01:01:35PM +0800, Yong Deng wrote:
>
Hi Laurent,
Thanks a lot for reviewing those patches.
On Mon, Aug 07, 2017 at 11:18:03PM +0300, Laurent Pinchart wrote:
> Hi Maxime,
>
> Thank you for the patch.
>
> On Thursday 20 Jul 2017 11:23:01 Maxime Ripard wrote:
> > The Cadence MIPI-CSI2 RX controller is a CSI2RX
; > Shouldn't we return an error code then? The names of these flags could
> > be better too.
>
> Then, where and how to deal with the error coce.
If you want to deal with FIFO overflow, I'm not sure you have anything
to do. It means, you've been to slow to queue buffers, so I guess
stopping the pipeline until more buffers are queued would make
sense. And we should probably increase the sequence number while doing
so to notify the userspace that some frames were lost.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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several engines,
each one connected to a stream.
One way to work around that could be to add some reference counting in
the start and stop functions, and keep enabling all the outputs.
This wouldn't solve the underlying issue that all the stream would be
enabled and we don't really have a way to tel
want to anticipate the future binding for devices with
multiple channels?
> >
> > If so, you should take a look at the last iteration of the
> > subnotifiers rework by Nikas Söderlund (v4l2-async: add subnotifier
> > registration for subdevices).
> >
> > It allow
e.
However, the PHY bit is set only when there's an internal D-PHY, which
means we have basically three cases:
- No D-PHY at all, D-PHY presence bit not set
- Internal D-PHY, D-PHY presence bit set
- External D-PHY, D-PHY presence bit not set
I guess that solves our discussion about whe
can be accessed
> from userspace (in this case because it embeds the subdev structure,
> accessible at least through the subdevs ioctls). This is incompatible with
> proper unplug handling. There are many other issues that we will need to
> solve
> in the V4L2 core to handling unplugging properly, but let's not add a new one.
What's wrong with kzalloc in such a case? As far as I know, the
userspace can access such a memory, as long as you use copy_to_user,
right? Or is it because of the life-cycle of the allocation that would
be gone while the userspace might not be yet? I'm not sure what would
be a proper fix for it though.
Thanks for your review!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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suggested by Rob
- Rebase on top of 4.13-rc1 and latest Niklas' serie iteration
Maxime Ripard (2):
dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings
v4l: cadence: Add Cadence MIPI-CSI2 RX driver
.../devicetree/bindings/media/cdns-csi2rx.txt | 98
drivers/medi
mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
drivers/media/platform/Kconfig | 1 +
drivers/media/platform/Makefile | 2 +
d
<r...@kernel.org>
Acked-by: Benoit Parrot <bpar...@ti.com>
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
.../devicetree/bindings/media/cdns-csi2rx.txt | 98 ++
1 file changed, 98 insertions(+)
create mode 100644 Documentation/d
xed both using the virtual channels and
the data-types, I'm not sure representing it using only muxed pads
like you did would work.
And I don't really know what a good stop gap measure would be either.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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hould I be working in sunxi-next I wonder?
I'd rather stick on 4.14. sunxi-next wouldn't bring any benefit, and
we want to provide something that works first, and always merging next
will always distract us from the actual code.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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