Re: [PATCH v6 6/8] v4l: xilinx: Add Xilinx Video IP core

On 03/09/2015 09:09 PM, Laurent Pinchart wrote: Hi Hans, Thank you for the review. On Wednesday 04 March 2015 16:11:43 Hans Verkuil wrote: Hi Laurent, Almost OK :-) Great :-) Two small issues remain, see below. On 03/04/15 15:51, Laurent Pinchart wrote: Xilinx platforms have no

Re: [PATCH v6 6/8] v4l: xilinx: Add Xilinx Video IP core

Hi Hans, Thank you for the review. On Wednesday 04 March 2015 16:11:43 Hans Verkuil wrote: Hi Laurent, Almost OK :-) Great :-) Two small issues remain, see below. On 03/04/15 15:51, Laurent Pinchart wrote: Xilinx platforms have no hardwired video capture or video processing

[PATCH v6 6/8] v4l: xilinx: Add Xilinx Video IP core

Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that

Re: [PATCH v6 6/8] v4l: xilinx: Add Xilinx Video IP core

Hi Laurent, Almost OK :-) Two small issues remain, see below. On 03/04/15 15:51, Laurent Pinchart wrote: Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular