Re: [PATCH v4 01/17] x86/mpx: Do not use SIB index if index points to R/ESP

2017-02-22 Thread Peter Zijlstra
On Wed, Feb 22, 2017 at 10:36:50PM -0800, Ricardo Neri wrote: > + /* > + * A negative offset generally means a error, except > + * -EDOM, which means that the contents of the register > + * should not be used as

[PATCH v4 16/17] x86: Enable User-Mode Instruction Prevention

2017-02-22 Thread Ricardo Neri
User_mode Instruction Prevention (UMIP) is enabled by setting/clearing a bit in %cr4. It makes sense to enable UMIP at some point while booting, before user spaces come up. Like SMAP and SMEP, is not critical to have it enabled very early during boot. This is because UMIP is relevant only when

[PATCH v4 15/17] x86/traps: Fixup general protection faults caused by UMIP

2017-02-22 Thread Ricardo Neri
If the User-Mode Instruction Prevention CPU feature is available and enabled, a general protection fault will be issued if the instructions sgdt, sldt, sidt, str or smsw are executed from user-mode context (CPL > 0). If the fault was caused by any of the instructions protected by UMIP,

[PATCH v4 11/17] x86/insn-eval: Add support to resolve 16-bit addressing encodings

2017-02-22 Thread Ricardo Neri
Tasks running in virtual-8086 mode or in protected mode with code segment descriptors that specify 16-bit default address sizes via the D bit will use 16-bit addressing form encodings as described in the Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2A Section 2.1.5. 16-bit

[PATCH v4 14/17] x86/umip: Force a page fault when unable to copy emulated result to user

2017-02-22 Thread Ricardo Neri
fixup_umip_exception will be called from do_general_protection. If the former returns false, the latter will issue a SIGSEGV with SEND_SIG_PRIV. However, when emulation is successful but the emulated result cannot be copied to user space memory, it is more accurate to issue a SIGSEGV with

[PATCH v4 05/17] x86/insn-eval: Add utility function to get segment selector

2017-02-22 Thread Ricardo Neri
When computing a linear address and segmentation is used, we need to know the base address of the segment involved in the computation. In most of the cases, it will be sufficient to use USER_DS, which has a base of 0. However, it may be possible that a user space program defines its own segments

[PATCH v4 08/17] x86/insn-eval: Add functions to get default operand and address sizes

2017-02-22 Thread Ricardo Neri
These functions read the default values of the address and operand sizes as specified in the segment descriptor. This information is determined from the D and L bits. Hence, it can be used for both IA-32e 64-bit and 32-bit legacy modes. For virtual-8086 mode, the default address and operand sizes

[PATCH v4 04/17] x86/insn-eval: Add utility functions to get register offsets

2017-02-22 Thread Ricardo Neri
The function insn_get_reg_offset takes as argument an enumeration that indicates the type of offset that is returned: the R/M part of the ModRM byte, the index of the SIB byte or the base of the SIB byte. Callers of this function would need the definition of such enumeration. This is not needed.

[PATCH v4 06/17] x86/insn-eval: Add utility function to get segment descriptor

2017-02-22 Thread Ricardo Neri
The segment descriptor contains information that is relevant to how linear address need to be computed. It contains the default size of addresses as well as the base address of the segment. Thus, given a segment selector, we ought look at segment descriptor to correctly calculate the linear

[PATCH v4 17/17] selftests/x86: Add tests for User-Mode Instruction Prevention

2017-02-22 Thread Ricardo Neri
Certain user space programs that run on virtual-8086 mode may utilize instructions protected by the User-Mode Instruction Prevention (UMIP) security feature present in new Intel processors: SGDT, SIDT and SMSW. In such a case, a general protection fault is issued if UMIP is enabled. When such a

[PATCH v4 03/17] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel

2017-02-22 Thread Ricardo Neri
Other kernel submodules can benefit from using the utility functions defined in mpx.c to obtain the addresses and values of operands contained in the general purpose registers. An instance of this is the emulation code used for instructions protected by the Intel User-Mode Instruction Prevention

[PATCH v4 10/17] insn/eval: Incorporate segment base in address computation

2017-02-22 Thread Ricardo Neri
insn_get_addr_ref returns the effective address as defined by the section 3.7.5.1 Vol 1 of the Intel 64 and IA-32 Architectures Software Developer's Manual. In order to truly give the linear address, we must add the effective address to the segment base as described by the segment descriptor. In

[PATCH v4 02/17] x86/mpx: Do not use R/EBP as base in the SIB byte with Mod = 0

2017-02-22 Thread Ricardo Neri
Section 2.2.1.2 of the Intel 64 and IA-32 Architectures Software Developer's Manual volume 2A states that when a SIB byte is used and the base of the SIB byte points to R/EBP (i.e., base = 5) and the mod part of the ModRM byte is zero, the value of such register will not be used as part of the

[PATCH v4 01/17] x86/mpx: Do not use SIB index if index points to R/ESP

2017-02-22 Thread Ricardo Neri
Section 2.2.1.2 of the Intel 64 and IA-32 Architectures Software Developer's Manual volume 2A states that when memory addressing is used (i.e., mod part of ModR/M is not 3), a SIB byte is used and the index of the SIB byte points to the R/ESP (i.e., index = 4), the index should not be used in the

[PATCH v4 00/17] x86: Enable User-Mode Instruction Prevention

2017-02-22 Thread Ricardo Neri
This is v4 of this series. Again, it took me a while to complete the updates as support for 16-bit address encodings for protected mode required extra rework. The two previous submissions can be found here [1], here [2] and here [3]. === What is UMIP? User-Mode Instruction Prevention (UMIP) is a

[PATCH v4 13/17] x86: Add emulation code for UMIP instructions

2017-02-22 Thread Ricardo Neri
The feature User-Mode Instruction Prevention present in recent Intel processor prevents a group of instructions from being executed with CPL > 0. Otherwise, a general protection fault is issued. Rather than relaying this fault to the user space (in the form of a SIGSEGV signal), the instructions

[PATCH v4 09/17] x86/insn-eval: Do not use R/EBP as base if mod in ModRM is zero

2017-02-22 Thread Ricardo Neri
Section 2.2.1.3 of the Intel 64 and IA-32 Architectures Software Developer's Manual volume 2A states that when the mod part of the ModRM byte is zero and R/EBP is specified in the R/M part of such bit, the value of the aforementioned register should not be used in the address computation. Instead,

[PATCH v4 07/17] x86/insn-eval: Add utility function to get segment descriptor base address

2017-02-22 Thread Ricardo Neri
With segmentation, the base address of the segment descriptor is needed to compute a linear address. The segment descriptor used in the address computation depends on either any segment override prefixes in the in the instruction or the default segment determined by the registers involved in the