Hi Paul,
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of Paul Walmsley
Sent: Saturday, June 21, 2008 4:44 AM
To: linux-omap@vger.kernel.org
Subject: [PATCH 0/2] Add clock post-rate-change notifier
This series adds a clock rate change notifier
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
---
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
drivers/i2c/chips/Makefile|2 +-
drivers/i2c/chips/twl4030-power.c | 337 +
2 files changed, 338 insertions(+), 1 deletions(-)
create mode 100644 drivers/i2c/chips/twl4030-power.c
diff
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/plat-omap/Kconfig |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index d7b34ff..6f891b7 100644
--- a/arch/arm/plat-omap/Kconfig
+++
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
---
The following patch set introduces support for the OMAP3 SYS_OFF_MODE
signal. This will cause a properly programmed triton2 to shutdown the
VDD1 and VDD2 regulators when both core and MPU powerdomain are in off
state. The patches includes programming triton2 with the appropriate
scripts for the
Hi,
style comments inlined.
On Mon, Jul 21, 2008 at 07:02:02PM +0300, Peter 'p2' De Schrijver wrote:
+#define OFFMODE_POL (13)
add spaces after 1 and before 3 (1 3)
-
unnecessary change ?!?
--
balbi
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On Mon, Jul 21, 2008 at 07:02:05PM +0300, Peter 'p2' De Schrijver wrote:
+/*
+*Power Bus Message Format
+*
+*Broadcast Message (16 Bits)
+*DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
+*RES_STATE[3:0]
+*
+*Singular Message (16 Bits)
+*
On Wed, Jul 16, 2008 at 06:19:05PM +0300, Tony Lindgren wrote:
I'm reposting the series to a wider audience as Russell King suspected that
other archs may be interested in reviewing these too, or at least some
parts of the code.
It would be nice to have some comment on these patches from other
Hello Peter,
On Fri, 18 Jul 2008, Peter 'p2' De Schrijver wrote:
On Thu, Jul 17, 2008 at 07:34:52PM -0600, ext Paul Walmsley wrote:
TWL4030 interrupt status register bits can be cleared in one of two ways:
either by reading from the register, or by writing a 1 to the
appropriate bit(s) in
On Fri, 18 Jul 2008, Felipe Balbi wrote:
On Thu, 17 Jul 2008 20:15:51 -0600, Paul Walmsley [EMAIL PROTECTED] wrote:
+ * Results the result of operation - 0 is success
I suppose you mean Returns here.
thanks Felipe, fixed.
- Paul
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